TW545099B - Bump forming technology with high resolution - Google Patents

Abstract

A bump forming technology with high resolution is disclosed. The invention utilizes a dielectric layer which is preferably a release film and laser or plasma etching, to precisely define the pattern of solder bumps both on a substrate or a wafer so as to form openings with high resolution in the dielectric layer. Solder bumps thereby can be precisely formed on bump pads of the substrate and under bump metal layers of the wafer with high aspect ratio, fine pitch and high density. The invention overcomes alignment problems and high cost of the conventional method which uses a stencil mask or plating method to form solder bumps. The invention also solves the resolution problem of the conventional printing by using photo film defined mask instead of stencil mask method. Furthermore, the invention also solves the problems of high cost and long process time of conventional plating processes by utilizing a squeegee printing method to fill the openings having laser opened high aspect ratio, fine pitch and high resolution with a micro-solder ball powder/paste to form solder bumps.

Description

4 545099 5. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for forming a high-resolution welding bump, particularly a method capable of forming a high aspect ratio (H igh A spect R ati) fine pitch high density Welding bump forming method of high-degree welding bump. 5-2 Background of the Invention: Semiconductor wafers containing integrated circuits are extremely important components in electronic devices. These semiconductor wafers are usually fixed on a substrate with terminals to connect other external circuits. This substrate can be a single-layer metal lead frame or a multilayer printed circuit board. In addition to providing connections to other external circuits of the semiconductor wafer, the substrate also provides mechanical support. The outer coating of the semiconductor wafer can protect the semiconductor wafer from the external environment and the impact of external forces.

Figures A through G show a bump formation method for a conventional packaging process. Referring to FIG. 1A, a component packaging structure before a solder bump is formed is shown. The component packaging structure includes a component 100, a pad 102, a protection layer 104, and a passivation layer. An under bump metal layer 106 (Unbump Metal). As shown in FIG. 1B, in order to form a solder bump on the metal layer 106 under the solder bump, a photoresist layer 108 must be formed on the structure shown in FIG. Then, as shown in FIG. 1C, the photoresist layer 108 is exposed and developed by a photolithography process to expose the metal layer 106 under the solder bump, so that the solder bump can be formed on the metal layer 10 under the solder bump. 6.

Page 6 545099 V. Description of the invention (2) ~-Next, as shown in Figure D of D, a welding bump (Solder) is produced by the process of dipping the R and 11Γ 乂 pen keys with lightning.

Bump) 1 1 0 is formed on the welding bump. The process is complicated and takes a long time to prepare the ghost layer 206. The general plating block is replaced by the welding bump, which has a high Ik cost. Another way to form solder bumps is to use fresh steel paste (the pattern on the Stencil plate must be true ::; the opening on the plate 'provided that the steel-a kind of solder bumps are formed on the butt joint 106 for precise alignment. There is also a method on the printed metal layer 106 which is defined by a photoresist film using the Panting method, but θ is ht ° Fllm Defined degree, which is not suitable for the solution of the photometer and t Directional aspect ratio fw; u

"Fine Pitch, Dipping" Day 1 ^ ttlgh Aspect Ratio) Fresh ridges with fine pitch u. If q 4 does not form a solder joint, the first F picture shows the results of the etch: ghost 1 110 removal of the photoresist layer 108 protective layer 1 104. After the metal layer 1 06 under the positive cup connection bump is exposed to heat and exposed to heat, before the welder advances the welding, the block 110 is formed by reflow (Ref l0w) as shown in Figure -G. . Λ 诒 W! _, Of the above-mentioned traditional packaged A-coat. Yiyi Figure A to Figure _6 The tail formation method has many disadvantages such as the cost of the electroplating process, and the non-bump formation method uses time consuming and high cost. In addition, the photoresist film Z steel plate forms solder bumps that are difficult to align and the steel Printing method is limited. The meaning of the printing (Photo Film Defined is not suitable for the formation of high-resolution photo film). Hlgh AsPect Rat i〇) Fine-pitch soldering 545099 V. Description of the invention (3) In view of the shortcomings of the traditional packaging structure and process described above, it is necessary to develop a novel and progressive structure and process to overcome the traditional structure and process. Disadvantages. The present invention is able to meet such needs. 5-3 Objects and Summary of the Invention: An object of the present invention is to provide a method for forming a solder bump with low cost and streamlined manufacturing process, and a shorter processing time. Another object of the present invention is to provide a method for forming a high aspect ratio welding bump capable of forming a smaller welding bump-to-solder bump pitch. Another object of the present invention is to provide a method for forming a high-resolution solder bump with high alignment accuracy. In the next step of welding, the analysis of the unpacked high-level method is used to form the block and the convex block is sent out. The high-level analysis of the degree is described above.塾 Re-welding has two sets of the first plate number, and there should be the middle one. The circle BB crystals should be combined with each other, and the plate-film-based welding is to prevent the supply and mention the first welding first. 〆The first one Count the first one and protect it in layers. The second layer of the cushion welding body is exposed to the bottom of the block, and the number of the welding is opened on the mouth. The number of the welding is two, and the one of the block is exposed to the welding. First, the first, the first, the first, the second, the number of shifts are turned into a plate-shaped base, and the layer is covered with an electrical layer.

Page 8 545099 5. Description of the invention (4). Then, a solder such as a solder paste or a small solder ball is filled into the first opening and a reflow process is performed. The first dielectric layer is then removed and a second dielectric layer is formed to cover the wafer. The pattern of the plurality of second solder bumps is then transferred into the second dielectric layer to form a plurality of second openings and expose the conductor layer under the solder bumps. Finally, solder such as solder paste or micro solder balls is filled into the second opening and a reflow process is performed. The foregoing brief description of the invention and the following detailed description are examples only and are not limiting. Other equivalent changes or modifications that do not depart from the spirit of the invention should be included in the patent scope of the invention. 5-4 Detailed Description of the Invention: What must be explained here is that the process steps and structures described below do not include a complete process. The present invention can be implemented by various manufacturing methods, and only the manufacturing methods required for understanding the present invention are mentioned here. The following detailed description will be made according to the accompanying drawings of the present invention. Please note that the drawings are in simple form and not drawn to scale, and the dimensions are exaggerated to facilitate understanding of the present invention. In a preferred embodiment of the present invention, the bump forming method is applied to a flip chip package process. The second diagram A to the second diagram and the third diagram A to the third diagram respectively show some of the preferred embodiments of the present invention.

Page 9 545099 V. Description of the invention (5) The process of the substrate (Subs t rat e) part, and the fourth A to fourth G and the fifth A to fifth F graphs show the inclusion product. The manufacturing process of the wafer portion of the bulk circuit wafer. Referring to FIG. 2A, a substrate 200 has a plurality of flip chip bonding pads Flip Chip Bump Pad 20 2 and a solder mask 2 0 4. The solder mask is used to cover and protect the parts other than the solder joints on the substrate, and to prevent solder bumps from being formed on the substrate other than the pads, and at the same time to prevent the circuit wires on the substrate from being attacked by the external environment. The substrate 200 shown in the second A is a non-Solder-Mask-Defined substrate, but the substrate used in the present invention may also be a (Solder- ^ I ask-De efined) substrate. That is, the solder mask covers the entire substrate including the periphery of the bump pads, and only the flat portion of the bump pads are exposed. The solder mask 2 0 4 can be formed by conventional materials and methods, such as photosensitive materials and exposure and development processes. Referring next to FIG. 2B, a dielectric layer 206 is covered on the structure shown in FIG. 2A. The dielectric layer 206 is preferably a release film (^ 6356 F i 1 m). The release film is a dielectric film used in general packaging processes, and is used to prevent the substrate from being contaminated by the external environment during the transportation to the subsequent processes. The release film used in the present invention is used to define the formation position of the solder bump and can be peeled off after the process is completed. Referring to FIG. 2C, the dielectric layer 206 is a release film, and the method of engraving the dielectric 206 is a method of vertical hole processing, such as an anisotropic | full engraving method. Especially in the form of laser perforation (Laser) or plasma; |

Page 10 545099 V. Description of the invention (6)

Plasma Etching) removes the part of the release film on the bump pad 202 to form an opening. Using laser openings or plasma etching can achieve openings precisely aligned to the resolution, so that the solder bumps can be accurately formed on the bump pads, and at the same time, the pitch of the solder bumps can be further reduced (successfully). Ground to form high aspect ratio (high aspect ratio) fine-pitch high-density solder bumps. Next, referring to the second figure D, a soldering horse or a small solder ball (Solder Paste / Solder Powder) 208 is filled into the opening exposing the bump pad 20 / with a Squeegee Printing method. Remove spilled solder paste or tiny solder balls. The solder paste is composed of many small solder balls (Solder Sphere), solvents and fluxes (Flux), and the solder balls are usually tin-lead alloys with eutectic composition. Refer to Figure 2E, Second_Medium The solder paste 208 shown is formed into the solder bump 21 by the re-soldering and cleaning process. However, when using a small solder ball p to add a flux before re-printing after printing, the solder ball bubbles can be reduced. ^ At least in the figure, the dielectric layer 206 is removed, and can be used for etching or electricity: > Moon Wash®. Then, as shown in the second figure G, a re-soldering process can be performed again. Finally As shown in the second H figure, a single pressing: (Coining) process is used to make the top of the solder bump 21 ° flat and coplanar to facilitate access to the solder bump on the wafer. There are 1 third A to The third figure shows the structure of a Ugishi 1-A, a substrate with solder mask I 4 pass, a substrate 300 has a plurality of test electricity from magnetic qnzi and 筮-ηsolid A crystal bonding bump pad 3 0 2 and a circuit structure 304 are provided. The rabbit rabbit knot shown in the second picture B is not on the structure shown in the third picture A.

545099 V. Description of the invention (7) · The results of covering the dielectric layers 3 0 6 and 3 0 7; the dielectric layers 3 0 6 and 3 0 7 are used to define the formation positions of the solder bumps, and the dielectric layer 3 0 6 and 3 0 7 include a non-photosensitive dielectric layer, and the dielectric layer 3 7 is preferably a release film. In addition, an adhesive film can be selectively added between the dielectric layers 306 and 307. Referring to FIG. 3C, the dielectric layers 3 06 and 3 7 are etched to expose the bump pads 3 2. The method of etching the dielectric layers 3 6 and 3 7 can be the traditional vertical direction. The method of the hole processing is, for example, anisotropic etching. The dielectric layer 3 07 is a release film, and the portion of the dielectric layer 3 6 and the release film located on the bump pad 3 2 can be removed by laser opening or plasma etching process. To form an opening. Plasma etching is used to form openings and an etching mask must be applied to the release film. The use of laser drilling or plasma etching can achieve high-resolution and precisely aligned openings, so that solder bumps can be accurately formed on the bump pads, and at the same time, the pitch of the solder bumps can be further reduced, and a high aspect ratio can be successfully formed. Higher density solder bumps than fine pitch. Next, referring to the third figure D, fill the solder paste or micro solder ball 3 0 8 with a doctor blade into the opening where the bump pad 3 2 is exposed, and move the overflowing solder paste or micro solder ball. except. Solder paste consists of many tiny solder balls, solvents and fluxes, and solder balls are usually tin-lead alloys with eutectic composition. Referring to FIG. 3E, solder paste 3 0 8 shown in FIG. 3 D is re-soldered and cleaned to form a solder bump 3 1 0 in the figure. When using micro solder balls, flux must be added before reflow after printing, so that the solder ball bubbles can be minimized. In the third F diagram, the dielectric layer 3 7 is removed and can be used.

Page 12 545099 V. Description of the invention (8) Dry etching or plasma cleaning the surface. Then, as shown in the third G diagram, a reflow process can be performed again. Finally, as shown in the third figure, a flattening process is performed to flatten the tops of the solder bumps 310 and have better coplanarity to facilitate bonding with the solder bumps on the wafer. Figures 4A to 4G show the manufacturing process of a wafer portion including an integrated circuit wafer in a preferred embodiment of the present invention. Referring to FIG. 4A, the present invention shows a component part packaging structure of a wafer including an integrated circuit wafer before the formation of a solder bump. The component part packaging structure of the wafer includes a wafer 4 0, a pad 4 2 (Metal Pad), protection layer 404 (Passivation Layer) and solder bump metal layer 406 (Under Bump Metal). Pad 402 includes aluminum pads, but other material pads should not be excluded. The pads 4 2 can be formed by conventional deposition, lithography and etching processes. The protective layer 4 0 4 can be formed by a conventional method. The protective layer 4 0 4 is etched by a conventional lithography and etching process to form an opening and expose the solder pad 4 2. The metal layer 406 under the solder bump is formed in the opening and on the solder pad 402 by a conventional deposition, lithography and etching process. Referring next to FIG. 4B, a dielectric layer 408 is covered on the structure shown in FIG. 4A. The dielectric layer 408 is preferably a release film. The release film is a dielectric film used in general packaging processes and can be easily peeled off. It can be completely removed after a simple cleaning step. The release film is used to define the formation position of the solder bump. Referring to FIG. 4C, the dielectric layer 408 is opened to expose the metal layer 406 under the solder bump. The dielectric layer 408 is a release film, which can be opened by laser.

Page 13 545099 V. Description of the invention (9) The method of laser or Plasma Etching removes the part of the release film located on the metal layer 4 06 under the solder bump to form Opening. Using laser openings or plasma etching can achieve high-resolution precisely aligned openings, so that the solder bumps can be accurately formed on the metal layer under the solder bumps, and at the same time, the pitch of the solder bumps can be further reduced, and successfully Formation of high aspect ratio (H igh A spect R ati) fine-pitch high-density solder bumps. The Cang Kaodi ’s four-D picture does not use the method of knife printing to fill in the poor or tiny fresh balls (Solder Paste / Solder Powder) 410 into the openings that expose the metal layer 4 0 6 under the solder bumps, and Remove spilled solder paste or tiny solder balls. The solder paste is composed of many tiny balls or solder powder (S ο 1 der P 〇wder), solvent and flux (flux) (F1 ux), and the solder ball is usually eutectic into the knife of the tin thermal alloy 0 cleaning must For the most dielectric, it can make 1 stepping knotting, knotting

Referring to FIG. 4E, the solder paste 4 1 0 shown in FIG. 4 D is re-soldered to form a solder bump 4 1 2 in the figure. When using tiny solder balls, add flux before printing and reflow, which can reduce the solder ball bubbles. In the fourth F diagram, if the dielectric layer 408 is a release film, the layer ^ 0 8 can be easily removed (and may not be removed if necessary), but if the dielectric layer 408 is dielectric, The material is removed by plasma etching or stripped by chemical liquid, and the surface is cleaned by dry etching or plasma. Then, as shown in the fourth figure G, a reflow process is performed again to form the pattern shown in the figure. When proceeding with the packaging process, the wafer part components shown in the fourth G diagram are shown in the first G diagram or the second part in the second G diagram. Welding bump 4 丨 2 and the second or third picture

Page 14 545099 V. Description of the invention The solder bumps 2 1 0 or 3 1 0 are aligned and soldered (S 1 d e r i n g) for the next process of flip chip packaging. 5A to 5F show the manufacturing process of a wafer portion including a bulk circuit wafer in a preferred embodiment of the present invention. Referring to FIG. 5A, it is shown that the present invention includes a wafer portion and a component packaging structure of an integrated circuit wafer before a solder bump is formed. The wafer portion of the component packaging structure includes a wafer 5 070 pad 5 0 2 Protective layer 5 0 4, Metal layer 5006 under the solder bump, 'Dry, dielectric layer ⑽5.9 is used to define the formation of solder bump,

5 0 8 and 5 0 9 include non-photosensitive dielectrics [and the dielectric layer 502 H is excellent. In addition, the dielectric layer can be optionally added between the 508 and 509, t film. The pad 502 contains fresh aluminum, which is made of beans: the pad is staked with traditional deposition kernels. The protective layer 504 can be formed by conventional methods, and only consumes c-shaped lithography and etching. 2. welding

s 出 ί ::: Fifth, as shown in the fifth Γ, the dielectric layers 508 and 509 are engraved with the following metal layer 506, and the dielectric layers 508 and 509 are etched: human thunder; direction hole processing The method 'for example, anisotropic etching An ur is a release film, you can laser open the hole or the metal / 22 Γ to remove the dielectric layer 5 08 and the release film located on the solder bump lower layer 06 Part to form an opening. Use the process of engraving

Page 15 545099 5. Description of the invention (11) An etching mask must be applied to the release film to form the opening. The use of laser drilling or plasma etching can achieve high-resolution and precisely aligned openings, so that solder bumps can be accurately formed on the bump pads, and at the same time, the pitch of the solder bumps can be further reduced, and a high aspect ratio can be successfully formed. Higher density solder bumps than fine pitch. Then, referring to the fifth figure c, fill the solder paste or micro solder balls 5 1 0 into the openings that expose the metal layer 5 06 under the solder bumps by scraper printing, and fill the solder paste or micro solder with overflow. The ball is removed. The solder paste is composed of many tiny solder balls or solder powders (So 1 der Powder), solvent and flux (, J: flux) (F 1 ux), and the fresh balls are usually eutectic tin thermal alloys. Φ Then refer to the fifth D chart, the solder paste 5 1 0 shown in the fifth C chart is re-soldered and cleaned to form the solder bump 5 1 2 in the figure. When using tiny solder balls, flux must be added before reflow after printing, so that the solder ball bubbles can be minimized. Then referring to the fifth figure E, the dielectric layer 509 is removed, and the surface can be cleaned by dry etching or plasma. Then, as shown in Figure 5F, a reflow process can be performed to form the pattern shown in the figure. In the further packaging process, the component packaging structure of the wafer part shown in the fifth figure F is combined with the packaging structure of the substrate part shown in the second figure or the third figure. The solder bumps 5 1 2 and the solder bumps 210 or 3 10 in the second or third drawing are aligned for soldering in order to perform the next flip-chip packaging process.

Page 16 545099 V. Description of the invention (12) In a preferred embodiment of the present invention, the dielectric layer, especially the way of opening and laser openings, or the lightness of the plasma rhyme is used to precisely determine the standing & The formation position of the solder bumps on the mold and the solder bumps on the wafer can form high-resolution and precisely aligned openings in the electrical layer of the substrate, so that the solder bumps are formed between the bump pads and the pads formed on the substrate. The solder bumps on the wafer are accurately deposited, and at the same time, the pitch of the solder bumps can be further reduced, and successfully formed = high aspect ratio (H igh A spect R ati) fine pitch high density fresh bumps $ Fiber can also overcome the use of steel (Stencil Mask) formation | continued ^ & dirt ghost " success of alignment and high cost of steel (Stencil Mask) problems can be created and solved by traditional photoresist film definition printing The (Photo Fiim Defined M Printing) method is limited by the resolution of the Photo Film and it is difficult to form high-aspect ratio fine-pitch fresh bumps or pads. In addition, 'Using solder paste or tiny solder balls to fill high aspect ratio (high aspect rat io) fine pitch high density and high resolution fine-aligned openings to form solder bumps can solve the traditional formation of glow joints by electroplating The problem of bumps being time consuming and costly. The above detailed description of the invention is merely an example and not a limitation. Other equivalent changes or modifications not falling within the spirit of the present invention are within the scope of the patent.

Page 545099 Brief description of the drawings In order to make the other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Figure A shows the device package structure before a solder bump is formed; Figure B shows the result of forming a photoresist layer on the device package structure shown in Figure A; Figure C shows the exposed photoresist layer The result of exposing the metal layer under the solder bump is shown in FIG. 1. The first D image shows the result of forming a solder bump on the metal layer under the solder bump. The first E image shows the result of removing the photoresist layer. The first F image The result of etching the metal layer under the solder bump to expose the protective layer is shown. The first graph G shows the result of reflow soldering of the solder bump. The second graph A shows a substrate with a plurality of flip-chip bonding bump pads and one Solder mask; 1 Page 18 545099 Brief description of the diagram Second diagram B shows the result of covering a dielectric layer on the structure shown in second A; second diagram C shows the dielectric layer is etched to expose the protrusions The result of the block pad is shown in the second D graph. The result of filling the paste or micro solder balls into the openings that expose the bump pads and removing the overflowing solder paste or micro solder balls; Figure 2E shows the solder paste or tiny solder shown in Figure 2D The result of the ball forming a solder bump after the reflow process; the second graph F shows the result of removing the dielectric layer; the second graph G shows the result of another reflow process; the second graph shows a flattening process The result of flattening the top of the solder bump; the third diagram A shows a substrate with a plurality of flip-chip bonding bump pads and a circuit structure; the third diagram B shows the structure shown in FIG. Photosensitive 11 Page 19 545099 The diagram briefly illustrates the results of the dielectric layer. Figure 3c shows the results of the two non-photosensitive dielectric layers being etched to expose the bump pads. Figure 3D shows the solder paste or The result of filling the solder balls into the openings that expose the bump pads and removing the overflowing solder paste or solder balls; Figure 3E shows the solder paste or solder balls shown in Figure 3D. Results of solder bump formation during reflow process; Figure 3 F shows shift of the release film dielectric layer The third graph G shows the results of another reflow process; the third graph shows the results of a flattening process to flatten the top of the solder bumps; the fourth graph A shows a wafer containing integrated circuit wafers Partial component package structure; Figure 4B shows the result of covering a dielectric layer on the structure shown in Figure 4A; page 545099 diagrams briefly explain Figure 4c shows the dielectric layer is etched to expose The result of soldering the metal layer under the bump; the fourth D image shows the result of filling the solder paste or micro solder ball into the opening exposing the metal layer under the solder bump and removing the overflowing solder paste or micro solder ball. Figure E shows the results of solder bumps or tiny solder balls shown in Figure 4D forming solder bumps after the reflow process;

Figure 4F shows the results of removing the dielectric layer. Figure 4G shows the results of another reflow process to form the type shown in the figure. Figure 5A shows the part of the wafer containing the integrated circuit wafer Device package structure; Figure 5B shows the result of etching the non-photosensitive dielectric layer shown in Figure 5A to expose the metal layer under the solder bump; Figure 5C shows the solder paste or micro solder balls The result of filling into the opening that exposes the metal layer under the solder bump and removing the overflowing solder paste or tiny solder balls;

Page 545099 Brief description of the diagram The fifth diagram D shows the results of solder bumps formed by the re-soldering process of the solder paste or micro solder balls shown in the fifth diagram C; the fifth E diagram shows the release film dielectric layer The results of the removal; and the fifth F chart shows the results of another reflow process. Representative symbols of the main parts: 1 0 0 component 1 0 2 solder pad 1 0 4 protective layer 1 0 6 solder metal layer under the bump 1 0 8 photoresist layer welding 1 1 0 bump 2 0 0 substrate 2 0 2 flip chip Bonding pads 2 0 4 Solder mask 2 0 6 Dielectric layer _ 2 0 8 Solder paste or micro solder balls 2 1 0 Soldering bumps 3 0 0 Substrate 3 0 2 Chip bonding pads 3 0 4 Circuit configuration

Page 22 545099 Brief description of the drawing 3 0 6 Dielectric layer 3 0 7 Dielectric layer 3 0 8 Solder paste or micro solder ball 3 1 0 Solder bump 4 0 0 Wafer 4 0 2 Pad 4 4 Protective layer 4 0 6 Solder bump metal layer 4 0 8 Dielectric layer 4 1 0 Solder paste or micro solder ball 4 1 2 Solder bump 5 0 0 Wafer 5 0 2 Solder pad 5 0 4 Protective layer 5 0 6 Solder bump Metal layer 5 0 8 Dielectric layer 5 0 9 Dielectric layer 5 1 0 Solder paste or micro solder ball 5 1 2 Solder bump

Page 23

Claims (1)

545099 6. Application Patent Scope 1. A method for forming a high-resolution solder bump, the method for forming a high-resolution solder bump includes: providing a substrate, wherein the substrate has a plurality of solder pads and a solder mask; forming a A release film covers the substrate; a pattern of a plurality of solder bumps is transferred into the release film to form a plurality of openings and expose the solder pads by a vertical hole-opening method; solder is filled into the openings; A reflow process is performed on the substrate to form a plurality of solder bumps; the release film is removed; and a flattening process is performed on the solder bumps. 2. The method for forming a high-resolution solder bump as described in item 1 of the scope of the patent application, wherein the substrate includes a solder mask to define the substrate. 3. The method for forming a high-resolution solder bump as described in item 1 of the scope of the patent application, wherein the substrate includes a non-solder mask-defined substrate. 4. The method for forming a high-resolution solder bump as described in item 1 of the scope of the patent application, wherein the above-mentioned vertical hole processing method includes a laser hole method. 5. The method for forming a high-resolution solder bump as described in item 1 of the scope of the patent application, wherein the above-mentioned method for processing the vertical hole includes plasma etching Page 24 545099 VI. Method of Patent Application Scope 0 The convex-blade welded welding knife of a square-shaped block is scraped to analyze the high-blade welding dagger, the iid derivative, or the 1-I ancient Tth welding enclosure. For the post-secondary, please ask Zhongshen Qiru. The 6 way method is a dry-shaped one-row convex splice plate. The welding base should be analyzed and resolved, and the higher one should be removed. Item form 1 off the table of the base of the board around the general description of the washing up school <Kuta Tachibana asks Cheng Chengshen to make D rnuj. Shi, Hai 7 method etch 8 square back to form a row of convex welding plate welding Fundamentals should be resolved, and the high-level descriptive shifts the membrane form ^ • Fan Shuli from Di Gaowei should be invited. Analysis of the welding degree of Shen Qicheng's convex welded joints. The solution to the problem of high welding is to explain the details or items of the paste. 1 Fresh is the range of materials that can be used for welding. Please apply for it. The 9 method of convex welding analysis analyzes the high degree of convex welding of this method. With unpacked high-precision method Fang Yicheng • Shape ο 1 piece Φ ^ ___ I film shape; 0 塾 a welding and number of plates based on the cover with the upper layer of the dielectric base of the medium light; its sense layer, non The electric plate, a substrate, a form of light, and a sense of sequential light are lifted. The joint opening of the cover is not convex, and a plurality of plural pieces are welded to form a complex shape. Enter the case directly from the square of the membrane Page 25 545099 6. The scope of the patent application exposes the solder pad; fills the solder into the opening; performs a re-soldering process on the substrate to form a plurality of solder bumps; removes the release film; and the solder bumps Perform a flattening process. 11. The method for forming a high-resolution solder bump as described in item 10 of the scope of the patent application, wherein the above-mentioned method for processing the vertical hole includes a laser hole method. 1 2. The method for forming a high-resolution solder bump as described in item 10 of the scope of the patent application, wherein the above-mentioned vertical hole processing method includes a plasma etching method. 1 3. The method for forming a high-resolution solder bump as described in item 10 of the scope of the patent application, wherein the solder paste or micro solder balls mentioned above are filled by doctor blade printing. 1 4. The method for forming a high-resolution solder bump as described in item 10 of the scope of patent application, wherein after the release film is removed, a dry # etch process is performed on the substrate to clean the surface of the substrate. 1 5. The method for forming a high-resolution solder bump as described in item 10 of the scope of patent application, wherein when the release film is removed, the substrate is performed once. Page 26 545099 6. Scope of patent application Reflow soldering process. 16. The method for forming a high-resolution solder bump according to item 10 of the scope of the patent application, wherein the solder may be a solder paste or a micro solder ball. 1 7. —A method for forming a high-resolution welding bump, the method for forming a high-resolution welding bump includes: Provide a wafer, wherein the wafer has a plurality of bonding pads, a protective layer having a plurality of openings to expose the bonding pads, and a plurality of solder bump under conductor layers (UBM) on the bonding pads; forming a A non-photosensitive dielectric layer covers the wafer; a pattern of a plurality of solder bumps is transferred into the dielectric layer by a method of vertical opening processing to form a plurality of openings and expose the conductor layer under the solder bumps; Filling the opening with solder; performing a reflow process on the wafer to form a plurality of solder bumps; and removing the dielectric layer. 18. The method for forming a high-resolution solder bump according to item 17 in the scope of the patent application, wherein the non-photosensitive dielectric layer described above includes a release film. 19. The method for forming a high-resolution solder bump according to item 17 in the scope of the patent application, wherein the above-mentioned method for processing the hole in the vertical direction includes laser opening. Page 27 545099 6. Scope of patent application Hole method. 20. The method for forming a high-resolution solder bump as described in item 17 of the scope of the patent application, wherein the above-mentioned vertical hole processing method includes a plasma etching method. 2 1. The method for forming a high-resolution solder bump as described in item 17 of the scope of the patent application, wherein the solder paste or micro solder balls mentioned above are filled by doctor blade printing. 2 2. The method for forming a high-resolution solder bump as described in item 17 of the scope of the patent application, wherein after the dielectric layer is removed, a dry #etch process is performed on the wafer to clean the surface of the wafer . 2 3. The method for forming a high-resolution solder bump as described in item 17 of the scope of patent application, wherein after the dielectric layer is removed, a reflow process is performed on the wafer. 24. The method for forming a high-resolution solder bump according to item 17 in the scope of the patent application, wherein the solder may be a solder paste or a micro solder ball. 2 5. —A method for forming a high-resolution solder bump, the method for forming a high-resolution solder bump includes: providing a wafer, wherein the wafer has a plurality of solder pads, Page 28 545099 VI. Patent application: Multiple openings to expose the protective layer of the pad and the conductor layer under the solder bump on the pad; sequentially forming a non-photosensitive dielectric layer to cover the wafer And a release film covering the non-photosensitive dielectric layer; transferring a pattern of a plurality of solder bumps into the release film and the non-photosensitive dielectric layer to form a plurality of openings by exposing a vertical hole; A conductor layer under the solder bump; filling solder into the opening; performing a reflow process on the wafer to form a plurality of solder bumps; and removing the release film. 26. The method for forming a high-resolution solder bump according to item 25 of the scope of the patent application, wherein the above-mentioned vertical hole processing method includes a laser hole method. 27. The method for forming a high-resolution solder bump as described in item 25 of the scope of the patent application, wherein the above-mentioned vertical hole processing method includes a plasma etching method. 2 8. The method for forming a high-resolution solder bump as described in item 25 of the scope of the patent application, wherein the solder paste or micro solder balls mentioned above are filled by doctor blade printing. 2 9 .High-resolution solder bump formation as described in item 25 of the scope of patent application 545099 6. Method for applying for a patent, wherein after the release film is removed, a dry I-worm process is performed on the wafer to clean the surface of the wafer. 30. The method for forming a high-resolution solder bump as described in item 25 of the scope of the patent application, wherein after the release film is removed, a reflow process is performed on the wafer. 31. The method for forming a high-resolution solder bump according to item 25 of the patent application scope, wherein the solder may be a solder paste or a micro solder ball. Page 30