TW544742B - Semiconductor device and method of production of same - Google Patents
Semiconductor device and method of production of same Download PDFInfo
- Publication number
- TW544742B TW544742B TW091110671A TW91110671A TW544742B TW 544742 B TW544742 B TW 544742B TW 091110671 A TW091110671 A TW 091110671A TW 91110671 A TW91110671 A TW 91110671A TW 544742 B TW544742 B TW 544742B
- Authority
- TW
- Taiwan
- Prior art keywords
- external connection
- semiconductor
- semiconductor device
- wires
- connection terminals
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 153
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 239000004020 conductor Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 50
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 50
- 229910052802 copper Inorganic materials 0.000 claims description 41
- 239000010949 copper Substances 0.000 claims description 41
- 229910052737 gold Inorganic materials 0.000 claims description 24
- 239000010931 gold Substances 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 10
- 235000012431 wafers Nutrition 0.000 description 34
- 238000007747 plating Methods 0.000 description 21
- 239000011347 resin Substances 0.000 description 15
- 229920005989 resin Polymers 0.000 description 15
- 238000005516 engineering process Methods 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 12
- 229910000679 solder Inorganic materials 0.000 description 10
- 238000002161 passivation Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 229910000831 Steel Inorganic materials 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 239000010959 steel Substances 0.000 description 3
- 238000007751 thermal spraying Methods 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000012467 final product Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000000746 purification Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
- H01L2224/02311—Additive methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02377—Fan-in arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05166—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05171—Chromium [Cr] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1182—Applying permanent coating, e.g. in-situ coating
- H01L2224/11825—Plating, e.g. electroplating, electroless plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/1356—Disposition
- H01L2224/13562—On the entire exposed surface of the core
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/1357—Single coating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13575—Plural coating layers
- H01L2224/1358—Plural coating layers being stacked
- H01L2224/13584—Four-layer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13655—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/13664—Palladium [Pd] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Description
544742 A7 ^--B7___ 五、發明説明(1 ) 發明背景 1·發明領域 本發明關於半導體元件和其製造方法,特別是關於藉 由在半導體晶圓的電極形成表面上形成外部連接端子而製 造出半導體元件和其製造方法。 2·相關技術說明 第12A至121圖顯示半導體元件的製造方法,該半導體 疋件在半導體晶圓的電極形成表面上形成有金屬柱作為外 部連接端子。在此製造方法中,首先,電極12被暴露出, 且半導體晶圓10中被鈍化膜14覆蓋的半導體晶圓1〇的電極 形成表面(第12Α圖),以喷鍍方式被覆蓋有導電層16(第12β 圖)。接著,導電層16的表面被光敏電阻18覆蓋(第12C圖), 然後,光敏電阻18被曝光和顯影,以便暴露出用以在導電 層16表面形成互接圖案的部份(第12D圖)。 電極12以極高密度被排列在例如半導體晶圓1〇的電 極形成表面的周緣。如第12E圖所示,藉由以銅電鍍導電 層16的暴露表面,來形成互接圖案20。互接圖案20從電極 12被引出而形成,以便確保外部連接端子的配置空間。 接著,光敏電阻18被移除且互接圖案20和導電層16的 表面用乾燥膜22覆蓋(第12F圖)。此乾燥膜22用來形成銅柱 24,該銅柱形成外部連接端子(第12G圖)。乾燥膜22被曝光 和顯影’以形成孔洞,用以在互接圖案2〇上形成銅柱24的 部份進行電鍍。藉由以銅電鍍這些部位,銅積聚在電鍍孔, 而形成向度約為1 〇〇 # m的金屬柱24。 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 4 (請先閱讀背面之注意事項再填寫本頁) 、? 544742 A7 —---------— B7 五、發明説明(2 ) ^^ --一~〜 接著,銅柱24的表面被依序電錢祕、把等,以形 障礙層26。 乾燥膜22被移除,然後導電層16中暴露於電極形成表 面的部份’藉敍刻而移除(第12H圖)。以此方式,半導體晶 圓1〇的電極形成表面被形成有銅柱24,銅柱24透過互接: 案2 0與電極12電性連接。 ° 、接著,如第121圖所示,半導體晶圓10的電極形成表面 被覆蓋有樹脂28進行密封。樹脂28被形成為大致相同於鋼 柱24的厚度。銅柱24的端表面被暴露於樹脂以表面。在樹 脂密封之後,焊球被放置於障礙層26表面,且焊料被做成 可逆流,以便形成焊料突起(未顯示)。最後,半導體晶圓 10可被沿著樹脂28切成小方塊,以得到晶片尺寸的半導體 元件。 丑 第13A至131圖顯示用來製造晶片尺寸的半導體元件 的另一方法。由此製造方法得到的半導體元件具有用來作 為外部連接端子之彎曲成L形的金線。第13A至UE圖所示 步驟基本上與上述第12A至12E圖所示步驟沒有不同。然 而,在此方法中,互接圖案20未被樹脂密封。互接圖案2〇 藉金鍍層而形成,以便使互接圖案能夠被維持在半導體元 件的外部表面暴露出。 如第13F圖所示,光敏電阻18(第13]£圖)被移除。接著, 如第13G圖所示,電極形成表面被電阻所覆蓋,然後,孔 3〇a形成於互接圖案20中,在之後金線連結的部份。電極形 成表面被電阻30覆蓋,以便在連結金線之後用強化鍍層只 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐)
»· ·', (請先閱讀背面之注意事^再填寫本頁) 、!· 544742 五、發明説明( 覆蓋住金線外表面。如第13H圖所示,金線被連結到互接 圖案20與開口 3〇a對齊(第13G圖)。接著,金線被彎成L形, 且其端部被切掉,以形成外部連接端子32。金線的外表面 被電鍍,以便強化金線(鍍層材料未顯示於圖中),然後, 電阻30被移除,且如第131圖所示,導電層16的暴露部份藉 姓刻而移除。 以此方式,半導體晶圓10的電極形成表面被形成有外 部連接端子32,其透過互接圖案2〇被電性連接到電極12。 最後,半導體晶圓10被切割成小方塊,以便得到被提供有 外部連接端子32的半導體元件,該外部連接端子係由彎成 L形的導線所構成。 在上述第12A至121圖以及第13A至131圖所示的例子 二導電層16被形成於鈍化膜14上,但是亦可能以聚醯亞 胺膜來覆蓋鈍化膜14,並在聚醯亞胺膜表面上形成導電層 16。 a 一用以利用上述銅柱作為外部連接端子的製造半導體 元件的步驟’以及利用彎成㈣的金線作為外部連接端子 的製造半導體元件的步驟被顯示於第⑷小圖。該等步 製造晶片尺寸的半導體元件,其係藉由加工半導體晶圓 形成電性連接於形成於其上的電極端子的外部連接端子 然後切割該半導體晶圓而達成。以此方式,習知技術的々 法利用複雜的步驟,所以問題在於製造效率降低且製造成 本增加。 而且,當將以習知技術的製造方法製出的半導體元件
本紙張尺度適用中國國家標準(CNS) Α4規格(210X297公D 6 驟 以 方
—--------— (請先閱讀背面之注意事項再填寫本頁) •、可I 544742 五、發明説明(4 ) =::Γ時,已有的下述問題在於:當將-使用銅柱 2外錢接端子的半導體^件以料安裝時,焊料不會 m:且外部連接端子不會可靠地連結於電路板。 件,其中該半導體元件被提供有藉彎曲 孟線駐形而形成外部連接端子時,部份由於外部連接端 子的高度約為700至綱㈣,所以半導體元件和電路板被 互相隔開地連結著。 本發明之總結 本發明用來解決習知技術中,藉加工半導體晶圓來製 ,半導體元件的製造方法中的問題。本發明之一目的在於 提供相當可靠的半導體元件,能夠藉較簡單方法來製出, 因而能夠提高製造效率,且能夠以較高密度配置外部連接 端子,因而能夠處理較多數目的銷,及其製造方法。 奴達成上述目的,根據本發明之一態樣,提供一種半 導體元件,其被提供有形成於半導體基體上的諸如電晶體 的半‘體組件’將该等組件連接到一外部電路的外部連接 端子’及將該等半導體組件的電極連接到該等外部連接端 子的互接圖案,其中該等外部連接端子係由含有導電材料 的導線所形成,而且該等導線之連結於該等互接圖案的部 份,被埋在形成該等互接圖案的該金屬層中。 形成互接圖案的金屬層較佳地被銅鍍層、金鍍層之類 形成。 ^ 作為形成外部連接端子的導電材料的導線,較佳的是 使用金線、銅線等。 本紙張尺度適用中國國家標準(CNS) A4規格(21〇x297公爱) 544742 五 發明說明 車父佳地’金屬層和導線由相同材料製造出。所以,較 也二金屬層藉金制而形成,且導線由金構成,或者金 •層藉鋼鍍層而’形成,導線由銅構成。 〆 覆蓋外部連接端子可被形成互接圖案的金屬層的材料所 半導體元件中形成互接圖案的表面可被密封,以便留 下外部連接端子暴露出。 根據本發明之第二態樣,提供一種半導體元件製造方 …该半導體元件被提供有形m導體基體的半導體 、’且件’將該等組件連接到一外部電路的外部連接端子,及 將半導體組件的電極連接到外部連接端子的互接圖案,該 訂 方法包含的㈣為:在半導縣體切成電極的整個表面 成I電層’在V電層的表面上形成—電阻圖案,留 下導電層的某些部份暴露出’該等部份為外部連接端子將 破連接到塾的部份以及欲形成互接圖案的部份;將含有導 電材料的導線,在欲形成塾的部份連結到導電層,以便形 成外部連接端子;在導電層的暴露部份形成一金屬層;移 除該電阻;及移除因移除電阻而暴露出的導電層,以便形 成該等互接圖案。 的 在形成互接圖案之後,半導體元件中形成互接圖案 表面被密封,以便留下外部連接端子暴露出。 圖式簡要說明 圖 本發明的這些和其他目的及特徵,將由下述關於附 所給予的較佳實施例的說明而變得更清楚,其中: 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 五、發明説明(6 ) 丰導 丰V體7G件的製造方法的圖式; 丰導„為用來解釋根據本發明之第二實施例的 半V體7〇件的製造方法的圖式;
、第®為根據本發明之第一實施例的半導體元件的製 造方法的流程圖; X 第4圖為根據本發明的第二實施例的半導體元件的製 造方法的流程圖; ^ 第5圖為覆蓋著半導體晶圓的電極形成表面的光敏電 阻的姓刻狀態的平面圖; 第6圖為被切割成小方塊之前,用來形成較多數目的 半導體元件的半導體晶圓的圖式; 第7 A圖為使外部連接端子與根據本發明之半導體元 件的互接圖案連結的-部份的放大剖面圖,第则為^外 部連接端子與習知技術的半導體元件的互接㈣連結的一 部份的放大剖面圖; 第8A圖為使外部連接端子與根據本發明之另一半導 體元件的互接®案連結的-部份的放大剖㈣,第8b圖為 使外部連接端子與習知技術的另_半導體元件的互接圖案 連結的一部份的放大剖面圖; 第9A至9C圖為用來解釋將一銅線或金線連結到本發 明之導電層的圖式; 第10A圖為根據本發明安裝於一板上的半導體元件的 圖式,而第10B圖為安裝於一板上的習知技術的半導體元 544742 A7 —_____________ 五、發明説明(7 ) 件的圖式; 第11A圖為安裝於一板上之根據本發明之另一半導體 元件的圖式,而第11B圖為安裝於一板上之習知技術之另 一半導體元件的圖式; 第12A至121圖為解釋習知技術之半導體元件的製造 方法的圖式; 第13A至131圖為解釋習知技術之半導體元件的另一 製造方法的圖式; 第14圖為第12 A至121圖所示之習知技術的半導體元 件的製造方法的流程圖;及 第15圖為13A至131圖所示之習知技術的半導體元件 的製造方法的流程圖。 較佳實施例之說.明 本發明之較佳實施例將同時參考附圖於下面詳細說 明。 第1A至II圖為用來解釋根據本發明之第一實施例的 半導體元件的製造方法的圖式。 如第1A圖所示,半導體晶圓1〇中形成有電極12的表面 被覆蓋有純化膜Η,而留下電極12暴露出。在此實施例的 半導體元件的製造方法中,導電層16被形成於半導體晶圓 10的電極形成表面上(第1BSI)。在本實施例中,藉喷鍍形 成鉻層,然後藉喷鍍形成銅層,以得到導電層16。鈍化膜 14表面可形成有.聚醯亞胺’或其他絕緣層(未顯示)作為保 護膜,於是導電層16形成。 本紙張尺度適用中國國家標準(OJS) A4規格(210X297公楚) 10
訂· 广請先閲讀背而之法意事項存填寫本買) 544742 A7 五、發明説明(8 ) 接著,光敏電阻18被塗覆於半導體晶圓10的全部電極 形成表面,以便以光敏電阻18覆蓋導電層16表面(第… 圖)光敏電阻為了做圖案而被曝光和顯影,以便如第1 d 圖所示,造成只有用來形成互接圖案的部份暴露出,用以 在導電層16的表面重新佈線。 第5圖為半導體晶圓的一晶片區段在光敏電阻1 8被暴 光和顯影的狀態下的一平面圖。參考數字18代表覆蓋住半 導體晶圓ίο的電極形成表面的光敏電阻,16a代表根據互接 圖案的配置導電層16中被暴露的部份,16b代表形成在互接 圖案的端部的形成墊的部份,16c代表連接於電極12的互接 圖案的基部端的部份。 本實施例的半導體元件的製造方法之特徵在於如第 1E圖所示,在使光敏電㈣做圖案之後,藉由將銅線接合 到形成墊的部份l6b的方法,而形成外部連接端子別。在導 線接曰時,銅線尖端被融化成球狀,球狀部份與形成墊的 部份接合,然後,導線被上拉並切掉,因而形成外部連接 端子50,、而突出部5〇a由從球狀部份往上突出的導線形成。 以此方式’外部連接端子5〇形成於所有形成於電極形成表 面的形成墊的部份16b。 在此方法中,因為外部連接端子5〇由導線接合而形 成’所以此工作是極度有效率的。而且,外部連接端子50 y利用傳統的接合工具形成。而且,因為銅線尖端定形為 f狀’⑽導電層16接合,然後在上拉時被切斷以形成外 ' # 子5G ’所W不需要習知技術中使導線f成L形的 本紙張尺度適财關緖準
•訂— (請先閲讀背面之注意事項再填寫本頁) .41^, 五、發明説明(9 ) 刼作,外部連接端子5〇的尺寸和形狀被容易地保持一致, 且此工作可被有效率地進行。 接著,導電層16的暴露表面以銅電鍍,以形成第❶圖 所示的互接圖案52。此時,如圖所示,外部連接端子㈣ 表面亦被覆蓋有銅鑛層。接著,外部連接端子的表面和互 接圖案52的表面被電鍍,以防止安裝時焊料的擴散。在本 實施例中,他們被連續地以鎳、鈀和金電鍍。 接著,如第1G圖示,光敏電阻18(第117圖)從半導體晶 圓10的電極形成表面移走,然後導電層16的暴露部份被飯 刻掉(第1H圖)。厚度為(^至丨微米數量級的導電層16,被 形成為遠薄於形成互接圖案52的銅鍍層,該銅鍍層的厚度 為5至20微米數量級,所以導電層16可被輕易地移走,且用 來移走導電層16的餘刻實際上不會對互接圖案52有影響。 導電層16的暴露部份可被移走,而不會被電阻覆蓋互接圖 案52。因此,鈍化膜14被暴露出,而且互接圖案”變得獨 立。 接著,半導體晶圓丨〇的電極形成表面被樹脂密封,以 便用树月曰28饮封互接圖案52和鈍化膜14。在樹脂密封步驟 中,使用利用密封模或封裝灌注(p〇tting)方法的傳遞模塑 (transfer mold)方法。由於此樹脂密封步驟因而得到外部連 接端子50從樹脂密封表面突出的半導體晶圓ι〇。第6圖顯示 出如此得到的半導體晶圓10,藉由切割此晶圓成為小方 塊’得到單獨的半導體元件54。 第2A至2H圖為用來解釋根據本發明之第二實施例的 544742 A7 ——----- B7 —_ 五、發明説明(1〇 ) 半導體元件的製造方法的圖式。此實施例的製造方法基本 上相同於上述實施例的製造方法,但在此實施例中,在形 成互接圖案俾在半導體晶圓的電極形成表面上重新佈線之 後’電極形成表面被保留在啊篆的狀態,在最終成 品中以樹脂密封。 如第2A圖所示,形成有電極12的半導體晶圓1〇的表面 被鈍化膜丨4所覆蓋,留下電極12暴露出,然後,如第⑼圖 所不,導電層16被形成。在本實施例中,鉻、鈦_鎢合金, 以及金藉喷鍍方法以該順序被沈積於電極形成表面上,以 便形成導電層16。 接著,光敏電阻18被塗覆於導電層16的表面上(第2c
圖),然後,光敏電阻18被曝光和顯影,以便做圖案(第2D 圖),以便暴露出之後形成互接圖案的部份16a、形成墊的 邛伤16b(第5圖)、以及在導電層16的表面連接於電極Η的 部份16c(第5圖)。 接著,如第2E圖所示,金線被連結到形成墊的部份 16b ’以形成外部連接端子6〇。而且當使用金線形成外部連 接端子60時,在端部有突出部6〇a的外部連接端子⑹被形 成以相同於上述貫施例的方式,藉由融化金線尖端成為 球狀,將球狀部份連結到形成墊的部份16b,然後上拉和切 斷金線。 利用導電層16作為電鍍能力進送層(plating power feed layer),導電層16的暴露表面被金電鍍,以形成第 囷所示的互接圖案62。在本實施例中,因為互接圖案a維 本紙張尺度適财b时標"7^7^ (21GX297公釐) —13 _—-—
------------- (請先閲讀背面之注意事項再填寫本頁) 、? 544742 A7 發明説明(11 持在最終成品中暴露於半導體元件的外表面,所以互接圖 案62藉金鍍層而形成。如圖所示,藉金鍍層,外部連接端 子60的表面亦被金鍍層覆蓋。 接著,如第2G圖所示,光敏電阻18(第217圖)從半導體 晶圓ίο的電極形成表面移除,然後導電層16的暴露表面被 蝕刻掉(第2H圖)。因此,鈍化膜14被暴露出,互接圖案變 得獨立。 將半導體晶圓切割成單獨的晶片而得到半導體元 件。在本貫施例的情況下,在使互接圖案62變得獨立之後 (在第2H圖所解釋的步驟之後),可能將半導體晶圓1〇的電 極形成表面用樹脂(未顯示)覆蓋住,以便留下外部連電極 的頂端暴露出。 第3圖為根據本發明第一實施例的半導體元件的製造 方法的流程圖,第4圖為根據第二實施例的製造方法的流程 圖。 比較第3和4圖所示之本發明方法以及第14和丨5圖所 示的相關技術的半導體元件的製造方法,在形成銅柱作為 外部連接端子之用來製造半導體元件的習知技術的方法中 (第14圖),層疊一乾燥膜以形成銅柱24,或是用銅鍍層堆 積成銅柱24的操作是必須的。相對於此,根據本發明方法, 因為外部電極係利用銅線或金線以導線接合方式形成,所 以可簡化製造程序,且可容易形成外部連接電極。 在藉-曲導線成L形而形成外部連接端子之用來製造 半導體元件的習.知技術的方法中(第15圖),將導線彎成l 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公楚) 14 (請先閲讀背面之注意事項再填寫本頁) 訂— 544742 A7 --·~__ B7 _ 五、發明說明(12 ) 〜 --- 形的步驟是需要的。而且塗覆一電阻層來給予外部連接端 子一強化鍍層的操作,以及曝光和顯影該電阻層是需要 =。相對於此,根據本發明方法,有可能以簡單的導線接 、口步驟形成外部.連接端子。而且,外部連接端子因銅錢而 破給予強化鍍層,俾形成互接圖案,而不需要塗覆、曝光 及顯影該電阻層。 以本發明方法製造出的半導體元件,具有不同於習知 技術的帛導體疋件的結才鼻,其不同在於外部連接端子和互 接圖案之間的接合部份,所以呈現出不同於習知技術的半 導體元件的動作和效果。第7八和73圖和第8八和犯圖為根 據本發明半導體元件的製造方法及習知技術的半導體元件 的製造方法所得到的半導體元件的外部連接端子的接合部 份和互接圖案的放大剖面圖。 第7A和7B圖顯示在互接圖案形成之後,以樹脂密封電 極形成表面的半導體元件的例子,而第8八和犯圖顯示互接 圖案暴露出的半導體元件的例子。 如第7A和8A圖所示,在根據本發明之半導體元件製 造方法中,在形成導電層16之後,銅線或金線被直接連結 到導電層16,以形成外部連接端子5〇和6〇,然後互接圖案 52和62藉銅鍍層或金鍍層而形成。相對於此,在相關的技 術的方法中,如第7B和8B圖中所示,在互接圖案2〇形成之 後,銅柱24或由金線形成的外部連接端子32,形成為在互 接圖案20的表面上的外部連接端子。 以此方式,.在本發明中,外部連接端子5〇和6〇被連結 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公复)
.............警…- (請先閲讀背面之注意事項再填寫本頁) 訂| 544742 A7 ^^ ----- -B7 五、發明説明---- 到‘電層16,且外部連接端子50和60的基部側(連結部)被 〆成互接圖案52和62的銅鍵層或金艘層中。所以,在 根據本發明的半導體元件中,相較於習知技術,外部連接 端子的高度減少至少互接圖案52和62的厚度量。因此,根 康本t月的半導體元件製造方法在形成薄和緊密的半導體 凡件上是有效的。而且,由第8A和8B圖的比較中很清楚看 在本务明中,外部連接端子6〇的高度變低。亦因為這 個原口,根據本發明,半導體元件整體可被緊密地製造。 、而且,當利用根據本發明的半導體元件製造方法時, Τ為鋼線或金線被直接連結到導電層16,以形成外部連接 *子50和60 ’所以優點在於外部連接端子可在被穩定支樓 下形成。 第9 Α至9 C圖顯示出外部連接端子,其係藉由將金線連 結到導電層16中的形成塾而形成,且其在圖案化電阻18的 处^路出第9 A圖顯示界定出形成墊的部份16b的電 的開口 ’》皮形成為較大於金線的連結部Y分。在此情況 下金線僅僅在其底部被連結到部份脱。第9B圖顯示開 a、7成為稍小於第9 A圖的情況。金線在其底部被連結到 口 IMW 6b。金線的連結部份的側邊的部份,與光敏電阻u 的側邊相接觸。第9C圖顯示出開口尺寸約相同於金線的連 結部份的情況。金線的底部被連結到形成墊的部份⑽。金 線的連結部份的側邊整個接觸於光敏電阻18的側邊。 、)此方式’根據藉由將金線或銅線直接連結到導電層 丨成外錢接端子的方法,因為金線或銅線被連結到 本紙張尺度適用中國國家標準(⑽
------------- (請先閲讀背面之注意事項再填寫本頁} 訂丨 544742 A7 -------— B7____ 五、發明説明(14 ) V電層16,且金線或銅線的連結部份被光敏電阻丨8所支 撐,所以可防止外部連接端子5〇和6〇的傾斜,且金線或銅 線可被可罪地連結到導電層1 6。而且,藉由將外部連接端 子50和60連結到.導電層16,然後以銅鍍層或金鍍層覆蓋導 電層16並且同日守藉由以銅鍍層或金艘層將外部連接端子 50和60的基部埋在互接圖案52和62中而支撐外部連接端子 50和60的基部(被連結的部份),外部連接端子咒和⑼被更 可靠地支撐。 第10A和10B圖以及第ι1Α和11B圖顯示安裝於板上的 本發明半導體元件相對於安裝於板上的習知技術半導體元 件的比較。第1 〇 A和10B圖顯示出根據本發明的半導體元件 (第10A圖)以及使用銅柱作為外部連接端子的習知半導體 元件(第10B圖)的比較。如第10B圖所示,當將形成有銅柱 24的半導體元件以焊料42安裝於板4〇上時,只有形成於銅 柱24的端表面的障礙層26從樹脂28的表面暴露出,而有不 良的焊接可沾性(solder wettability)。所以,焊料42有時不 會形成適合與銅柱連結的新月形。相對於此,當如第i〇a 圖所示安裝根據本發明的半導體元件時,由於突出部5〇a 從外部連接端子50突出,所以焊料42形成一合適的新月 形’所以半導體元件被可靠地安裝到板上。 第11A和11B圖顯示出互接圖案暴露出的本發明之半 導體元件(第ΠΑ圖)以及習知技術的半導體元件(第nB圖) 的比較。如第11B圖所示,當將習知技術的半導體元件(被 提供有藉由彎曲金線成為L形而得到外部連接端子32)安裝 本紙張尺度適用中國國家標準() A4規格(21〇><297公釐) '"一-— -
——… (請先閱讀背面之注意事項再填寫本頁) 、言 544742 A7 ~*-----— B7__ 五、發明說明(15 ) ~" 於板4〇上時,外部連接端子32的尖端抵接於板40,以便連 結,所以半導體元件和板4〇互相隔開。相對於此,當將根 據本發明的半導體元件安裝於板4()上時,如第Μ圖所 不,知料42在外部連接端子6〇的突出部咖被沈積成新月 形,所以半導體元件和板40被可靠地連結,而且,半導體 元件和板40之間的距離可縮短。 以此方式,根據本發明的半導體元件可以可靠地安裝 於板上,以便確保高可靠度,諸如與板的良好電性連接。 根據本發明之半導體元件和其製造方法,如上面的說 明,可能藉由連結導線而容易地形成外部連接端子,因而 容易地簡化製造半導體元件的步驟。而且,根據本發明, 可能改良半導體元件的生產效率,並降低半導體元件的製 造成本。本發明使得外部連接端子能夠以高密度被配置, 且能夠處理較多數目的銷。而且,可能提供相當可靠的半 導體元件,其中外部連接端子被可靠地連結於板上。 儘管本發明已關於為舉例目的所選定的特定實施例 來說明,應該清楚的是很多改良可被熟於此技者做出,而 不會背離本發明的基本原則和範圍。 本揭露内容係關於2001年5月25日所申請之日本專利 申請案第號所包含之標的内容,其揭露内容整 個被明確地合併於此作為參考。 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) -18
— (請先閲讀背面之注意事項再填寫本頁) 、trl 544742 A7 B7 五、發明説明(16 ) 10.. .半導體晶圓 14.. .鈍化膜 16a...部份 18.. .光敏電阻 22.. .乾燥膜 26.. .障礙層 30…電阻 32.. .外部連接端子 42…焊料 50a...突出部 60.. .外部連接端子 62…互接圖案 元件標號對照表 12…電極 16.. .導電層 16b...部份 20…互接圖案 24···銅柱 2 8…樹脂 30a."開口 4 0…才反 50.. .外部連接端子 52…互接圖案 60a...突出部 (請先閲讀背面之注意事項再填寫本頁) 19 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐)
Claims (1)
- 申明專利範園 1 · 一種半導體元件,包含·· 形成於一半導體基體的半導體組件; 外部連接端+,其等將言亥等組件連接到一外部電 路,及 互接圖案’將該等半導體組件的電極連接到該等 外部連接端子, /、中"亥等外部連接端子係由含有導電材料的導 線所形成,而且 ^忒等導線之連結於該等互接圖案的部份,被埋在 形成該等互接圖案的該金屬層中。 2.如申請專利範圍第丨項之半導體元件,其中形成該等 妾囷案的4金屬層被銅錢層和金錢層其中一戶 形成。 3·如申請專利範圍第旧之半導體元件,其中該等導線 由金線或銅線中選出。 4·如申請專利範圍第1項之半導體元件,其中該金屬声 和該等導線的材料相同。 曰 5·如申請專利範圍第㈣之半導體元件,其中該金屬層 和該等導線的材料為金。 日 6·如申請專利範圍第;!項之半導體元件,其中該金屬層 和5玄專導線的材料為銅。 7.如申請專利範圍第㈣之半導體元件,纟中該等外部 連接端子被形成該等互接圖案的該金屬層的材料所 544742 申請專利範圍 覆蓋。 如申明專利範圍第1項之半導體元件,其中該半導體 元件中形成該等互接圖案的表面被密#,以便留下 该等外部連接端子暴露出。 9·如申請專利範圍第3項之半導體元件,其中該半導體 =件中形成該等互接圖案的表面被密圭t,以便留下 該等外部連接端子暴露出。 10·一種半導體元件製造方法,該半導體元件被提供有 形成於-半導體基體的半導體組件,將該等組件連 妾】外°卩電路的外部連接端子,及將該等半導體 組件的電極連接到該等外部連接端子的互接圖案, 該方法包含的步驟為·· 在該半導體基體中形成該等電極的整個表面上 形成一導電層, 在4導電層的該表面上形成一電阻圖案,留下該 導電層的某些部份暴露出,該等部份為該等外料 接端子將被連接到墊的部份以及欲形成 案的部份, 」字含有導電材料的導線,在欲形成墊的部份連結 到°亥‘電層,以便形成外部連接端子, 在該導電層的該等暴露部份形成一金屬層, 移除該電阻,及 移除因移除該電阻而暴露出的該導電層,以便形 成該等互接圖案。 u’如申請專利範圍第10項之半導體元件製造方法,其 中該等互接圖案被銅鑛層和錢層之其中一者所形 成。 12·如申請專利範圍第10項之半導體元件製造方法,其 中金線或銅線被用來作為該等導線。 13·如广請專利範圍第10項之半導體元件製造方法,其 中該相同材料被用於該金屬層和該等導線。 14·如申請專利範圍第10項之半導體元件製造方法,其 中金被用來作為該金屬層和該等導線的材料。、 15·如申請專利,範圍第10項之半導體元件製造方法,其 中銅被用來作為該金屬層和該等導線的材料。 16·如申請專利範圍第10項之半導體元件製造方法,其 :當在該導電層的該暴露部份形成該金屬層時,該 等外部連接端被子被該金屬層的該材料所覆蓋。 17.如申請專利範圍第H)項之半導體元件製造方:,其 中在形成該等互接㈣之後,該半導體元件中形成 該等互接圖_表面被密封,以便留下該等外部連 接端子暴露出。 18.如申請專利範圍第12項之半導體元件製造方法,其 中在形成該等互接圖案之後,該半導體元件中形成 該等互接圖案的表面被密封,以便留下該等外部連 接端子暴露出。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001157451A JP2002353371A (ja) | 2001-05-25 | 2001-05-25 | 半導体装置及びその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW544742B true TW544742B (en) | 2003-08-01 |
Family
ID=19001308
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW091110671A TW544742B (en) | 2001-05-25 | 2002-05-21 | Semiconductor device and method of production of same |
Country Status (5)
Country | Link |
---|---|
US (1) | US6646357B2 (zh) |
EP (1) | EP1261029A3 (zh) |
JP (1) | JP2002353371A (zh) |
KR (1) | KR20020090301A (zh) |
TW (1) | TW544742B (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7271497B2 (en) * | 2003-03-10 | 2007-09-18 | Fairchild Semiconductor Corporation | Dual metal stud bumping for flip chip applications |
JP4863746B2 (ja) * | 2006-03-27 | 2012-01-25 | 富士通株式会社 | 半導体装置およびその製造方法 |
DE102007046556A1 (de) | 2007-09-28 | 2009-04-02 | Infineon Technologies Austria Ag | Halbleiterbauelement mit Kupfermetallisierungen |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5476211A (en) | 1993-11-16 | 1995-12-19 | Form Factor, Inc. | Method of manufacturing electrical contacts, using a sacrificial member |
US5650667A (en) * | 1995-10-30 | 1997-07-22 | National Semiconductor Corporation | Process of forming conductive bumps on the electrodes of semiconductor chips using lapping and the bumps thereby created |
AU8280398A (en) | 1997-06-30 | 1999-01-19 | Formfactor, Inc. | Sockets for semiconductor devices with spring contact elements |
JP2000200804A (ja) * | 1998-10-30 | 2000-07-18 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP3524441B2 (ja) * | 1999-08-10 | 2004-05-10 | 新光電気工業株式会社 | 配線形成方法 |
-
2001
- 2001-05-25 JP JP2001157451A patent/JP2002353371A/ja active Pending
-
2002
- 2002-05-20 KR KR1020020027903A patent/KR20020090301A/ko not_active Application Discontinuation
- 2002-05-20 EP EP02253531A patent/EP1261029A3/en not_active Withdrawn
- 2002-05-20 US US10/151,607 patent/US6646357B2/en not_active Expired - Lifetime
- 2002-05-21 TW TW091110671A patent/TW544742B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US6646357B2 (en) | 2003-11-11 |
KR20020090301A (ko) | 2002-12-02 |
US20020175426A1 (en) | 2002-11-28 |
JP2002353371A (ja) | 2002-12-06 |
EP1261029A2 (en) | 2002-11-27 |
EP1261029A3 (en) | 2004-06-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2809115B2 (ja) | 半導体装置とその製造方法 | |
US8105856B2 (en) | Method of manufacturing semiconductor device with wiring on side surface thereof | |
TWI331797B (en) | Surface structure of a packaging substrate and a fabricating method thereof | |
US6921980B2 (en) | Integrated semiconductor circuit including electronic component connected between different component connection portions | |
TWI248140B (en) | Semiconductor device containing stacked semiconductor chips and manufacturing method thereof | |
TW398063B (en) | Lead frame and its manufacturing method thereof | |
US9443827B2 (en) | Semiconductor device sealed in a resin section and method for manufacturing the same | |
TWI313492B (en) | Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices | |
TWI251314B (en) | Manufacturing method of semiconductor device, semiconductor device, circuit substrate and electronic equipment | |
TWI261328B (en) | Circuit device | |
US7651886B2 (en) | Semiconductor device and manufacturing process thereof | |
JP7179526B2 (ja) | 半導体装置および半導体装置の製造方法 | |
TW201631701A (zh) | 以聚合物部件爲主的互連體 | |
WO2010029668A1 (ja) | 集積回路装置 | |
TW200816414A (en) | Semiconductor device and manufacturing method thereof | |
US20100078813A1 (en) | Semiconductor module and method for manufacturing the semiconductor module | |
TW200810639A (en) | Conductive connection structure formed on the surface of circuit board and manufacturing method thereof | |
TW201227898A (en) | Package substrate and fabrication method thereof | |
US20040124516A1 (en) | Circuit device, circuit module, and method for manufacturing circuit device | |
EP1478021A1 (en) | Semiconductor device and manufacturing method thereof | |
JP2017228585A (ja) | 配線基板およびその製造方法、ならびに半導体装置の製造方法 | |
TW544742B (en) | Semiconductor device and method of production of same | |
TW423122B (en) | Process for manufacturing semiconductor device | |
TW200539408A (en) | Method of manufacturing circuit device | |
TW200930173A (en) | Package substrate having embedded semiconductor element and fabrication method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MM4A | Annulment or lapse of patent due to non-payment of fees |