542961 A7542961 A7
發明說明（ 經濟部智慧財產局員工消費合作社印制衣 【技術領域】 本發明係關於一種容錯系統，特別是指一種多匯流排 共享記憶體容錯系統。 【先前技術】 5 整個系統的容錯設計排除傳統的主從板設計。傳統的 選擇邏輯都是在主控板與備用板上各有一條控制線，以決 定主控板動作或是備用板動作。 夕匯机排共旱記憶體容錯系統的硬體架構與傳統的容 錯系統之硬體架構的最大差異在於主控板當機後，備用板 10繼續運作可到達的程度。最早的容錯系統只是單純的具體[Explanation] [Technical Field] The present invention relates to a fault-tolerant system, in particular to a multi-bus shared memory fault-tolerant system. [Prior Art] 5 Fault-tolerant design of the entire system Traditional master-slave board design. The traditional selection logic is to have a control line on the main control board and the standby board to determine the action of the main control board or the standby board. The biggest difference between the hardware architecture and the traditional fault-tolerant system is the extent to which the standby board 10 can continue to operate after the main control board is down. The earliest fault-tolerant systems were simply specific
Hot Swapping的功能，即當主控板當機時，經由故障燈 的顯不或警鈴的叫聲通知控制中心，再由控制中心人員在 不斷電的情況下，將備用板插上取代主控板，此時系統雖 能繼績運作但備用板上的系統資料卻是空白的，因此系統 15跟重新開機疋沒什麼兩樣。而後來的容錯系統雖然已經把 主控板與備用板同時運作考慮進去，並且在主控板當機 日寸，備用板亦能及時接手運作，而且系統資料也沒有流 失。但是當系統内其他卡板發生問題並發送訊號給主控 板，同時要求主控板給予回應時，主控板不幸的也發生問 2〇題並切換到備用板接手，這時候第二代的容錯系統將無法 解決，發生問題的卡板將-直等待回應的訊號而無法正常 的工作。 由此可見，上述習用物品仍有諸多缺失，實非一良善 之設計者，而亟待加以改良。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公 β 裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 542961 A7 ------- PA890393.TWP - 4/17 五、發明說明（>) 本案發明人鏗於上述習用系統所衍生的各項缺點，乃 亟心加以改良創新，並經多年苦心孤諸潛心研究後，終於 -裝--- (請先閱讀背面之注意事寫本頁) 成功研發完成本件多匯流排共享記憶體容錯系統。 【發明目的】 5 纟發明多匯流排共享記憶體容錯系統之主要目的，係 在於使得系統的心臟部分得到多重的保護，不管在任何時 刻、任何匕意外的情況下當機，依然能夠把系統當時的資 料狀心等系統資汛同時被主控（Active)板及備用 (Standby)板所擁有而不會流失，並在任何—塊卡板出現 10問題的同時啟動另外一塊卡板接手，讓CPU能夠保持原有 狀態繼續正常動作。 【技術内容】 -線· 可達成上述發明目的之多匯流排共享記憶體容錯系 統，包括有：CES、MUX、STM、CPU四種卡板，CPU卡板 15 上的 RTDB(Reai Time Data Back叩）及他卜 經濟部智慧財產局員工消費合作社印制衣 / ocess co_unicati〇n)等多匯流排共享記憶體容錯 系統之设計，使得系統的心臟部分得到多重的保護，不管 t任何時刻、任何意外的情況下當機，依然能夠把系統當 寸的資料狀恶等系統資訊同時被主控（Ac t i ve)板及備 20用（Standby)板所擁有而不會流失，並在任何一塊卡板出 現問題的同時啟動另外_塊卡板接手，讓cpu能夠保持原 有狀態繼續正常動作。 【圖式簡單說明】 明蒼閱以下有關本發明一較佳實施例之詳細說明及其 -4- 冢紙張尺ϋ用fii家標準--- 542961 A7 B7 PA890393.TWP - 5/17 五、發明説明 經濟部中央標準局員工消費合作社印製 附圖，將可進一步瞭解本發明之技術内容及其目的功效； 有關該實施例之附圖為： 圖一為本發明多匯流排共享記憶體容錯系統之系統架 構圖； 5 圖二為本發明多匯流排共享記憶體容錯系統之CES卡 板方塊圖； 圖三為本發明多匯流排共享記憶體容錯系統之MUX卡 板方塊圖； 圖四為圖三MUX卡板之系統交換架構圖； 10 圖五為本發明多匯流排共享記憶體容錯系統之STM卡 板方塊圖； 圖六為本發明多匯流排共享記憶體容錯系統之CPU卡 板方塊圖； 圖七為本發明多匯流排共享記憶體容錯系統之CPU共 15 享記憶體容錯系統方塊圖； 圖八為本發明多匯流排共享記憶體容錯系統之I PC通 道之整體概略圖； 圖九為本發明多匯流排共早記憶體容錯糸統之容錯糸 統架構圖； 20 圖十為本發明多匯流排共享記憶體容錯系統之ACL選 擇邏輯狀態圖。 【較佳實施例】 本發明分成三部份。 (一）系統簡介。 (請先閱讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 542961 PA890393.TWP - 6/17 五、發明說明（(^ ) 本發明之多匯流排共享記憶體容錯系統架構如圖一所 不’主要包含CES卡板、MUX卡板、STM卡板、CPU卡板等 四種卡板，以下就四種卡板作一介紹： ※CES卡板：其方塊圖如圖二所示，CES卡板是將十 5六路的T1/E1線之信號轉換成為一 ATM AALUATM Adaptation Layer 1)之信號，然後將此信號送往MUX 卡板。 CES卡板分為四大部分： 第一部份為CPU與動態存取記憶體及唯讀記憶體。此 10部份在開機時即將預設值填入其它的三部分之元件内，使 其可正常工作並可透過Dual Port RAM與CPU卡板來溝 通。 第二部份為LIU部份，負責將16路的T1/El線的類比 信號中的CLOCK與DATA解出，並轉換成數位信號。 15 第三部份為Framer部份，負責將LIU部份的T1/E1的 數位信號，加以處理並取出訊框信號，以達成同步。 第四部份為AAL部份，負責將Framer部份的T1/E1數 位信號，經過運算轉換成ATM UTOPIA(Universal Test and Operation PHY Interface for ATM:通用性測 20試及實體操作介面）Level 1信號，並將此信號送往MUX 卡板成為1路的UTOPIA Level 2的信號。由於CES卡板上 共可將1 6路的T1/E1的信號轉變成為一路的UTOPIA Level 1的信號，故最多可收容384/512路電話線。CES 卡板亦具有Dual Port RAM的晶片可負責與CPU卡板來溝 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項寫本頁) I!裝 -丨線· 經濟部智慧財產局員工消費合作社印製 542961 A7 PA890393.TWP - 7/17 五、發明說明（γ) 通’由此以告知CPU卡板是否CES卡板尚在正常的運作 中’若有問題產生則可由燈號或CPU板得知。 (請先閱讀背面之注意事項再填寫本頁) MUX卡板：其方塊圖如圖三所示。mux卡板是將十六 路CES卡板所產生之低速信號集合成為一路高速之信號， 5然後將此信號送往STM卡板。 ※从以卡板分為三大部分： 第一部份為CPU與動態存取記憶體及唯讀記憶體，此 部份在開機時即將預設值填入某部分之元件内之記憶空間 使其可正常工作及透過Dual p〇rt 1?龍與(^11卡板來溝 10 通。 第一部份為ATM UTOPIA Level 1信號轉變成 UTOPIA Level 2信號的轉換晶片及由VHDL (Very high speed integrated circuit Hardware Description language)所寫成的 FPGA(Field 15 Programmable Gate Array) ’ 此部分為 MUX卡板之主 體，一個 ATM UTOPIA Level 1信號轉變成 utopia 經濟部智慧財產局員工消費合作社印製The function of Hot Swapping, that is, when the main control board is down, the control center is notified by the display of a fault light or the call of an alarm bell, and then the control center staff plugs in the replacement board to replace the main Control board, although the system can continue to operate at this time, the system data on the standby board is blank, so the system 15 is no different from restarting. In the later fault-tolerant system, although the main control board and the standby board have been considered to operate at the same time, and when the main control board is down, the standby board can take over the operation in time, and the system data is not lost. However, when problems occurred with other card boards in the system and sent signals to the main control board, and at the same time requested a response from the main control board, the main control board unfortunately also encountered a problem 20 and switched to the standby board to take over. The fault-tolerant system will not be able to solve the problem, and the card board will wait for the response signal and cannot work normally. It can be seen that there are still many shortcomings in the above-mentioned conventional articles. They are not a good designer and need to be improved. This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 male β pack -------- order --------- (Please read the precautions on the back before filling this page) 542961 A7 ------- PA890393.TWP-4/17 V. Description of the invention (>) The inventor of this case, eager to improve and innovate due to the shortcomings derived from the above-mentioned conventional system, has been eager to improve and innovate, and after many years of hard work After meticulous research, I finally-installed --- (Please read the note on the back to write this page) Successfully developed this multi-bus shared memory fault tolerance system. [Objective of the Invention] 5 纟 Invented multi-bus shared memory The main purpose of the fault-tolerant system is to make the heart part of the system receive multiple protections. Regardless of the machine crashing at any time and in any accident, it can still control the system's data at the same time and other system resources such as flood control ( Active) and standby (Standby) boards will not be lost, and when any-10 card problems occur at the same time start another card board to take over, so that the CPU can maintain the original state to continue normal operations. [Technical content] -Line · Can achieve the above hair Many purposes of the bus shared memory fault-tolerance system, including: CES, MUX, STM, CPU four card boards, RTDB (Reai Time Data Back 叩) on CPU card board 15 and staff consumption of the Intellectual Property Bureau of the Ministry of Economic Affairs The design of multi-bus shared memory fault-tolerant system such as cooperative printing clothes / ocess co_unicati〇n), so that the heart of the system is protected multiple times, no matter what time, any unexpected situation, the system can still be able to put the system down When the system information such as data is evil, it is owned by the main control board and standby board at the same time without losing, and when any card board has a problem, it starts another _ card board Take over, so that the CPU can maintain its original state and continue normal operations. [Brief description of the drawings] Ming Cang read the following detailed description of a preferred embodiment of the present invention and its 4-1 standard for the use of mound paper ruler --- 542961 A7 B7 PA890393.TWP-5/17 V. Invention Explaining the printed drawings of the staff consumer cooperative of the Central Bureau of Standards of the Ministry of Economics will further understand the technical content of the present invention and its purpose and effectiveness. The drawings related to this embodiment are: Figure 1 is a multi-bus shared memory fault tolerance system of the present invention 5 is a block diagram of the CES card board of the multi-bus shared memory fault tolerance system of the present invention; FIG. 3 is a block diagram of the MUX card board of the multi-bus shared memory fault tolerance system of the present invention; Three MUX card board system exchange architecture diagram; Figure 5 is a block diagram of the STM card board of the multi-bus shared memory fault tolerance system of the present invention; Figure 6 is a block diagram of the CPU card board of the multi-bus shared memory fault tolerance system of the present invention ; Figure 7 is a block diagram of a total of 15 shared memory fault-tolerant systems for the CPU of the multi-bus shared memory fault-tolerant system of the present invention; Figure 8 is a block diagram of the I PC channel of the multi-bus shared memory fault-tolerant system of the present invention; Schematic view; FIG nine present multiple fault-tolerant bus system which is common early schematic diagram of the memory system which is fault-tolerant invention; FIG. 20 of the present invention ten bus shared ACL multiple fault-tolerant memory systems select logic state. [Preferred Embodiment] The present invention is divided into three parts. (1) System introduction. (Please read the precautions on the back before filling out this page) The size of the paper used for this edition is applicable to the Chinese National Standard (CNS) A4 (210X297 mm) 542961 PA890393.TWP-6/17 5. Description of the invention ((^) The multi-bus shared memory fault-tolerant system architecture is shown in Figure 1. It mainly includes CES card board, MUX card board, STM card board, CPU card board and other four card boards. The following introduces the four card boards: CES Card board: Its block diagram is shown in Figure 2. The CES card board converts the signals of the T1 / E1 lines of 15 channels to an ATM AALUATM Adaptation Layer 1) signal, and then sends this signal to the MUX card board. The CES card board is divided into four parts: The first part is the CPU, dynamic access memory and read-only memory. These 10 parts will be filled with the default values in the other three parts when they are turned on, so that they can work normally and can communicate with the CPU card board through Dual Port RAM. The second part is the LIU part, which is responsible for resolving the CLOCK and DATA in the analog signal of the 16-channel T1 / El line and converting it into a digital signal. 15 The third part is the Framer part, which is responsible for processing the digital signal of T1 / E1 in the LIU part and taking out the frame signal to achieve synchronization. The fourth part is the AAL part, which is responsible for converting the T1 / E1 digital signals of the Framer part into ATM UTOPIA (Universal Test and Operation PHY Interface for ATM: Level 1 signal) And send this signal to the MUX card to become a 1-way UTOPIA Level 2 signal. A total of 16 T1 / E1 signals can be converted into one UTOPIA Level 1 signal on the CES card board, so it can accommodate up to 384/512 telephone lines. The CES card board also has Dual Port RAM chip which can be used to communicate with the CPU card board. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back to write this page) I -Equipment-Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 542961 A7 PA890393.TWP-7/17 V. Description of the Invention (γ) This will tell the CPU card whether the CES card is still operating "If there is a problem, it can be known from the light or the CPU board. (Please read the precautions on the back before filling this page) MUX card board: its block diagram is shown in Figure 3. The mux card board is a set of low-speed signals generated by the sixteen CES card boards into one high-speed signal, and then sends this signal to the STM card board. ※ The card board is divided into three parts: The first part is the CPU, dynamic access memory and read-only memory. When this part is turned on, the default value will be filled into the memory space in the components of a certain part. It can work normally and pass 10 channels through Dual port 1 龙 dragon and ^ 11 card board. The first part is a conversion chip for ATM UTOPIA Level 1 signal to UTOPIA Level 2 signal and VHDL (Very high speed FPGA (Field 15 Programmable Gate Array) written by integrated circuit Hardware Description language 'This part is the main body of the MUX card board. An ATM UTOPIA Level 1 signal is transformed into utopia printed by the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
Level 2信號的轉換晶片負責將4路的CES卡板所送來的 ATM UTOPIA Level 1信號轉變成為丨路的UT〇piA Level 2的信號，由於共有四顆的轉換晶片，故可將丨6路 20的UTOPIA Level 1的信號轉變成為四路的UT〇piA Level 2的信號，然後經由VHDL寫成所可程式化FpGA將 四路的UTOPIA Level 2的信號再合成並轉變成為i路的 UTOPIA Level 1的高速信號，本晶片的設計重點在於多 路的UTOPIA Level 2的信號轉變成為UT〇pu ^…丨^ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --—-- 542961 A7 - —- ⑸ PA89Q393.TWP - 8/17 五、發明說明（&) 時中間要經由Polling(查詢）的程序去得到一個公正的信 號選取過程。 第三部分為Dual P〇rt RAM 與 Watch dog，DualThe Level 2 signal conversion chip is responsible for converting the ATM UTOPIA Level 1 signal sent by the four-channel CES card board into the UT0piA Level 2 signal. Since there are four conversion chips, it can convert 丨 6 channels The signal of 20 UTOPIA Level 1 is converted into four-channel UT〇piA Level 2 signals, and then VHDL is written into a programmable FpGA. The four-channel UTOPIA Level 2 signals are synthesized and converted into i-channel UTOPIA Level 1 signals. High-speed signals. The design of this chip focuses on the conversion of multiple UTOPIA Level 2 signals into UT〇pu ^ ... 丨 ^ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ----- 542961 A7-—- ⑸ PA89Q393.TWP-8/17 V. In the description of the invention (&), the process of polling must be used to obtain a fair signal selection process. The third part is Dual Porat RAM and Watch dog, Dual
Port RAM的晶片的部分負責與cpu卡板來溝通，由持續 5的由Watch dog所發出的信號保持與cpu卡板的互動以告 知CPU卡板是否MUX卡板尚在正常的運作中，在模組中若 有其中-片MUX卡板產生問題則由另一片卡板來取代。其 系統交換架構圖如圖四所示。 ※STM卡板：其方塊圖如圖五所示。STM卡板是把來 10自腳乂卡板的高速UTOPIA ievei丨的信號，經過Saturn User Network Interface(SUNI)晶片轉換成 ATM 的格 式再經由光電轉換模組（0/E、E/0 m〇du 1 e)轉換成光信 號’以0C-3的速率傳送到ATM網路。 》CPU卡板：其方塊圖如圖六所示。cpu卡板為整個 15系統的控制及管理中樞，提供的功能為「呼叫處理」 (Calling Processing) 、 「異常管理」（Fault Processing) > 「績效管理」（Performance Processing)、「容錯控制」（Dup丨ex contr〇1)和「診 斷」（Diagnostic & Audi ting)。開機時兩片CPU卡板 2〇經由一者溝通協調後其中之一取得主控（A c t i v e)權而另 一片則成為備用（Standby)。經由軟體的機制使二者的計 憶體儲存内容一致而使CPU卡板本身即有「容錯控制」 之機能’糸統中M U X卡板以及S T Μ卡板之「容錯控 制」管理則由主控之CPU卡板處理。CPU卡板本身可以 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Port RAM's chip part is responsible for communicating with the CPU card board. The signal sent by Watch dog for 5 keeps interacting with the CPU card board to inform the CPU card board whether the MUX card board is still in normal operation. If there is a problem with one of the MUX cards in the group, another card will replace it. Its system exchange architecture diagram is shown in Figure 4. ※ STM card board: Its block diagram is shown in Figure 5. The STM card is a high-speed UTOPIA ievei signal from a 10-pin card, which is converted into an ATM format by a Saturn User Network Interface (SUNI) chip, and then passed through a photoelectric conversion module (0 / E, E / 0 m. du 1 e) is converted into an optical signal and transmitted to the ATM network at a rate of 0C-3. 》 CPU card board: Its block diagram is shown in Figure 6. The cpu card is the control and management hub of the entire 15 system. The functions provided are "Calling Processing", "Fault Processing" > "Performance Processing", "Fault Tolerance Control" ( Dup 丨 ex contr〇1) and "Diagnostic" (Diagnostic & Audi ting). One of the two CPU card boards 20 communicated and coordinated with one another at the start-up time, and one of them obtained the master control (A c t i v e) right while the other one became a standby (standby). Through the software mechanism, the memory contents of the two memories are consistent, so that the CPU card itself has the function of "fault tolerance". In the system, the "fault tolerance control" management of the MUX card and the ST M card is managed by the main control. CPU card processing. The CPU card itself can be used. This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm).
(請先閱讀背面之注意事Z ri裝— Θ寫本頁) 經濟部智慧財產局員工消費合作社印製 542961 PA890393.TWP - 9/17 A7 B7 五、發明說明（q ) 透過LOCAL BUS與系統上其他的CES卡板、MUX卡板及 STM卡板充分溝通得以掌握系統的運作狀況並提供整個 系統的控制及管理。 (二）多匯流排共享記憶體容錯系統介紹。 5 在CPU的主控板及備用板卡板上，都有一顆cpu、一 顆SRAM及一顆Dual-Port RAM。SRAM用來作及時資料備 份（Real Time Data Backup : RTDB)之用，Dual-Port RAM用來與系統内其他卡板作内部處理溝通（inter — Process co_unicati〇n : IPC)之用，方塊圖如圖七所 10 示。 主控板上的CPU的匯流排並接於備用板上的RTDB，備 用板上的cpu的匯流排同時並接於主控板上的RTDB，如此 一來，主控板及備用板上的RTDB同時被主控板上的cpu所 複寫，其内容在任何時刻都是一樣，因此當主控板有狀況 15發生而備用板接手時，備用板上的RTDB可以保有原本主 ί工板的R T D B的系統資料，繼續正碟且資料不會流失的正 常運作。另一方面，主控板上的CPU的匯流排並接於備用 板上的I PC，備用板上的cpu的匯流排同時並接於主控板 上的IPC，正常情況下主控板使用主控板的IPC與系統其 2〇他卡板作内部處理溝通，備用板使用備用板的IPC與系統 其他卡板作内部處理溝通，但是當主控板上的是正常 的，而IPC卻是無法工作時，主控板的cpu將可利用備用 板上的IPC與系統其他卡板作内部處理溝通。同理，備用 板上的CPU也可透過主控板的IPC與系統其他卡板作内部 -9- 本紙張尺度ϋ用中國國家標準（CNS)A4規^：(21〇 x 297公）--------------一 • I r-----------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 542961 A7 ____ β7 PA890393.TWP - 10/17 經濟部智慧財產局員工消費合作社印製 發明說明（¾ ) 處理溝通，其整體概圖如圖八所示。 多匯流排共享記憶體容錯系統的硬體架構與傳統的容 錯糸統之硬體架構的最大差異在於主控板當機後，備用板 繼續運作可到達的程度。而參閱先前技術所說明的狀況， 5在本發明中之多匯流排共享記憶體容錯系統之備用板將會 利用多匯流排的架構透過另一個I p C的管道（如圖七及圖 八所示）得知有卡板正等待回應的訊號，因此送出回應的 訊號給卡板讓系統繼續正常的工作。 (二）A C L與糸統容錯系統介紹。 系統内CES、MUX、STM、CPU四種卡板都有主控板與 備用板的設計，其整體概圖如圖九所示。而其主控板或備 用板的選擇是由選取控制邏輯（Access C(DntrQl Logic : ACL)來決定，傳統的選擇邏輯都是在主控板與備 用板上各有一條控制線，以主控板=1及備用板钊，（或主 控板=0及備用板二1)來決定那塊是主控板及那塊是備用 板。這樣的選擇邏輯在下列情況發生時便會不知所措而產 生誤動作，如： 1 ·任何一條控制線斷線時。 2·因雜訊或干擾造成兩條控制線同時為〇或同時為工 3·兩條控制線短時間内變動不停。 因此本系統的主控板及備用板各有兩條控制線來表示 其狀態，如此一來，共有16種狀態可以決定是主控板或 是備用板動作，其選擇邏輯如圖十所示。 在每個狀態的四個位元中a、b兩位元代表主控板的 -10 本紙張尺度適用中國國家標準（CNS〉A4規格（210 X 297公爱） 五 10 15 20 請 先 閱 讀 背 面 之 注 意 事 項(Please read the note on the back Z ri install — Θ write this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperatives 542961 PA890393.TWP-9/17 A7 B7 V. Description of the invention (q) Via LOCAL BUS and the system The other CES card boards, MUX card boards and STM card boards fully communicated to grasp the operating status of the system and provide control and management of the entire system. (2) Introduction of multi-bus shared memory fault tolerance system. 5 There are one CPU, one SRAM, and one Dual-Port RAM on the main control board and the spare board of the CPU. SRAM is used for real-time data backup (Real Time Data Backup: RTDB), Dual-Port RAM is used for internal processing communication (inter — Process co_unicati〇n: IPC) with other cards in the system, the block diagram is as follows This is shown in Figure VII. The bus of the CPU on the main control board is connected to the RTDB on the standby board, and the bus of the CPU on the standby board is connected to the RTDB on the main board at the same time. In this way, the RTDB on the main board and the standby board At the same time, it is copied by the CPU on the main control board, and its content is the same at any time. Therefore, when the main control board has a condition 15 and the standby board takes over, the RTDB on the standby board can retain the original RTDB of the main board. System data, normal operation continues without data loss. On the other hand, the bus of the CPU on the main control board is connected to the I PC on the standby board. The bus of the CPU on the standby board is also connected to the IPC of the main control board. Under normal circumstances, the main control board uses the main board. The IPC of the control board communicates with the other boards of the system for internal processing. The standby board uses the IPC of the standby board to communicate with the other boards of the system for internal processing. However, when the main board is normal, IPC cannot. During work, the CPU of the main control board can use the IPC on the standby board to communicate with other card boards in the system for internal processing. In the same way, the CPU on the standby board can also use the IPC of the main control board and other card boards in the system for internal use. -9- This paper standard uses the Chinese National Standard (CNS) A4 regulation ^: (21〇x 297 公)- ------------ 一 • I r ----------- Install -------- Order --------- (Please read first Note on the back, please fill out this page again) Printed by the Intellectual Property Bureau's Consumer Consumption Cooperative of the Ministry of Economic Affairs 542961 A7 ____ β7 PA890393.TWP-10/17 Printed by the Intellectual Property Bureau's Employee Consumption Cooperative of the Ministry of Economic Affairs Printed Description of the Invention (¾) Handling communication, its whole The outline is shown in Figure 8. The biggest difference between the hardware architecture of the multi-bus shared-memory fault-tolerant system and the traditional fault-tolerant system's hardware architecture is the extent to which the standby board can continue to operate after the main control board goes down. And referring to the situation described in the prior art, 5 The spare board of the multi-bus shared memory fault tolerance system in the present invention will utilize the multi-bus architecture through another I p C channel (as shown in Figures 7 and 8). (Shown) I learned that there is a signal waiting for the card board to respond, so I sent a response signal to the card board to allow the system to continue to work normally. (2) Introduction of A C L and the unified fault tolerance system. In the system, the four card boards of CES, MUX, STM, and CPU have the design of the main control board and the spare board. The overall outline is shown in Figure 9. The selection of its main control board or standby board is determined by the selection of control logic (Access C (DntrQl Logic: ACL)). The traditional selection logic is to have a control line on the main control board and the standby board to control the main control board. Board = 1 and standby board (or main control board = 0 and standby board 2 1) to determine which is the main control board and which is the standby board. Such selection logic will be at a loss when the following situations occur Malfunctions occur, such as: 1 When any control line is disconnected. 2. The two control lines are at the same time 0 or at the same time due to noise or interference. 3. The two control lines are constantly changing for a short time. The system's main control board and standby board each have two control lines to indicate their status. In this way, a total of 16 states can be determined to be the main control board or the standby board. The selection logic is shown in Figure 10. Among the four bits of each state, a and b represent -10 of the main control board. This paper size is applicable to Chinese national standards (CNS> A4 specification (210 X 297 public love). 5 10 15 20 Please read the note on the back first. matter
寫 本 頁 訂 542961 PA890393.TWP - 11/17 A7 B7 a - 五、發明說明〆） 狀悲’ c、d兩位元代表備用板的狀態，以多數決及狀態 相似度兩種規則為判斷依據，可發現〇 1 〇 〇、1 〇 〇 〇、 1110、1101等狀態會明確地導向狀態11〇〇，即主控板動 作。同樣的1011、0111、000 1、0010等狀態會明確地導 5向狀態00U，即備用板動作。雖然狀態1111、1001若是 以多數決及狀態相似度兩種規則為判斷依據，無法明確地 導向1100或0011，卻可明確地導向1〇11，而1〇11則明確 地導向0011，即備用板動作。同理，狀態〇11〇、〇〇〇〇若 是以多數決及狀態相似度兩種規則為判斷依據，無法明確 10地導向1100或0011，卻可明確地導向〇〇1〇，而〇〇1〇則明 確地導向0011，即備用板動作。同理，狀態0101若是以 多數決及狀態相似度兩種規則為判斷依據，無法明確地導 向1100或0011，卻可明確地導向11〇1，而11〇1則明確地 導向1100，即主控板動作。同理，狀態1〇1〇若是以多數 15決及狀悲相似度兩種規則為判斷依據，無法明確地導向 1100或0011，卻可明確地導向1 000，而1〇〇〇則明確地導 向1100，即主控板動作。 .H【特點及功效】 本發明所提供之多匯流排共享記憶體容錯系統，與其 20他習用技術相互比較時，更具有下列之優點·· 1. 夕匯*排共享記憶體容錯系統的硬體架構與傳統 的容錯系統之硬體架構的最大差異在於主控板當機後，備 用板繼績運作可到達的程度。 2. 夕匯流排共享記憶體容錯系統之備用板將會利用 -11 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） L I I 1·1 I I I I I — — — — — — II « — — — — — — I— I 1 I I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 542961 A7 ____B7______ PA890393.TWP - 12/17 五、發明說明（0 多匯流排的架構透過另一個IPc的管道得知有卡板正等待 回應的訊號，因此送出回應的訊號給卡板讓系統繼續正常 的工作。 上列詳細說明係針對本發明之一可行實施例之具體說 5明，惟該實施例並非用以限制本發明之專利範圍，凡未脫 離本發明技藝精神所為之等效實施或變更，均應包含於本 案之專利範圍中。 綜上所述’本案不但在技術思想上確屬創新，並能增 進上述多項功效，應已充分符合新穎性及進步性之法定發 1〇明專利要件’爰依法提出申請，懇請貴局核准本件發明 專利申請案，以勵發明，至感德便。 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Write this page to order 542961 PA890393.TWP-11/17 A7 B7 a-V. Description of the invention 〆) State of sadness' c and d represent the status of the standby board, based on the majority rule and state similarity rules It can be found that the states of 001, 100, 1110, 1101, etc. will clearly lead to state 1100, that is, the main control board moves. The same states of 1011, 0111, 000 1, 0010 will clearly lead to the 5-way state 00U, that is, the standby board moves. Although states 1111 and 1001 cannot be explicitly guided to 1100 or 0011 based on the two rules of majority and state similarity, they can be explicitly directed to 1011, while 1011 is explicitly directed to 0011, that is, the spare board. action. In the same way, if the states 011 and 100,000 are based on the two rules of majority and state similarity, they cannot be explicitly guided to 1100 or 0011, but they can be explicitly guided to 〇〇〇〇, 〇〇1 〇 is clearly directed to 0011, that is, the action of the backup board. Similarly, if the status 0101 is based on the two rules of majority and status similarity, it cannot be explicitly directed to 1100 or 0011, but it can be explicitly directed to 010, and 1101 is explicitly directed to 1100, that is, the main control Board action. In the same way, if the state 10100 is based on the two rules of majority 15 and similarity, it cannot be explicitly directed to 1100 or 0011, but it can be explicitly directed to 1,000, and 1000 is explicitly directed. 1100, that is, the main control board moves. .H [Features and Effects] The multi-bus shared-memory fault-tolerant system provided by the present invention has the following advantages when compared with 20 other conventional technologies. 1. Xihui * Hard-memory shared-memory fault-tolerant system The biggest difference between the physical architecture and the hardware architecture of the traditional fault-tolerant system is the extent to which the standby board can continue to operate after the main control board goes down. 2. The spare board of the bus shared memory fault tolerance system will be used. -11-This paper size applies to China National Standard (CNS) A4 (210 X 297 public love) LII 1 · 1 IIIII — — — — — — II «— — — — — — I— I 1 II (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 542961 A7 ____B7______ PA890393.TWP-12/17 5. Description of the invention ( 0 The multi-bus architecture learns that the card board is waiting for a response signal through another IPc channel, so it sends the response signal to the card board to allow the system to continue to work normally. The above detailed description is for one of the feasible implementations of the present invention The specifics of the example are 5 clear, but this embodiment is not intended to limit the scope of the patent of the invention, and any equivalent implementation or change that does not depart from the technical spirit of the invention should be included in the scope of the patent in this case. 'This case is not only innovative in terms of technical ideas, but also enhances the above-mentioned multiple effects. It should have fully complied with novel and progressive statutory issuance of 10 patents.' To apply, please ask your office to approve this invention patent application, in order to encourage invention, to the best of your ability. (Please read the notes on the back before filling this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Consumption Cooperative 2 This paper is applicable to China National Standard (CNS) A4 specification (210 X 297 mm)