經濟部智慧財產局員工消費合作社印製 五、發明説明（/) 發明摘要說明： 本發明係有關一種具有可配置資料/位址通道架 構之資料處理系統，尤指一種利用非同步資料/位址 通道來取代傳統的同步數據匯流排，能根據實際的 資料流量需求，決定出所需要的通道數量，而增加 兩元件之間的傳輸頻寬之設計。 技術背景說明： 如第1圖所示，係為傳‘統電滕系統的基本架構 圖；一般電腦系統概括有：中央處理器10 (CPU)、 系統控制器20 (system controller)、記憶體30 (memory)、視訊次系統 40 (video subsystem)以 及 PCI 元件 50 (peripheral component interconnect device)。前述各元件的連結係利用多 條資料線的匯流排（bus)來進行資料的傳遞。系統控 制器20是作為中央處理器10及其他系統元件（如記 憶體30、視訊次系統40及PCI元件50)之間的橋 接界面，以一般電腦系統為例，即為系統晶片組 (chipsets)或是北橋晶片（north bridge)。在系統控 制器20與CPU 10之間的系統匯流排ll(system bus)中，包含複數條平行的資料線（Data I/O)以及 位址線（Address I/O)，以目前Pentium Π和 PowerPC為例，共有64條資料線以及32條位址線， -----^------1--------tr------^ I (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用令國國家標準（CNS ) A4規格（210X297^釐） 4 3 66 9 5 經濟部智慧財產局員工消費合作社印製 A7 B7_ 五、發明説明（> ) ~~" ^~ 用以平行接收/傳送資料和位址。另外系統控制器2〇 和記憶體30之間的記憶體匯流排3l(mem(^y bus)，則包括64條資料線以及數條位址線(根據不 同的記憶體類型而不同）。這些傳統匯流排的另__項 特徵是單一性，例如當記憶體30要傳送資料到視訊 次系統40時，則全部的資料1/0和位址ϊ/〇都會 被使用在此時的傳送狀態中，記憶體3〇不可能一邊 送資料給視訊次系統40而同時又送資料給cpu 10 ° : 簡單的說，上述匯流排有兩個特點： (1) 平行多條的資料/位址線’這在資料/位址資訊 的處理頻寬上具有較佳的性能，舉例來說，資 料線由32條增加到64條，在相同的操作時脈 下，頻寬可以增加一倍。 (2) 單一性和同步性（synchronous)，其優點在於時 序關係可以定義的非常清楚，因此在實作上很 方便’有利於實現匯流#兩端元件的通訊協定。 傳統匿流排的平行化和同步化特性固然有其優 點，但是也有下列之缺點：(1) 時脈頻率大致是以8MHz—16MHz—33MHz〜 66MHz—100MHz之軌跡發展。然而，隨著操 作時脈頻率的逐漸提昇，同步化變徉非常困難。 (2) 像是目前大多數電腦系統所使用匯流排的資料/ (請先閲讀背面之注^項再填寫本頁) -订 線 ,1 -I - t^i 本紙張尺度適用中國國家標準·（ CNS ) A4規格（210X297^-1 ) A7 B7 五、發明説明（多） (請先閲讀背面之注意事項再填寫本育) 位址線位元寬度(bit width)為64位元寬度的資 料線’未來可預見的是128位元寬度的匯流排 將會是主流。位元寬度的增加即意味著1C接腳 數量（pin count)的增加，而且所增加的接腳數 相當地大。接腳數量太大則會導致封裝的難度 增加，體積變大等等的缺點。其中以系統控制 器20的接腳數量影響最大（這是因為其必須對 每個與其相連的元件，個別地增加對應的接腳）。 (3) 平行化的資料/位址線在'出現同時切換（由〇變 1 ’由1變0)的情況時，在功率的消耗上會比 較大，同時產生較大的雜訊。 (4) 系統控制器20所能夠處理的資料流量為固定， 所以即使其相連元件透過增加資料/位址接腳數 量的方式來增加頻寬，也不見得可以增加整體 性能。換言之’最後結果可能只是徒然增加接 腳數而已。 經濟部智慧財產局員工涓費合作社印製 緣此’本發明之主要目的即是提供一種具有可 配置資料/位址通道架構之資料處理系統，係利用非 同步資料/位址通道來取代傳統的同步數據匯流排， 系統控制器與其相連元件間係透過複數個通道來傳 送位址/資料’藉由系統控制器中的交換電路模組以 及控制邏輯來決定不同元件之間的通道連接，並可 以根據實際的資料流量需求，決定出所需要的通道 本紙張尺度適用中國國家標準（CNS) A4規格（2【0Χ297公釐） A7 B7 436695 五、發明説明（/) 數量，而增加兩元件之間的傳輸頻寬，達到資料傳 輸的最佳化。 依據前述，該交換電路模組是由資料緩衝器所 構成’具有固定方向、動態方向及多重通道設定組 態，可以是上述三種交換電路模組之任一種，或是 其他變化的模式。透過控制邏輯單元的設定，可以 將交換電路模組中的資料緩衝器根據通道連接的需 求’調整成通道的組態以建立通道傳輸的方向性， 同時也構成通道中的緩衝區。· 依據前述，每個通道本身是獨立運作，以較多 通道進行資訊傳輸時可以獲得較高的資料傳輸速 率。每個通道在設定完成後，需要維持單一方向的 傳輸，藉此可以避免掉回轉時間所造成的時間延遲， 加速資訊傳遞的速度者。 以下將對本發明之結構設計與技術原理，作一 詳細之說明，並參閱附呈之圖式’將對本發明之特 徵作更進一步之瞭解，其中： 圖式說明： 第1圖係為傳統電腦系統的基本架構圖； 第2圖係為習知技術與本發明之差異示意圖； 第3圖係為本發明之第一種架構示意圖； 第4圖係為本發明之第二種架構示意圖； 本紙張尺度適用中國國家揉準（CNS ) A4規格（2丨0X29&釐） ----- ------Λ—-------訂------線 _ (請先閎讀背面之注意項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 /1，' 卜' r · A7 ______B7_ 五、發明説明（〇 第5圖係為本發明的動作流程圖； 第6圖係為固定方向設定組態之交換電路模組 示意圖； 第7圖係為動態方向設定組態之交換電路模組 不意圖， 第8圖係為多重通道設定組態之交換電路模組 示意圖。 圖號說明： 10中央處理器 40 視訊次系統 11系統匯流排 50 PCI元件 20系統控制器 60 系統控制器 21位址匯流排 61 交換電路模組 22資料匯流排 62 控制邏輯 30記憶體 63 傳輸方向設定信號 31記憶體匯流排 64 交換控制信號 本發明之詳細說明： 本發明所採用的架構 ，是以適應型資料/位址通 道模型來取代傳統的匯流排架構，習知技術與本發 明間的差異可由第2圖看出。 在習知的匯流排架構(如第2圖左半部）中，各元 件（如前述，於此圖中以一元件Α通稱之，請配合於 (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4规格（210X 297公釐） 4 3 66 9 5 A7 經濟部智慧財產局員工消費合作社印製 B7 五、發明説明（6 ) 第一圖所示）係以匯流排方式連接上系統控制器20, 原始匯流排包含了位址匯流排21(16位元）以及資料 匯流排22(64位元）。以記憶體存取為例，由於匯流 排之單一性與同步性的特點，此時的存取請求是單 一時間對單一記憶體進行讀或寫圉定位址。對於元 件A本身而言，此種情況即為單一處理程序（single processing) ° 而在本發明所提供的通道架構中，相同的連接 腳數可以構成數條通道CH，每個通道CH則可以依 照需求加以配置。也就是說，在同一時間，對於記 憶體需求可以讀或寫不同的位址。如果以相同前述 之的接腳數量來說，可以組成8個通道CH、每通道 CH有10條信號線。如此即可視實際應用，配置不 同需求不同的通道數量配置，也就是可以讓元件B 進行多重處理程序，達到最佳化的設定。 每個通道CH本身是獨立運作，以較多通道CH 進行資訊傳輸時可以獲得較高的資料傳輸速率。每 個通道CH在設定完成後，需要維持單一方向的傳 輸，藉此可以避免回轉時間所造成的時間延遲。另 外，通道CH與信號線的觀念並不相同，每個通道 CH可能有數條信號線，每條信號線則依照通道傳輸 協定來進行資料的傳送。在本發明中，通道CH本 身的傳輸協定並不特別定義。如果像是在上述範例 (請先閱讀背面之注意事項再填寫本頁) 訂 線！ 本紙張尺度適用中國國家橾準（CNS ) A4規格（2丨0 X 297?^釐） A7 A7 經濟部智慧財產局員工消費合作社印製 五、發明説明（7) 中’利用10條信號線構成一通道，可以定義一條為 時脈線，一條為位址線（以序列傳輸方式傳送），八條 為資料線（以平行傳輸方式傳送卜不過實際可應用之 通道類型可以視情況而改變。 在本發明中，重點在於系統控制器20如何控制 通道CH以及配置通道CH的機制，以下將以二實 施例作詳細說明。 如第3圖所示，係為本發明之第一種架構示意 圖；該系統控制器60 (system controller)的功能類 似於通道管理器的角色，每個通道CH則代表在外 部元件（處理器10、記憶體30或週邊元件）與系統控 制器60之間具有一定傳輪速率的資料流◊系統控制 器60包含有交換電路模組61(switching box)及控 制邏輯62(control logic)兩個部分。該交換電路模 組61係由複數個資料緩衝器（data buffer)所搆 成，可以是固定方向、動態方向及多重通道設定組 態三種交換電路模組61之任一種，或是其他變化的 模式（容后詳述）。該控制邏輯62的主要作用是提供 各元件間訊息的實際傳遞控制，用以控制由資料緩 衝器（data buffer)所構成之交換電路模組61，藉以 在前述之外部元件間構成實際通道CH。 以第3圖中通道CH P1與通道CH Ml之間的 情況為例說明。當CPU 10欲從記憶體30中讀出資 —.!------tA------ir-----.1 線！ (請先閣讀背面之注意事項再填寫本頁) 本紙浪尺度速用中國國家標準（CNS ) A4规格（2!0X29V>釐） 436695 A7 經濟部智慧財產局員工消費合作社印製 五、發明説明（及） 料時，可以設定通道CH Ml的方向為記憶體30— 系統控制器60，設定通道CHP1的方向為系統控 制器60—處理器10。控制邏輯62係根據元件的實 際傳輸需求，產生一組傳輸方向設定信號 63(direction setting signals}以及交換控制信號 64(switching control signals)，用以控制交換電 路模組61中各個資料緩衝器的動作，以建立兩者間 的資訊（包括位址、資料本身）傳遞通道。當某個元件 t 欲傳送資料到另一元件時，必須提供三種訊息： (1) tag(標籤），係指示所要傳送的目的元件； (2) data(資料），係所要傳送的資料； (3 ) address(位址），該資料在該目的元件的定址資 訊。 除此之外，需要傳送的資訊可能還需要包含一 部分的控制信號，這些資訊都可以透過通道CH上 進行傳送。 另外，第3圖所示之各元件和系統控制器60中 的橢圖形標記，係表示通道所對應的界面處理電路 Ι、Γ，連接的雙方需以相同通道傳輸協定來進行資 訊的傳遞。必須注意的是，本發明的重點在於透過 這種通道CH的架構以及其啟動和配置可以是機動 性的，傳統匯流排架構的缺點便可以獲得改善。 系統控制器60在控制位址/資料的流量時，可 (請先閲讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準（CNS ) Α4規格（210Χ2%公釐） A7 B7 五、發明説明（分） —~—- 以根據實際的資料流量需求，決定出所需要的通道 β數量亦即，當某一元件對於資料流量的需求變 得非常大時，系統控制器6〇可以開啟更多的通道， 讓通訊頻寬增加，加速資料的傳遞。而每個元件的 通道CH也可以機動地調整。換言之，本發明通道 CH的總數量為固定的，但通道CH配置係採用動態 的設計。舉例來說，如第3圖所示，系統控制器6〇 連接於處理器10、記德艘3〇、第一週邊裝置、第 二週邊裝置的通道中，設有複數個通道係相通的， 如第3圖左半部的虛線所示，為避免圖式線條眾多 複雜，在此例中僅以處理器與第一週邊裝置為例說 明，兩者間即具有CH col至CH c〇n連結於處理 器10與第一週邊裝置間。在傳輸時’處理器具有8 個通道CH’假設對於第一週邊元件的資訊傳輸需求 非常大而對於處理器10的資訊傳輸需求則相當小 時’可以一方面配置4個通道CH COl〜C04對應 第一週邊裝置，同時僅配置剩餘的通道則對應處理 器10’藉此可以有效率地配置資源（通道CH)的使 用。 每個通道CH每次啟動時只能維持單一傳送方 向，在通道CH内傳送的位址/資料則是透過既定的 傳輸格式進行。這種作法有値好處，就是可以節省 在資訊傳送過程中需要改變傳送方向的轉向時間 本纸張尺度通用中國國家揉準（CNS > A4規210X29砂釐） I 閑 讀 背 * 注Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (/) Summary of the invention: The invention relates to a data processing system with a configurable data / address channel structure, especially a method using asynchronous data / addresses Channels can replace the traditional synchronous data bus, which can determine the number of channels needed based on the actual data traffic requirements, and increase the design of the transmission bandwidth between the two components. Description of the technical background: As shown in Figure 1, it is the basic architecture diagram of the traditional system; general computer systems are summarized as: central processing unit 10 (CPU), system controller 20 (system controller), and memory 30. (memory), video subsystem 40 (video subsystem), and PCI component 50 (peripheral component interconnect device). The connection of the foregoing components uses a bus of a plurality of data lines to transfer data. The system controller 20 is used as a bridge interface between the central processing unit 10 and other system components (such as the memory 30, the video subsystem 40 and the PCI component 50). Taking a general computer system as an example, it is the system chipset (chipsets) Or the North Bridge chip. The system bus 11 (system bus) between the system controller 20 and the CPU 10 includes a plurality of parallel data lines (Data I / O) and address lines (Address I / O). Based on the current Pentium Π and PowerPC as an example, there are 64 data lines and 32 address lines, ----- ^ ------ 1 -------- tr ------ ^ I (Please read first Note on the back, please fill in this page again) This paper size is applicable to the national standard (CNS) A4 specification (210X297 ^ cent) 4 3 66 9 5 Printed by A7 B7 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ;) ~~ " ^ ~ Used to receive / transmit data and addresses in parallel. In addition, the memory bus 3l (mem (^ y bus)) between the system controller 20 and the memory 30 includes 64 data lines and several address lines (different according to different memory types). These Another characteristic of the traditional bus is unity. For example, when the memory 30 is to transmit data to the video sub-system 40, all the data 1/0 and the address ϊ / 〇 will be used at this time. In the memory 30, it is impossible to send data to the video sub-system 40 while also sending data to the CPU 10 °: To put it simply, the above bus has two characteristics: (1) multiple data / address lines in parallel 'This has better performance in the processing bandwidth of data / address information. For example, the number of data lines has increased from 32 to 64. Under the same operating clock, the bandwidth can be doubled. (2 ) Singleness and synchronization. The advantage is that the timing relationship can be clearly defined, so it is convenient in practice to facilitate the implementation of the communication protocol of the components at both ends of the confluence #. Parallelization and synchronization of traditional hidden buses Although the chemical characteristics have their advantages, they also have the following Disadvantages: (1) The clock frequency is roughly developed on the trajectory of 8MHz-16MHz-33MHz ~ 66MHz-100MHz. However, with the gradual increase of the operating clock frequency, synchronization becomes very difficult. (2) Like the current Information about the bus used by most computer systems / (Please read the note ^ on the back before filling out this page)-Alignment, 1 -I-t ^ i This paper size applies to Chinese national standards (CNS) A4 specifications ( 210X297 ^ -1) A7 B7 V. Description of the invention (multiple) (Please read the notes on the back before filling in this education) Address line The bit width is a 64-bit data line 'foreseeable in the future A bus with a width of 128 bits will be the mainstream. An increase in the bit width means an increase in the number of 1C pins (pin count), and the increased number of pins is quite large. If the number of pins is too large, This leads to the disadvantages of increasing the difficulty of packaging, increasing the volume, etc. Among them, the number of pins of the system controller 20 has the greatest influence (this is because it must individually add corresponding pins to each component connected to it). 3) Parallelized data / address lines appear in ' When switching from time to time (from 0 to 1 'from 1 to 0), the power consumption will be relatively large and large noise will be generated at the same time. (4) The data flow that the system controller 20 can process is fixed. So even if its connected components increase the bandwidth by increasing the number of data / address pins, it may not increase the overall performance. In other words, 'the final result may simply increase the number of pins in vain. Staff fee of the Intellectual Property Bureau of the Ministry of Economic Affairs Cooperatives print this' The main purpose of the present invention is to provide a data processing system with a configurable data / address channel architecture, which uses asynchronous data / address channels to replace the traditional synchronous data bus, the system controller The address / data is transmitted through a plurality of channels between the connected components. 'The switching circuit module and control logic in the system controller are used to determine the channel connection between different components, and can be determined according to the actual data traffic requirements. The required channels for this paper are in accordance with China National Standard (CNS) A4 specifications (2 [0 × 297 mm) A7 B7 436695 V. Description Ming (/) the number, increases the transmission bandwidth between the two elements, to optimize the data transfer. According to the foregoing, the switching circuit module is composed of a data buffer, and has a fixed direction, a dynamic direction, and a multi-channel setting configuration, which can be any of the three types of switching circuit modules described above, or other changing modes. Through the setting of the control logic unit, the data buffer in the switching circuit module can be adjusted to the configuration of the channel according to the requirements of the channel connection to establish the directivity of the channel transmission, and also constitute the buffer in the channel. · According to the foregoing, each channel operates independently, and a higher data transmission rate can be obtained when more channels are used for information transmission. After the setting of each channel is completed, it is necessary to maintain transmission in a single direction, thereby avoiding the time delay caused by the turning time and accelerating the speed of information transmission. The structure design and technical principle of the present invention will be described in detail below, and the features of the present invention will be further understood by referring to the accompanying drawings, wherein: Schematic description: Figure 1 is a traditional computer system Figure 2 is a schematic diagram of the differences between the conventional technology and the present invention; Figure 3 is a schematic diagram of the first architecture of the present invention; Figure 4 is a schematic diagram of the second architecture of the present invention; this paper Standards are applicable to China National Standard (CNS) A4 (2 丨 0X29 & PCT) ----- ------ Λ --------- Order ------ Line_ (please first闳 Read the notes on the back and fill in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics / 1, 'Bu' A7 ______B7_ V. Description of the invention (0) Figure 5 is a flowchart of the operation of the invention; Figure 6 is a schematic diagram of a switching circuit module with a fixed direction setting configuration; Figure 7 is a schematic diagram of a switching circuit module with a dynamic direction setting configuration; Figure 8 is a schematic diagram of a switching circuit module with a multi-channel setting configuration Description of the drawing number: 10 CPUs 40 video subsystems 11 systems Bus 50 PCI component 20 System controller 60 System controller 21 Address bus 61 Switch circuit module 22 Data bus 62 Control logic 30 Memory 63 Transmission direction setting signal 31 Memory bus 64 Exchange control signal Detailed description: The architecture adopted by the present invention replaces the traditional bus architecture with an adaptive data / address channel model, and the difference between the conventional technology and the present invention can be seen in Figure 2. In the conventional bus In the framework (as shown in the left half of Figure 2), each component (as mentioned above, is generally referred to as a component A in this figure, please cooperate with it (please read the precautions on the back before filling this page). Order the intellectual property of the Ministry of Economy The paper size printed by the Bureau ’s Consumer Cooperatives applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 4 3 66 9 5 A7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs B7 V. Invention Description (6) (Shown in the figure) is connected to the system controller 20 in the form of a bus. The original bus includes the address bus 21 (16-bit) and the data bus 22 (64-bit). As an example, because of the uniqueness and synchronization of the bus, the access request at this time is to read or write a single memory at a single time. For the component A itself, this situation is Single processing ° In the channel architecture provided by the present invention, the same number of connection pins can form several channel CHs, and each channel CH can be configured according to requirements. That is, at the same time, For memory requirements, different addresses can be read or written. In terms of the same number of pins as described above, 8 channels CH can be formed, and each channel CH has 10 signal lines. In this way, depending on the actual application, the channel number configuration with different requirements is configured, that is, the component B can perform multiple processing procedures to achieve the optimal setting. Each channel CH operates independently, and a higher data transmission rate can be obtained when more channels CH are used for information transmission. After each channel CH is set, it is necessary to maintain transmission in a single direction, thereby avoiding the time delay caused by the turning time. In addition, the concept of the channel CH is not the same as the signal line. Each channel CH may have several signal lines, and each signal line transmits data in accordance with the channel transmission protocol. In the present invention, the transmission protocol of the channel CH itself is not particularly defined. If it looks like the example above (please read the precautions on the back before filling this page). This paper size applies to China National Standard (CNS) A4 (2 丨 0 X 297? ^) A7 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (7) 'Using 10 signal lines For one channel, one can be defined as a clock line, one as an address line (transmitted by serial transmission), and eight as data lines (transmitted by parallel transmission). However, the actual applicable channel type can be changed according to circumstances. In the present invention, the focus is on how the system controller 20 controls the channel CH and the mechanism for configuring the channel CH, which will be described in detail in the following two embodiments. As shown in FIG. 3, it is a schematic diagram of the first architecture of the present invention; The function of the system controller 60 (system controller) is similar to the role of the channel manager. Each channel CH represents a certain transfer wheel between the external components (processor 10, memory 30 or peripheral components) and the system controller 60. The rate data flow system controller 60 includes two parts: a switching circuit module 61 (switching box) and control logic 62 (control logic). The switching circuit module 61 The data buffer (data buffer) is composed of three types of switching circuit modules 61 in fixed direction, dynamic direction and multi-channel setting configuration, or other changing modes (described in detail later). This control The main function of the logic 62 is to provide the actual transmission control of the messages between the components, and to control the switching circuit module 61 composed of the data buffer, so as to form the actual channel CH between the aforementioned external components. The situation between the channel CH P1 and the channel CH M1 in the figure 3 is taken as an example. When the CPU 10 wants to read the data from the memory 30-.! ------ tA ------ ir ---- -.1 line! (Please read the precautions on the back before filling out this page) This paper is a quick-use Chinese National Standard (CNS) A4 specification (2! 0X29V >%) 436695 A7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The description of the invention (and) When the material is set, the direction of channel CH M1 can be set to memory 30—system controller 60, and the direction of channel CHP1 can be set to system controller 60—processor 10. The control logic 62 is based on the component's Actual transmission requirements Direction setting signals 63 (direction setting signals) and switching control signals 64 (switching control signals) are used to control the operation of each data buffer in the switching circuit module 61 to establish information between the two (including the address, the data itself) ) Transmission channel. When a component t wants to transmit data to another component, three kinds of information must be provided: (1) tag, which indicates the destination component to be transmitted; (2) data, which is to be transmitted (3) address, which is the addressing information of the component in the destination. In addition, the information to be transmitted may also need to include a part of the control signals, and these information can be transmitted through the channel CH. In addition, the components shown in FIG. 3 and the ellipsoidal marks in the system controller 60 represent the interface processing circuits I and Γ corresponding to the channels. Both connected parties must use the same channel transmission protocol to transmit information. It must be noted that the focus of the present invention is that through the architecture of such a channel CH and its startup and configuration can be maneuverable, the disadvantages of the traditional bus architecture can be improved. The system controller 60 can control the flow of address / data. (Please read the precautions on the back before filling out this page.) This paper size is applicable to China National Standard (CNS) Α4 specification (210 × 2% mm) A7 B7 5 、 Explanation of the invention (minutes) — ~ —- Based on the actual data traffic demand, determine the required number of channels β. That is, when the demand for data traffic of a certain component becomes very large, the system controller 60 can be turned on. More channels increase communication bandwidth and speed up data transfer. The channel CH of each element can also be adjusted manually. In other words, the total number of channels CH of the present invention is fixed, but the channel CH configuration adopts a dynamic design. For example, as shown in FIG. 3, the system controller 60 is connected to the channel of the processor 10, the Tektronix 30, the first peripheral device, and the second peripheral device. A plurality of channels are connected. As shown by the dashed line in the left half of Figure 3, in order to avoid the complexity of the graphic lines, in this example, only the processor and the first peripheral device are used as an example, and there is a CH col to CH con connection Between the processor 10 and the first peripheral device. During the transmission, 'the processor has 8 channels CH', it is assumed that the information transmission requirement for the first peripheral component is very large and the information transmission requirement for the processor 10 is quite small. A peripheral device that only configures the remaining channels at the same time corresponds to the processor 10 ', thereby efficiently configuring the use of resources (channels CH). Each channel CH can only maintain a single transmission direction each time it is started, and the address / data transmitted in the channel CH is carried out through a predetermined transmission format. This method has the advantage that it can save the turning time that needs to change the direction of transmission during the information transmission process.
項 再 窝 本 I 經濟部智慧財產局員工消費合作社印製 4 3 66 9 5 a? _B7_ 五、發明説明（i D ) (turn-over time)，以加速資訊傳遞的速度。需注意 的是，通道CH與通道CH之間並不需要同步，換 言之，彼此可以獨立完成工作。 如第4圖所示，係為本發明之第二種架構示意 圖；其架構其實是第3圖架構的變化類型，兩者間 差異點僅在於原本透過通道本身傳送的部分標籤(tag) 和控制信號，在第4圖中是利用單獨的接腳來傳送(如 圖中虛線部分control/tag)。這部分可以簡化通道 CH内非資料訊息的時序複雜度，不過也會增加額外 的接腳需求。 另外，在本實施例中，與第3圖同樣具有通道 的機動變化性，與前揭實施例相同。 依據前述可以歸納出如第5圖的流程圖，更能 明白本發明的通道傳輸方式。 步驟a·中央處理器10下達的存取命令。 步驟b·系統控制器60内的控制邏輯62即依據存取 命令或實際傳輸需求，產生一組傳輸方向設 定信號63以及交換控制信號64，用以控 制交換電路模組61中各個資料緩衝器的動 作（設定通道數量、目的、存取方向等），以 建立兩者間的資訊傳遞通道。 步驟c·切換電路模组61依據設定進行緩衝器切換， 連結成資料傳輸的方向性。 (請先鬩讀背面之注意事項再填寫本頁) -訂 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4规格（210X29?公釐） 436695 經濟部智慧財產局員工消費合作社印製 五、發明説明（/ /) 步驟d.資料流由指定的週邊經緩衝器所連結的通道 傳送至目的週邊。 步驟e.存取動作完畢β 如前所述，交換電路模組是由許多資料緩衝器 所構成。在以下說明中，舉出三種交換電路模組的 設定組態，藉以說明交換電路模組的動作。 如第6圖所示，係為固定方向設定組態（Hxed direction setup)之交換電路模組示意圖；在此設定 t 組態中，交換電路模組61中的資料缓衝器只能設定 為單一方向。資料緩衝器A1的資料輸入方向有兩 個，分別來自處理器界面以及相鄰的缓衝器A2 ’同 樣地，其資料輸出方向亦有兩個，分別是到第一週 邊界面（配合於第1圖為視訊次系統40)和相鄰的缓 衝器B1。因此，如果要建立由處理器10界面到第 三週邊界面（配合於第1圖可為記憶體30)之間的通 道CH，可以利用資料緩衝器A1-B1-C1-D1或者是 A3-B3-C3-D3組成，相對地，如果要建立由第三週 邊界面到處理器界面之間的通道，則可以利用資料 緩衝器D2-C2-B2-A2或者是D4-C4-B4-A4(同理 類推）。固定方向設定組態的優點是架構單純，容易 實現，不過資料緩衝器的使用效率並不高。 如第7圖所示，係為動態方向設定組態之交換 電路模組（dynamic direction setup)示意圖；在此 (請先聞讀背面之注f項再填寫本頁) .訂 -線 本紙張尺度適用中國困家捸準{ CNS ) A4規格（210X297^^^ ) 經濟部智慧財產局員工消費合作社印製 厂1:0 . . A7 B7 五、發明説明（/>) 設定組態中’每個資料緩衝器對外的連線是雙向可 設定的’換言之’每個連線的方向是由控制邏輯犯 在配置時加以設定，不過必須注意每個資料緩衝器 雖然具有雙向輸出入連線，但是當通道CH完成配 置後’單向性仍然必須維持’如此才能夠避免回轉 時間（turn-over time)。由於利用動態方向設定組態 時需要進行資源的有效配置，並且雙向連線在實施 上也比較複雜’因此成本較高；不過在資料緩衝器 的使用效率上比較高β 如第8圖所示’係為多重通道設定組態（multi-channel setup)之交換電路模組示意圖；在此設定 組態中，每個資料緩衝器的對外連線方向也是雙向 的，不過並不是所有的資料緩衝器都可以任意的配 置，其中左半部的資料緩衝器只能夠配置給處理器10 通道、第 0 週邊界面 PIO(peripheral interface 0) 和第1週邊界面PI1之間的通道，而右半部的資料 緩衝器則只能夠配置給處理器通道、第2週邊界面 PI2和第3週邊界面PI3之間的通道。另外，在第8 圖所示的設定組態中，實際通道數董會高於資料缓 衝器的數量。 交換電路模組61是由資料緩衝器所構成’其模 式可以是上述三種交換電路模組之任一種，或是其 他變化的模式，透過控制邏輯62的設定’可以將交 本紙張尺度逍用中國國家榡準（CNS ) A4规格（210X29]梦釐） -----------/-------1T------^ 1 (請先閱讀背面之注意事項再填寫本頁) 436695This item is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 3 66 9 5 a? _B7_ V. Description of Invention (i D) (turn-over time) to accelerate the speed of information transmission. It should be noted that the channel CH and the channel CH do not need to be synchronized, in other words, work can be completed independently of each other. As shown in Figure 4, it is a schematic diagram of the second architecture of the present invention; its architecture is actually a type of change in the architecture of Figure 3. The difference between the two is only the part of the tags and controls originally transmitted through the channel itself. The signal is transmitted using a separate pin in Figure 4 (as shown by the dashed line control / tag in the figure). This part can simplify the timing complexity of non-data messages in the channel CH, but it will also add additional pin requirements. In addition, in this embodiment, the maneuverability of the passage is the same as that in Fig. 3, which is the same as that in the previous embodiment. According to the foregoing, the flowchart as shown in FIG. 5 can be summarized, and the channel transmission method of the present invention can be more clearly understood. Step a. An access command issued by the central processing unit 10. Step b. The control logic 62 in the system controller 60 generates a set of transmission direction setting signals 63 and exchange control signals 64 according to the access command or actual transmission requirements, and controls the data buffers in the switch circuit module 61. Actions (set the number of channels, purpose, access direction, etc.) to establish a channel of information transmission between the two. Step c. The switching circuit module 61 performs buffer switching according to the setting, and connects the data transmission directionality. (Please read the notes on the back before filling this page)-Order the paper size printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs to apply the Chinese National Standard (CNS) A4 specification (210X29? Mm) 436695 Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the employee consumer cooperative V. Description of the invention (//) Step d. The data stream is transmitted from the designated periphery to the destination periphery through the channel connected by the buffer. Step e. The access operation is completed β As described above, the switching circuit module is composed of a plurality of data buffers. In the following description, the setting configurations of three types of switching circuit modules are listed to explain the operation of the switching circuit modules. As shown in Figure 6, it is a schematic diagram of a switching circuit module with a fixed direction setup (Hxed direction setup); in this setting t configuration, the data buffer in the switching circuit module 61 can only be set to a single direction. There are two data input directions for data buffer A1, which are from the processor interface and the adjacent buffer A2. Similarly, there are two data output directions, which are to the first peripheral interface (coordinated with the first The picture shows the video sub-system 40) and the adjacent buffer B1. Therefore, if you want to establish the channel CH from the interface of the processor 10 to the third peripheral interface (memory 30 in conjunction with the first figure), you can use the data buffer A1-B1-C1-D1 or A3-B3 -C3-D3 composition. In contrast, if you want to establish a channel from the third peripheral interface to the processor interface, you can use the data buffer D2-C2-B2-A2 or D4-C4-B4-A4 (same as Analogy). The advantage of fixed-direction configuration is that the structure is simple and easy to implement, but the efficiency of the data buffer is not high. As shown in Figure 7, it is a schematic diagram of a dynamic direction setup configured for a dynamic direction setup; here (please read the note f on the back before filling this page). Applicable to China ’s poor families {CNS) A4 specifications (210X297 ^^^) Employees ’Cooperative Cooperative Printing Factory of the Intellectual Property Bureau of the Ministry of Economic Affairs 1: 0.. A7 B7 V. Description of the invention (/ >) The external connection of each data buffer is bidirectionally configurable. In other words, the direction of each connection is set by the control logic during configuration. However, it must be noted that each data buffer has two-way input and output connections, but When the channel CH is configured, the 'unidirectionality must still be maintained' so as to avoid the turn-over time. Because the configuration of the dynamic direction is required to effectively configure the resources, and the two-way connection is more complicated to implement, so the cost is higher; but the efficiency of the use of the data buffer is relatively high β as shown in Figure 8 ' It is a schematic diagram of a switching circuit module for a multi-channel setup. In this configuration, the external connection direction of each data buffer is also bidirectional, but not all data buffers are It can be arbitrarily configured, in which the data buffer in the left half can only be allocated to the channel of the processor 10 channel, peripheral interface 0 (PIO (peripheral interface 0) and PI1), and the data buffer in the right half The processor can only be configured for the processor channel, the channel between the second peripheral interface PI2 and the third peripheral interface PI3. In addition, in the setting configuration shown in Figure 8, the actual number of channels is higher than the number of data buffers. The switching circuit module 61 is composed of a data buffer. Its mode can be any of the three types of switching circuit modules described above, or other changed modes. Through the setting of the control logic 62, the paper can be used in China. National Standard (CNS) A4 Specification (210X29) Dream Li) ----------- / ------- 1T ------ ^ 1 (Please read the precautions on the back first (Fill in this page again)
換電路模組61中的資料緩衝器根據通道CH連接的 需求，調整成通道CH的組態以建立通道CH傳輸 的方向性，同時也構成通道CH中的緩衝區。 經濟部智慧財產局員工消費合作社印製 综上所述，本發明所提供之具有可配置資料/位 址通道架構之資料處理系統，能透過複數個通道來 傳送位址/資料，及藉由系統控制器中的交換電路模 組以及控制邏輯來決定不同元件之間的通道連接， 並可以根據實際的資料流量需求，決定出所需要的 通道數量，而增加兩元件之間的傳輸頻寬，達到資 料傳輸的最佳化；對於傳統的單一處理程序之匯流 排缺失提出有效之解決辦法及對策，確實已符合創 作專利之申請要件，懇請鈞局詳加審查，並惠賜准 予專利，以嘉惠民生利國利民，實感德便。 唯以上所敘述之技術、圖說、程式或控制等方法， 僅僅係本發明較佳實施例之一而已；舉凡依本發明 申請專利範圍之技術所作之均等變化或修飾或擷取 部分功能之雷同製作，皆應仍屬本發明專利權所涵 蓋之範圍；當不能依此限定本發明實施之範圍。 (請先聞讀背面之注意事項再填寫本頁) 訂 線！ 本紙張尺度適用中國國家標準（CNS > Α4規格（210X29?分釐）The data buffer in the switching circuit module 61 is adjusted to the configuration of the channel CH to establish the directivity of the transmission of the channel CH according to the needs of the channel CH connection, and also forms a buffer in the channel CH. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs In summary, the data processing system provided by the present invention with a configurable data / address channel structure can transmit addresses / data through multiple channels, and through the system The switching circuit module and control logic in the controller determine the channel connection between different components, and can determine the required number of channels according to the actual data flow requirements, and increase the transmission bandwidth between the two components to achieve the data Optimization of transmission; effective solutions and countermeasures for the lack of traditional single processing buses have indeed met the requirements for the creation of patents, and we urge you to examine them in detail and grant the patents to the benefit of the people. Health benefits the country and the people, I really feel virtuous. Only the methods, techniques, diagrams, programs, or control methods described above are just one of the preferred embodiments of the present invention; for example, all equivalent changes or modifications or extraction of some functions made according to the patented technology of the present invention are similarly produced Should still fall within the scope of the patent right of the present invention; when the scope of implementation of the present invention cannot be limited accordingly. (Please read the notes on the back before filling this page) Order! This paper size applies to Chinese national standards (CNS > Α4 size (210X29? Centimeters)