TW538433B - Body contact in SOI devices by electrically weakening the oxide under the body - Google Patents

Body contact in SOI devices by electrically weakening the oxide under the body Download PDF

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Publication number
TW538433B
TW538433B TW091104816A TW91104816A TW538433B TW 538433 B TW538433 B TW 538433B TW 091104816 A TW091104816 A TW 091104816A TW 91104816 A TW91104816 A TW 91104816A TW 538433 B TW538433 B TW 538433B
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substrate
ions
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oxide
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TW091104816A
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Sundar K Iyer
Devendra K Sadana
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Ibm
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/66772Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743Making of internal connections, substrate contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

538433 A7 B7 五、發明説明(1 ) 發明領域 本發明頜域係為具有本體接觸之氧化物之絕緣物上矽之 積體電路。.、 發明背景 在氧化物之絕緣物上矽之積體電路中,一熟知之問題係 為N型場故電晶體(NFET)及P型場效電晶體(PFET)本體中分 別之電洞/電子的堆積,改變該電晶體之驅動力。標準的解 答係為對該電晶體本體製作一接觸,提供一接地的路徑以 排放電荷。不幸的是,大部分之本體接觸消耗極寶貴之矽 面積(area)。在少數案例中,該接觸的製作可以藉由僅於該 源極與汲極之下選擇植入氧氣,或是藉由在該嵌入之氧化 物(Si〇2)中蝕刻一電洞並填充一導體。選擇植入很貴且費時 。在現存技術中,不適合做小型特徵大小之電晶體。此外 ,必須得製作某種對準之參考,以將該等電晶體置於正確 的位置。在該電晶體本體下蝕刻一電洞並以一絕緣體來填 充,需要許多額外之處理步驟並且很昂貴。在該電晶體本 體中矽之品質也會在處理過程中變差。 發明概要 本發明有關一種形成一本體接觸之方法,藉由在該電晶 體本體之下建立一導體路徑穿過該嵌入之絕緣體下至該矽 基板。 本發明之一特徵係為將離子植入穿過該電晶體本體,並 植入該嵌入之絕緣體中,接著應用一電壓足夠擊穿該氧化 物,並建立一導體路徑於該電晶體本體與該基板之間。 -4 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 裝 訂
線 538433 A7
圖式簡單 圖1至4示範處理過程中不同之階段。 圖5示範一完成之電晶體。 圖6示範應用偏壓於形成於該基板中之井等上。 較佳具體實方fe例 月’考圖1 ’其中示範一半導體作用區3 〇(以矽做示範) 之剖面視圖.,其以淺槽隔絕(STI)構件等35來包圍。區域 ^〇ίτ、置於一絕緣層2〇之上。整個以大塊基板ι〇來支持, 不範的是摻雜ρ-型。示範層2〇係藉由植入氧氣形成,接 以问溫(〜1 300。〇退火,在文獻中稱為5刚〇乂法(以植入 氧氣隔絕)。 兒晶體將於作用區3〇中形成’其本體將連穿層2〇至基 板10 °以根擄本發明形成之傳導路徑,將會有一路徑以自 該操作中之電晶體本體排放電荷。 圖2示範冗積一層氧化物(si〇2)40及一層抗蝕劑50的結果 ’於4抗钱劑中形成一孔5 2。選擇抗餘劑與氧化物的總厚 度’以阻擋(block)該等即將植入之離子不至達到裝置層30 。在示範之圖中,氧化物層40之厚度約為500nm,而抗蝕劑 5 0之厚度約為1,〇 〇 〇 n m。該氧化物與抗钱劑可以以高達 2 OOkeV之能量阻擋植入之離子達到該孔外邊之矽。 圖3示範於氧化物40中#刻一孔54,並經過該孔將一劑離 子植入至該嵌入氧化物(BOX),並恰於其下的結果,該離子 植入區以數字25來表示。如果需要的話,可以變化該等離 +的能量,使得該離子植入區整個延伸過該氧化物。該離 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐)
k 538433 五、發明説明(3 ) 子能量值將取決於裝置層30與3〇又2〇的厚度。五人於現在 左右的劑量,已足夠將_26nm厚之(高°^_ 極氧化物的電擊穿場^18MV/cm大大地降低至y3MV/cm 。該劑量之大小將由植入區域的厚度來決定;SIM0X曰圓 較接合之晶圓好’因為其具有相當之未反應之石夕的量二 以貢獻做傳導路徑。較佳的是,以—直向反應離子姓刻來 勤穿該氧化物40,使得該孔具直牆。 吾人發現鉬可以滿足降低該氧化物之擊穿電壓,但是熟 知此項技藝之人士可以使用其他的選擇。其他適合產生較 低之擊穿電壓之離子等,包括至少與矽一樣重之離子,尤 其是在週期表中之第111與IV行中的離子,例如鎵、鈦、矽 、鍺、錫、船、金與鐵等。 如果需要,該電晶體本體可以經過一井連接,其依次連 接至該晶圓表面上之一接觸。該結構示於圖6中,其中一 P-井15與一 n-井115分別具有本體接觸25與125。接觸25可以 使用Ρ-型離子(例如硼)製作,而接觸125可以使用卜型離子 (例如磷、砷或是銻)製作。 ρ-井15具有一額外之接觸2 6,其接觸於該裝置層中之一 ρ-型植入區4 9。區域49,則具有一垂直接觸構件4 9,,其連 接至一偏壓源。類似地,η-井Π 5具有一接觸126穿過Β〇Χ 20,在該BOX中有一η-型植入區126、一η-型植入區149及一 接觸構件149’。因此,兩井可以隨意偏壓,例如井15用負 電壓或是接地’井115用正電壓。 在藉由植入來電氣弱化該氧化物後,該電晶體之處理可 -6- 本紙浪尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐) 538433 A7 B7 五 發明說明(4 ) 、%下去 方法為使用该掩蔽氧化物以於本體接觸25 ^上方形成—自我對準的問極。現在請參考圖4,在孔洲 :部已成長-閉極氧化物42 ’並已沉積—層多晶石夕且以化 :機械研磨法研磨’使用氧化物4〇之上表面做一拋光停止 “乂形成閘極45。另一種處理方法係在植入接觸25之後, 將该沉積之抗I虫劑與氧化物層4〇移除。然後該電晶體可以 傳.·充之處理來衣造。因為Β〇χ弱化之微影蝕刻以該 丁故刻記號為參考來對準,該相同之參考可以使用做問極 ,定義。此允許該等電氣弱化Β〇χ之區域直接出現於該Ν型 场效電晶體與Ρ型場效電晶體的本體下。該第二法並非自我 對準,但是接觸25與本體之對準並不是最緊要的。 圖5示範該完成之電晶辦, ‘, 具閘極4)、邊牆47、源極/汲 ㈣與本體接觸25。其他之習知的㈣,如於閑極、源極 與及極上形成石夕化物’並形成内連與中間介質層以連接電 «來形成電路等’將被集合稱為、'完成該電路。類似 地’習㈣預備步驟’如形成襯塾氧化物及氮化物、形成 S'TI、臨界值調整植入’及類似的步驟,因專利之故將稱為 備製該基板"。 在離子植入後任何方便之時間,可以應用一適當之電壓 以擊穿該氣化物。該電壓應跨越該B〇x產生_電場,其值 高於該BOX、、弱化"F A々船六# π化區域之擊穿值,但卻低於未植入Β〇χ 區域之必t兒壓。此舉可藉由將該晶圓曝光於一電漿來完 成,其具偽壓條件組使得該電漿電壓可以對擊穿有貢獻。 或者,可以沉積一暫時之金屬層或是電鍍(或是將一導電液 本紙浪尺度適用中國國家樣準(CNS) A4規格(210X297公嫠]------—— 裝 訂 538433 A7
塗佈於该上表面)以提供一接觸,另 上。對一厚度為100ηιη之BOX來說, 於50 V,桓是可以隨離子劑量的大 化0 基板 約小 而變 一接觸則應用於該 该電壓的大小較佳 小、離子種類等等 該術語、'擊穿〃纟此使用的意思為失去該氣化物之絕緣 特質’且該氧化物、'漏電”(約低於1〇6歐姆卜其並不必為 -導體’尸、要具有夠高之電漏’使得該等電洞可以穩定地 排放。 較佳的是在該閘極氯仆妨7 +且+ ^ &你/ m炫礼化物成長之前進行此弱化植入,以 保護該閘極氧化物不致受到植入的損壞。 雖然本發明僅以一單_較佳具體實施例來說明,對熟知 此項技藝之人士而f,便可明瞭本發明可以有^之變化 ,卻仍在以下申請專利範圍之精神與範疇之内。 -8- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公董i -----—

Claims (1)

  1. A8
    一種形成 備製_ 絕緣體層 p積te電路之方法,包含以下步驟: 半夺體晶圓,其具有一位於半導體基板之上的 之上的半導體裝置層; , 、,.包日日胆+肢位置内植入一劑離 W制離子使用之枯 At旦/土 d-Λ 伸八枝 入犯置使付離子從該等本體位置 π佈過該絕緣體層並進入該基板; 岸;亥衣置層與該基板之間施加一電壓 9之材料被擊穿並變成具傳導性;以及 成組電晶體並連接該組電晶體 ’使得該絕緣體 以形成該積體電
    2. 3 . 4. 5 . 6. 如申請專利範圍第1項之方法 &緣體為氧化物。 如申請專利範圍第2項之方法 第m行之離子。 其中該裝置層為矽,且該 其中該等離子係為週期表 $申請專利範圍第2項之方法,其中該等離子係 第IV行之離子。 如申請專利範圍第2項之方法,其中該等離子從 鍺、銦、銷、鈦、金與鉑所組成的群組之中選注 如申請專利範圍第2項之方法,其中一^^型立^效 電晶體本體係摻雜之ρ-型,且該基板在該組電 之一區係推雜之Ρ-型。 如申請專利範圍第2項之方法,其中一 ρ型場效 電晶體本體係摻雜之η-型,且該基板在該組電 之一區係4參雜之η型。 週期表 、鎵、 晶體組 本體下 晶體組 本體下 裝 玎 籲線 -9-
TW091104816A 2001-03-16 2002-03-14 Body contact in SOI devices by electrically weakening the oxide under the body TW538433B (en)

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