TW533573B - Layout method for probe card - Google Patents

Abstract

The present invention discloses a layout method for probe cards that is suitable to test integrated circuit chips. The layout method for the probe cards of the present invention first unifies the standard of the pitch between adjacent solder balls and provides a couple of the quality standards of the ranks of solder ball arrays. Then, a number of probe array layouts are designed according to the standards of the pitch and the arrays of the solder balls on the chip. In the present invention, the probe pitch of the probe array layout is the same with the standard of the pitch between the solder balls, and the scales of the probe arrays are equal to or greater than those of the solder balls, so that a suitable probe card is provided according to the different array standards while various kinds of chips are tested. Therefore, the consumed time, manpower and cost for manufacturing the probe cards can be saved.

Description

533573 A7 ------_ ___ V. Description of the invention () Field of the invention: The present invention relates to a kind of probe card cloth. (Please read the precautions on the back before filling out this page) (Layout) method, especially the method for exploring a vertical stylus. Fabric invention background: During the production of Integrated Circuits (1C), product testing steps are performed at different stages of the process, and precision analysis equipment is used to make quality control decisions throughout the entire process. Various inspections to ensure that the process yield and wafer quality can reach the best level, and to detect defects in the integrated circuit during the manufacturing process. Then, find out the cause of the product defects, so as to further ensure that the product quality meets the standards and achieve the purpose of improving the process yield. Therefore, in the manufacturing process of integrated circuits, testing is an important step to improve the yield of integrated circuit components and to establish effective data for engineering analysis. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs to distinguish the timing of testing, testing of integrated circuit products can be mainly divided into chip pin testing (Chip Pr0be; CP, also known as Wafer Sort) and finished product testing (F ina 1 T est; FT 'also known as package T est) two stages. Among them, the wafer pin testing step is performed when the wafer is in the form, so as to distinguish the good and bad of the die before packaging to avoid unnecessary waste. Furthermore, the function of chip pin test is to detect the defects of the integrated circuit during the manufacturing process and find out the reason, to ensure the product yield, and provide test data for the integrated circuit design and manufacturing analysis. use. The finished product test is performed after sealing, to ensure that the chip still meets the specifications after the packaging process. 3 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 533573. 5. Description of the invention (). (Please read the precautions on the back before filling in this page.) Because the chip pin test system is used for the electrical function of the chip, the integrated circuit first transitions out of the electrical function before entering the structure, so as to avoid the increase of defective products. manufacturing cost. Therefore, wafer pin testing = testing the electrical characteristics of each die in the wafer and the purpose. Another purpose of wafer pin testing is to test the yield of the product. Rate to determine whether the wafer manufacturing process is biased. When ^ = high, it means that the wafer manufacturing process is all normal; and when the yield rate is: second rate, the table is not in the wafer manufacturing process, and there is a check as soon as possible to correct it. When a problem occurs, "when chip testing of integrated circuits must be performed, first use the tester to send the electrical signals required for the chip to be tested", and then pass the test head connected to the tester's electric injection, and then pass through the test head's pin test board The probe transmits the electrical signal to the chip under test. When the chip under test receives the electrical signal from the tester, the chip under test will generate a response electrical signal, and the probe will respond to the electrical signal through the probe on the pin test board. Pass to the test machine. At this time, the 'test machine' judges the electrical test result of the product based on the returned electrical signal. Among them, the control details in the testing machine, β q 疋 is protected by a test program (T e s t P r 〇 g r a m) written for the chip under test. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs at present, in response to the demand for high input / output (I / O) numbers, high heat dissipation, high efficiency, and size reduction of integrated circuits The circuit's package type is oriented towards high-level chip scale packaging (CSP) and flip-chip (Flip). This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 public love) 533573

V. Invention Description (Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

(ChlP; FC) packaging trend headless ancient 6 — another / beijing Jin, because the flip-chip bonding technology has the same, "degree, short connection ^ paste p bucket ^ low inductance, high frequency noise easy to control" and With advantages such as reduced package size, it is widely used in the packaging process of integrated circuits. …, And, with the increase in the number of integrated electric wheels, the number and distribution density of… In order to match the number of fish and fish ratios, the solder ball layout with increasing whiteness can be made long: for a large number and welcome. The vertical pin test board of the Alfero probe is widely used for testing of integrated circuits. It depends on μ 丄, and then the test S is prepared, and the test equipment is generally run by the test equipment. The test equipment and equipment provided by the manufacturer are quite expensive. On the other hand, with the continuous shortening of the life cycle of integrated circuit = 'and the increasing complexity of integrated circuit functions', the price of integrated circuit test equipment is becoming increasingly heavy. For example, 'for each different chip to be tested, it is usually necessary to provide different pin test boards' to comply with the layout of the fresh solder balls on the chip to be tested before testing. In this way, when testing the wafer to be tested, the test cannot be performed immediately, but the solder ball layout of the wafer to be tested must first be used to rebuild a suitable probe board. Therefore, not only is it time-consuming and wasteful of human resources, it also leads to a significant increase in the cost of the testing step, which is not economically beneficial. Purpose and summary of the invention: In the above-mentioned practice, when testing integrated circuit wafers, it is necessary to redesign and make suitable probe boards for different wafers, which will result in round-off, time and human resources, and cause manufacturing processes. The cost burden seriously affects the product. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). Ί—Γ ..... 变 ......... Order ... ..Violent (please read the precautions on the back before filling this page) 533573 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the invention description () Timeliness. ::, The main purpose of the present invention is to provide — Bureau Method. The probe pin of the present invention is a vertical type, which is suitable for wafers of the plate crystal type. By unifying; / is called to cover a μ, the distance between adjacent solder balls on a daily basis, row specifications And according to the distance and array of 1 dry solder balls, see here, to arrange the probe array of the probe board, and provide several gates: the probe board of the small probe array. Therefore, when the same 1 After selecting the probe array = solder ball array from some probe test boards, directly measure the wafer to be tested. . Therefore, the waiting time for wafer test of Nakata Niu Ni to improve the yield. The purpose of the present invention is that the probe array layout of the probe board can be used for the layout of the array of fresh solder balls on various wafers without the need for different crystals. After redesigning and manufacturing the probe board, you can directly use the existing probe board for testing. Because & not only can save the time, labor, and cost of rebuilding the probe board, but also improve the timeliness of the product According to the above-mentioned object, the present invention further provides a pin test board layout method suitable for testing a wafer, wherein the wafer includes at least one solder ball array, and the solder ball array includes at least a plurality of solder balls. The layout method of the pin probe board of the present invention includes at least: unifying the first preset size of the solder ball array, unifying a first preset distance between adjacent fresh solder balls; providing a pin probe board; A probe array is formed on the board, and the probe array has a second predetermined size, and the probe array includes at least a plurality of probes, wherein a first This paper applies a preset scale between China National Standard (CNS) A4 size (210X297 mm) J tr (Please read the Notes on the back of the field and then write this page} 533573 A7 B7 V. invention is described in ()

The printed distance of the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and the second preset distance between adjacent probes is approximately equal to the first preset distance between adjacent solder balls on the wafer. In addition, the second preset size of the probe array on the probe board of the present invention must be equal to or larger than the first preset size of the solder ball array on the wafer, that is, the detection of the rows and columns of the probe array The number of pins must be equal to or greater than the number of solder balls in the rows and columns of the solder ball array. In this way, the probe board of the present invention can be applied to wafers with a variety of solder balls of different array sizes. Schematic illustration of the application: The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures, where: Figure 1 shows a preferred implementation of the present invention Sectional schematic diagram of a pin probe board of an example > FIG. 2 is a solder ball layout diagram of a wafer showing a preferred embodiment of the present invention. FIG. 3 is a diagram of a preferred embodiment of the present invention. Sensing probe plate layout view; and Figure 4 is a schematic diagram of the present invention other than the best solid probe layout view of a needle plate of the embodiment of the measurement. Drawing number comparison description: 100 printed 'circuit board 102 pin test board 104 probe 106 pitch 200 wafer 202 solder ball 204 pitch 300 pin test board This paper size applies to China National Standard (CNS) A4 specification (210X 297 mm)- -: r ..... fees ........., but ... (Please read the notes on the back before writing this page) Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative A7 B7 · V. Description of the invention (302 probes ^ ... pin probe board = pitch 354 pitch ~ probe invention detailed description: The present invention discloses a layout method of the pin probe board, the distance between the solder ball array of the chip With the array, the first, the first: the ball array: the distance between the array and the specifications of the array of probes to form a plurality of sets of probe boards: ^ 2 made probe boards with different probe array specifications. That is to say, for the solder of the wafer to be tested: directly select the applicable one from the pre-made pin test board, and use the test board to test the wafer. In order to make the invention: complete and complete, you can refer to the following description And cooperate with Figures 1 to Figure 4: Please refer to Figure 1, 帛! The drawing is a schematic cross-sectional view of one of the present invention compared to a stylus board. The vertical stylus board 102 is generally: Printed Circuit B 〇ard; pcB) i〇〇 之 ： 上 'and the probe board 102 includes at least a plurality of probes i04 located on and above. Because the probe 104 on the probe board 102 can be made into Quite subtle ...-Come, you can also increase the density of the probe 104 on the probe board 102. The vertical probe board 102 can be used to test zinc tin. Nanzhi flip-chip packaged wafer. Please refer to Figure 2. Figure 2 shows the solder ball layout of a wafer of a preferred embodiment of the present invention. Chips for integrated circuits 200 are covered on the paper scale. Applicable to China National Standard (CNS) A4 specification (210X297 public love)

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S 533573 A7 B7 V. Description of the invention () ..... I (Please read the precautions on the back before filling out this page) Package, chip 200 has a regular array of solder balls 202 array, two adjacent There is a distance of 204 between the solder balls 202. The chip 200 may be, for example, a memory element, a logic element, an embedded memory element, a mixed signal element, or the like. When the pin 200 is used to test the wafer 200, the probe 200 of the pin 200 must be in electrical contact with the solder ball 202 of the wafer 200. Therefore, the distance 106 between two adjacent probes 104 of the pin test board ι2 must be equal to the distance 204 between two adjacent solder balls 202, in order to perform the test smoothly. Because the current packaging technology trend is to unify the pitch 204 of two adjacent solder balls 2002, and according to product requirements, multiple sets of solder ball 202 arrays of different array sizes are determined. Therefore, according to the trend of this packaging technology, the present invention proposes a universal pin probe board layout.

S Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Please refer to FIG. 3, which is a diagram showing a probe layout of a probe board according to a preferred embodiment of the present invention. The layout method of the probe board of the present invention is to first unify the array specifications of the solder balls 200 of the wafer 200 according to the current product requirements, such as 15x20, 12x12, etc., and then unify two adjacent fresh tins of the wafer 200 The distance between the balls 202 is 204. If you have the standard 2Q2 array of solder balls and the size of pitch 204, you can use it directly. According to the specification of the array of solder balls 202 of # 200, and the distance between two adjacent solder balls 002, a probe 302 array layout is planned on the probe board 300. The layout of the probe 302 array is such that the distance 3G4 between two adjacent probes 302 is approximately equal to 5 giant 204 between two adjacent fresh solder balls 202, and the size of the probe 302 array is not less than Scale of 2 0 2 array of solder balls. 9 Regulations 4 A S) N C Tendering Country Moderate Use Moderate Rule Paper

Chu Gong 7 9 2 X 533573 A7

V. Description of the invention () Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, that is, in each row of the solder ball 202 array, there are 7 solder balls 202 'and in each column of the solder ball 2 () 2 array , 胄 $ 个 鲜 锡 球 2 0 2, as expected in the 9-country price dagger-Ge Le 2 map does not. Therefore, the number of probes 302 in each row of the probe 302 array must be at least equal to 7, and in each column of the probe 302 array, the number of probes 302 must be at least equal to 5, as Figure 3 does not. In this way, the probe plate 300 can be used to test the wafer 200 in Figure 2. In addition, as shown in Figure 4, in the probe 352 array layout on the probe plate 350, any two adjacent probes The distance 354 between 3 and 52 is approximately equal to the distance 402 between two adjacent solder balls 202 of the wafer 2000. Furthermore, in the probe / array arrangement, each row contains 9 probes 352, and each column contains 7 probes 352. Because, in the array of solder balls 202 of the wafer 200, each row contains only seven solder balls 202, and each column contains only five solder balls 202. Because of & the stylus board 35 can also be used for wafer 200 testing. In addition, although the chip 200 is known to have various functionalities, such as drivers, input / output channels (I / O Channels), etc., depending on the design requirements of the components. However, by adjusting the test machine (not shown), the test can be performed smoothly without the need to uniformly specify the placement positions of the solder balls 202 with different functions. One feature of the present invention is to provide a plurality of sets of probe array probe array layouts according to a public or industry-unified solder ball array layout, and to make spare probe arrays in advance according to these probe array layouts. When the wafers of different products enter the paper size, the Chinese National Standard (CNS) A4 specification (210X297 mm) is applicable. . ^ 0 (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed 533573 V. Description of the invention (): Speculation: Hours, you can start from the pin test board prepared in advance, Select the board 'to test directly. The invention of the pin-tap invention—the advantage is to provide—a layout method of the stylus board. The layout of the stylus board is suitable for the cloth of the vertical stylus board. Wafer. Based on the distance between the two adjacent solder balls on the wafer and the array specifications of the solder balls1, the probe pin p can be planted according to the distance between the solder balls and the array specifications to prepare arrays of probe arrays with different sizes. Stylus. When testing various wafers, you can directly select the probe array from the previously prepared probe test board that is equal to or larger than the solder ball array of the test board to test the test board. Therefore, the time for re-producing the pin test board can be saved, and the time to be tested for the chip can be effectively reduced, thereby achieving the purpose of increasing the yield. Another advantage of the present invention is that the probe array of the stylus board can be applied to the solder ball array of different wafers. There is no need to redesign and make the stylus board according to the different products. carry out testing. Therefore, not only can save the time, labor and cost of re-producing the stylus plate, but also the product can obtain better timeliness. As understood by those familiar with this technology, the above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all others completed without departing from the spirit disclosed by the present invention Equivalent changes or modifications should be included in the scope of patent application described below. 11 This paper size applies to China National Standard (CNS) A4 specifications (210X297 mm), ..... # · --------, order-: ...... «6 Jingxian read (Notes on the back, reprint this page)

Claims (1)

533573 ABCD applied for a patent scope l A layout method of probe card (Probe Card), applicable; "Yes," "Where the wafer includes at least one solder ball array (Solder Ball) array" and the solder ball array at least It includes a plurality of solder balls, and the method of arranging the stylus board at least includes: unifying a first preset size of the solder ball array; unifying a first preset distance between adjacent solder balls to provide the pin A measuring pin; and forming a pin array on the pin measuring plate, and the probe array has a pre-sighed size, and the probe array includes at least a plurality of probes, among which there are- The second preset pitch is approximately equal to the first preset pitch of the solder balls, and the number of the probes is not less than the number of the solder balls. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 · The layout method of the pin probe board as described in the application scope of the patent application 帛 i, wherein the second preset size of the probe array is equal to that of the solder ball array First preset size. Take the layout of the stylus board as described in item i of the patent application scope where the second preset size of the probe array is larger than the first preset size of the solder ball array. μ 12 This paper size is applicable to China National Standard (CNS) A4 (2ι〇 × 297 Gongfeng) ........... # ....... ..J (Please read the notes on the back before filling this page >!) 33573 A8 B8 4 · The method of arranging the stylus board as described in item 1 of the scope of patent application. /, The stylus board is a vertical stylus board. 5. The layout of the stylus board as described in item 丨 of the patent application, wherein the chip is a memory device. 6 · The layout method of the stylus board as described in item 1 of the claim, wherein the chip is a logic element.彳 The layout method of the stylus board described in item No. 丨 of the scope of patent application of 7 · T. The Japanese film of the eighth day is an embedded memory device. 8. The layout method of the stylus board as described in item 1 of the patent application scope of the claim, wherein the chip is a mixed signal component. Please read the back notice before ordering printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs. 9 · A layout method of a pin test board, suitable for testing a chip, where the B chip includes at least one solder ball array, and the solder ball array At least a plurality of solder balls are included, and the method of arranging the stylus board includes at least: unifying a first preset size of the solder ball array; unifying a first preset distance between adjacent solder balls; providing The probe plate; and forming a probe array on the probe plate, the probe array having a second preset size, and the probe array including at least a plurality of probes, of which 13 paper standards are applicable to China National Standard (CNS) A4 specification (210X297 mm) 533573 AB CD 6. There is a second preset distance between the probes adjacent to the patent application range, and the second preset distance is approximately equal to that of the solder balls. The first preset pitch, and the first preset size of the solder ball array 歹 | J is not smaller than the second preset size of the probe array. 10. The method of layout of a stylus board as described in item 9 of the scope of patent application, wherein the stylus board is a vertical stylus board. 1 1. The layout method of the stylus board as described in item 9 of the scope of patent application, wherein the chip is a memory element. 1 2. The layout method of the stylus board as described in item 9 of the patent application scope, wherein the chip is a logic element. 1 3. The layout method of the stylus board as described in item 9 of the scope of patent application, wherein the chip is an embedded memory device. 1 4. The layout method of the stylus board as described in item 9 of the scope of patent application, wherein the chip is a mixed signal element. ..........., can .........] (Please read the notes on the back before filling out this page) Intellectual Property of the Ministry of Economic Affairs The paper size printed by the Bureau's Consumer Cooperative is applicable to China National Standard (CNS) A4 (210X 297 mm)