TW533511B - Dual epitaxial layer for high voltage vertical conduction power MOSFET devices - Google Patents

Abstract

The epitaxial silicon junction receiving layer of a power semiconductor device is formed of upper and lower layers. The lower layer has a resistivity of more than that of the upper layer and a thickness of more than that of the upper layer. The total thickness of the two layers is less than that of a single epitaxial layer that would be used for the same blocking voltage. P-N junctions are formed in the upper layer to define a vertical conduction power MOSFET device. The on-resistance is reduced more than 10% without any blocking voltage reduce. The upper epitaxial layer can be either by direct second layer deposition or by ion implantation of a uniform epitaxial layer followed by a driving process.

Description

533511 V. Description of the invention (1) Field of the invention The field of invention of the present invention relates to a metal-oxide-semiconductor field-effect transistor semiconductor device (M 0 SFETS emic 〇nduct 〇r Devices), especially with a vertical conductive power The new structure and procedure of the metal oxide half field effect transistor device (vert i cal 丨 conduction power MOSFET device) is related to the program i, where the device has a reduced on-resistance.

I 丨 Background of the Invention

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I I The vertical conductive power metal-oxygen half-efficiency transistor device is a well-known device. This device has been proposed by other documents, such as the k-planar type 'cellular type i-type device in US Pat. No. 5,007,724, or a well-known parallel fringe pattern can be applied. (Parallel stripe topology) to manufacture the device, or the device can be manufactured using a trench-shaped design. | This device's on-resistance (RDSON) and stupid crystals

丨 (epitaxially) the resistivity of the silicon layer is large, and the measurement is related to 'where the stone layer receives the device's contacts, and this resistivity; and the degree of blocking voltage required by the last device Decide. Therefore, a higher I blocking voltage requires a higher resistance on the epitaxial layer, but this in turn results in an increase in the on-resistance of the device.

Therefore, there is a great need for a structure for a high-voltage device, and in particular, the blocking voltage of the clothing must be greater than about 100%.

533511 V. Description of the invention (2) Volt, which has a blocking voltage.丨 Summary of the invention I According to the present invention, the layer has a uniform resistance in Shi Xi | The depth of the I layer is sufficient; And the total thickness of |, this! 丨 adding I in the following can produce a reduction i! It has been known that | | on-resistance is about a hundred | voltage (breakdown |; Fig. 2 is the diagram, and "The electric field is the diagram, and Fig. 3 is the decrement of the electric current. The next day, there is less conduction," without having to sacrifice. From the top of the substrate (or gradient) the epitaxial contact receiving rate, this resistivity tapeworm crystal has a deep double-layer structure. The lower layer has all the equipment to receive: uniform resistivity on the upper layer. The upper and lower contacts, And about five s of the thickness of the lower layer has two epilayers which can reduce the number of two epilayers required. ♦ This will be clear. So 'for a given design specification, the On-resistance. The novel structure of the present invention can be reduced by more than 10% by the design of a device, and its exchange condition is not to reduce the breakdown voltage. ° The vertical field of a representative conventional technique that receives an epitaxial layer at a contact Sectional view of an effect transistor. The electric field of a single epitaxial layer is a function of the depth of the voltage blocking state. A cross-sectional view of a double epitaxial layer structure according to the present invention. 533511 V. Description of the invention (3) FIG. 4 is a view similar to FIG. 2 but has been modified according to the present invention. Fig. 5 shows a histogram, which is a comparison between a single-layer epitaxial structure and a double-layer epitaxial structure of the same high order in the present invention. Explanation of drawing number ~ 1 〇 substrate 1 1 crystal layer 1 2, 1 3 P-type base diffusion 1 4 source diffusion ring 1 6 gate oxide layer 1 7 gate electrode 1 8 interlayer oxide layer 1 9 aluminum source electrode 2 1 Lower crystalline layer 3 〇 Line 3 1 Detailed description of the preferred embodiment of the shaded area Now please refer to FIG. 1 ′ which shows a cross-sectional view of a substantially vertical conductive oxy half field effect transistor, which has a high height The conductive N + + matrix 1 0 has a single epitaxially deposited N-layer thereon. N-layer 1 1 Receives multiple contacts that need to be generated by the device, such as spaced P-type bases

Page 6 533511 V. Description of the invention (4) P type base diffusions l 2, 1 3, which contain N's source diffusion rings 1 4, 1 5 (used in cell formula Atlas). In the reversible channel region between the periphery of the source ring and the base diffusion region, the gate electrode layer 16 and the gate electrode of the conductive gate 22 are reproduced. electrode) 1 7. The gate electrode 17 is an interlayer oxide layer 18, and the top surface of the device is covered with an aluminum source electrode 19. -4 receive / and drain electrode 20 of the wafer or wafer. The structure of Fig. 1 is a basic structure in a variety of devices advantageous to the present invention; it will be described below. Therefore, the N-channel device can display one? Channel device (opposite all conductive types), and the garment can use a channel pattern instead of the flat pattern shown. When calculating the device shown in Figure 1, two key design parameters 1 'Ί ^: lock voltage and on-resistance. The blocking voltage of this device is a function of the resistance of the epitaxial layer = the resistance p. In particular, if 2 X is plotted under the curved green in the epitaxial layer 11 as shown in FIG. 2, it is shown that the blocking voltage is proportional to the area of the resistance undershirt of. The on-resistance of the device is proportional to the epitaxial layer blocking voltage ^ ^ the inverse of the straight line. It can be seen that if there is one less deployment; the slope of the curve must be reduced if added. Therefore, to take Γ τ ′ between to must take a compromise between a given blocking voltage or a given on-resistance. The invention allows the designer to change the shape of the area (seal # $ @ 1 ^ +, 4, 2). The way is (blocking the electricity house) can be increased (or maintained fixed), and all

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533511

V. Description of the invention (5) The depth of the epitaxial layer can be reduced, and the slope of the line can be maintained unchanged for multiple depths of the epitaxial layer. In particular, as shown in FIG. 3, the epitaxial layer 11 in FIG. 1 can be divided into an upper contact receiving layer and a lower epitaxial layer 2 1 for reducing resistance, and the resistance of the lower epitaxial layer is greater than that of the layer 20 Resistor, but with a thicker thickness. In the 600 volt device layer 20 shown in FIG. 3, basically the thickness I of the device is about 10 micrometers, and is greater than the depth of the base contacts 12,13. For high voltage devices, layer 21 is thicker than layer 20. Obviously different values can be used for different crash voltages. Generally, the resistance of the lower layer 21 is higher than the resistance of the layer 20.

I For a conventional 600 volt device, the epitaxial layer 1 of FIG. 11; 1 is substantially 2 1.50 hm-cm, and 57 μm thick. This results in a device with an on-resistance of about 0.68 ohms. According to the present invention, this device can be replaced by the I device of FIG. 3, where in the device of FIG. 3, the layer 20 is 20 μhm-cm (this value is used for a 25 volt device), and the layer 2 1 is 2 | 1.50hm-cm material (traditionally used in 600V installations). Layers I 20 and 21 have thicknesses of 7 and 48 microns, respectively. The effect of this two-layer structure is shown in Figure 4, where the structure has a

| Low resistance upper layer 2 0. The slope of the line 30 in FIG. 4 is the same as the line 1 in FIG. 2. However, the increase in the area under the curve of Fig. 4 by 2 is followed by the shaded area 3 1 caused by the larger slope of the segment 3 2. Therefore, in FIG. 4, the depth of the lower-resistance stupid crystal layer 20 of FIG. 3 is X: ′ and the region 2 0 ′ 2 1

'The total depth is reduced from the depth W (for the design shown in FIG. 1) to W 〇 As a result, the device of FIG. 3 has a breakdown voltage similar to that shown in FIG. 2.

Page 8 533511 V. Description of the invention (6) 丨 The area under the curve in Figure 4 is about the same as the area in Figure 2. However, the on-resistance is reduced due to the design of the stupid crystal layer, and the resistance in the first parasitic layer is also reduced. The comparison of these resistances is listed directly in Figure 4, which compares the total on-resistance of single and dual epitaxial layers. Figure 5 shows the equivalent breakdown voltage and on-resistance using single and dual epitaxial structures. Γ Although the present invention should be described in the preferred embodiments, those skilled in the art should understand that the above embodiments can be modified and changed without departing from the spirit and perspective of the present invention. Therefore, the present invention is not limited by the embodiment described above, but is limited by the scope of patent application below. 4

Page 9 533511 Simple illustration

Claims (1)

533511 VI. Application for patent scope 1. A semiconductor device includes: a silicon substrate, which is a combination of first and second surfaces, a first layer of epitaxial silicon formed above the first surface, and η or p conductive Type of impurities, which are uniformly distributed throughout the first: layer, a second layer of epitaxial silicon formed above the surface of the first layer, the epitaxial silicon and its coexistence, and the type of impurities is the same as The conductivity pattern of the first layer of impurities and the multiple diffusion regions are uniformly distributed throughout the volume! The conductivity pattern is opposite to that of the second layer, and the diffusion regions are evenly distributed on the surface of the second I layer. And a ρ-η contact is formed therein. I 2. The device according to item 1 of the scope of patent application, wherein the resistivity of the second layer is smaller than the resistivity of the first layer. I 3. The device according to item 1 of the scope of patent application, wherein the thickness of the first I layer is greater than the thickness of the second layer. I 4. The device according to item 2 of the scope of patent application, wherein the thickness of the first layer is greater than the thickness of the second layer. 5. The device according to item 1 of the scope of patent application, wherein the device has a given blocking voltage, and wherein the total thickness of the first and second layers is less than the thickness of the single layer of stupid crystals. Lies in blocking the given seal: lock voltage. ^ 6. The device according to item 2 of the scope of patent application, wherein the device has a given blocking voltage, and wherein the total thickness of the first and second layers is less than the thickness of the single layer of stupid crystals, this design It is to block the given blocking voltage. 7. The device according to item 3 of the scope of patent application, wherein the device has a given blocking voltage, and wherein the total thickness of the first and second layers Page 11 533511 6. The scope of patent application is smaller than the thickness of the single-layer epitaxial silicon. The design is to block the given blocking voltage. 8. The device as described in item 4 of the scope of patent application, wherein the device has a given blocking voltage, and wherein the total thickness of the first and second layers is less than the thickness of the single layer of stupid stone. It is to block the given blocking voltage. I 9. The device according to item 8 of the scope of patent application, wherein the device is a vertically conducting power metal-oxygen half field effect transistor. 1 0. A type of vertically conducting power metal-oxide half-field-effect transistor device, which has a reduced on-resistance, the device includes a silicon substrate, which is on the bottom surface; and a pole electrode, and There is a layer of stupid \ crystalline silicon on the upper surface of the substrate, which extends above it; from the free surface (fre I e surface) above the layer to the bottom, the device has a certain conductivity type I 丨 and its concentration is gradient The upper part of the layer extends from its free surface II, the surface is used to receive a PN contact, the contact is at least partially defined | the system's metal-oxygen half field effect transistor, and its average impurity concentration is greater than that of the layer The average impurity concentration at the bottom of S. The bottom of the layer accounts for more than 5 I 0% of the total thickness of the layer. : 1 1. The device as described in item 10 of the scope of the patent application, wherein the upper and lower portions of the lower: layer respectively include the first and second layers formed separately, which have individual uniform concentrations of i. 1 2. The device according to item 11 of the scope of patent application, wherein the device has a given blocking voltage, and wherein the total thickness of the first and second layers is smaller than the thickness of the single-layer epitaxial silicon, and Designed to block the given 533511 VI. Blocking voltage for patent application