TWI455190B - Trench power mosfet array and fabrication method thereof - Google Patents

Description

Ditch type power MOS half field effect transistor array and manufacturing method thereof

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a gold oxide half field effect transistor array and a method of fabricating the same.

In the conventional technology, the power metal-oxide-semiconductor field-effect transistor (MOSFET) has gradually replaced the traditional double-carrier transistor because of its low power consumption and fast switching rate. It is the most commonly used semiconductor component in integrated circuits. The trench-type power MOS half-field effect transistor is one of the structures of the gold-oxygen half-field effect transistor, and the trench-type design can make the size of the component smaller.

When designing the above array of MOS field-effect transistors, the withstand voltage and on-resistance characteristics are mainly considered. But because these two features are conflicting, a new design is needed to improve both features.

Therefore, one aspect of the present invention provides a trench-type power MOS field-effect transistor array and a manufacturing method thereof, which can increase the breakdown voltage of a trench-type power MOS field-effect transistor and simultaneously reduce the conduction per unit area. resistance.

According to an embodiment of the invention, the method for fabricating the trench-type power MOS field-effect transistor array comprises the following steps. A germanium epitaxial layer is formed on the germanium substrate. A spaced field trench is formed in the germanium epitaxial layer. A conformal field dielectric layer and a first polysilicon layer are sequentially formed on the inner surface of the field trench, and the first polysilicon layer is used as a field plate. A gate trench is formed in the epitaxial layer between adjacent trenches, wherein the vertical depth of the gate trench is smaller than the field trench. A conformal gate dielectric layer and a second polysilicon layer are sequentially formed on the inner surface of the gate trench, wherein the second polysilicon layer serves as a gate. A first implantation step is performed to form a base region in the tantalum epitaxial layer, and the base region is electrically opposite to the tantalum epitaxial layer, and the tantalum epitaxial layer and the tantalum substrate under the base region are used as the drain. A second implantation step is performed to form a plurality of sources on both sides of the gate trench in the substrate region. The thickness of the field dielectric layer may be, for example, 4000-10000 . The thickness of the gate dielectric layer can be, for example, 100-1000 .

According to another embodiment of the present invention, the structure of the trench type power MOS field effect transistor comprises a germanium substrate, a germanium epitaxial layer, a base region, a field trench in the germanium epitaxial layer, and an inner surface of the field trench Field dielectric layers and field plates, as well as trench-type power MOS transistors. The trench-type power MOS transistor includes a gate dielectric layer and a gate located in the gate trench, and a source and a drain. Wherein, the vertical depth of the gate trench is smaller than the trench of the field.

The Summary of the Invention is intended to provide a simplified summary of the present disclosure in order to provide a basic understanding of the disclosure. This Summary is not an extensive overview of the disclosure, and is not intended to be an The basic spirit and other objects of the present invention, as well as the technical means and implementations of the present invention, will be readily apparent to those skilled in the art of the invention.

According to the above, a trench type power MOS field effect transistor array and a manufacturing method thereof are provided, which can increase the breakdown voltage of the trench type power MOS field effect transistor and simultaneously reduce the on-resistance per unit area. In the following description, an exemplary manufacturing method of the above-described trench type power MOS field-effect transistor array and an exemplary structure thereof will be described. In order to facilitate an understanding of the described embodiments, a number of technical details are provided below. Of course, not all embodiments require these technical details. At the same time, some well-known structures or elements are only shown in the drawings in a schematic manner to appropriately simplify the contents of the drawings.

Referring to Fig. 1, this is a schematic cross-sectional structure of a general trench type power MOS field effect transistor. An n-type germanium epitaxial layer 110 is generally disposed on the n-type germanium substrate 100, wherein the n-type germanium substrate 100 and the n-type germanium epitaxial layer 110 serve as the drain 120. A gate 130, a p-type base region 140, a source 150, and a p-type contact doping region 160 are disposed in the germanium epitaxial layer.

In general, if the doping concentration of the n-type germanium epitaxial layer 110 is lower, the breakdown voltage of the trench-type power MOS field-effect transistor is higher, but the on-resistance is higher, causing a dilemma. .

Therefore, according to an embodiment of the present invention, the field plate structure is disposed at the position of the p-type contact doping region 160, which can improve the profile of the depletion region of the germanium epitaxial layer and increase the breakdown voltage of the trench-type power MOS field-effect transistor. . Therefore, the doping concentration of the n-type germanium epitaxial layer 110 can be increased, and the on-resistance per unit area of the trench-type power metal oxide half field effect transistor array can be reduced.

Method for manufacturing trench type power MOS half field effect transistor array

Please refer to FIG. 2A-2G, which is a cross-sectional structural diagram of a manufacturing process of a trench type power MOS field effect transistor according to an embodiment of the invention.

In FIG. 2A, a germanium epitaxial layer 210 is formed on the tantalum substrate 200. In FIG. 2B, spaced field trenches 220 may be formed in the germanium epitaxial layer 210 using photolithographic etching. Next, a conformal field dielectric layer 222 and a first polysilicon layer 224 are sequentially formed on the inner surface of the field trench 220. The method of forming the field dielectric layer 222 may be, for example, a thermal oxidation method, and the method of forming the first polysilicon layer 224 may be, for example, a chemical vapor deposition (Chemical Vapor Deposition) method.

In FIG. 2C, the excess first polysilicon layer 224 and the field dielectric layer 222 are removed from the germanium epitaxial layer 210, leaving the first germanium layer 224 and field dielectric in the field trench 220. Layer 222 and exposed germanium epitaxial layer 210. The first polysilicon layer 224 is used as the field plate 224a, and the field dielectric layer 222 is 4,000-10000. between. The method of removing the first polysilicon layer 224 and the field dielectric layer 222 may be, for example, a dry etching method.

In FIG. 2D, a gate trench 230 may be formed in the germanium epitaxial layer 210 between adjacent field trenches 220 by means of photolithography. Next, a conformal gate dielectric layer 232 and a second polysilicon layer 234 are sequentially formed on the inner surface of the gate trench 230. The method of forming the gate dielectric layer 232 may be, for example, a thermal oxidation method, and the method of forming the second polysilicon layer 234 may be, for example, a chemical vapor deposition method. The vertical depth of the gate trench 230 is less than the vertical depth of the field trench 220.

In FIG. 2E, the excess second germanium layer 234 and the gate dielectric layer 232 on the germanium epitaxial layer 210 are removed, leaving a second germanium layer 234 and gate dielectric in the gate trench 230. Layer 232 and exposed germanium epitaxial layer 210. The second polysilicon layer 234 is used as the gate 234a, and the gate dielectric layer 232 is 100-1000 thick. between. The method of removing the second polysilicon layer 234 and the gate dielectric layer 232 may be, for example, a dry etching method.

In FIG. 2F, a comprehensive first implantation step is performed to form the base region 240 in the tantalum epitaxial layer 210. Next, a regional second implantation step is performed to form source 250 on both sides of gate trench 230 in substrate region 240. The electrical conductivity of the base region 240 is opposite to that of the germanium epitaxial layer 210. In addition, the germanium epitaxial layer 210 and the germanium substrate 200 located under the substrate region 240 can serve as the drain 212.

The method for manufacturing the above-described trench-type power MOS field-effect transistor array may further include the following steps, please refer to FIG. 2G. First, a dielectric layer 260 and a contact window 262 are sequentially formed on the germanium epitaxial layer 210. Next, a contact doping region 264 is formed in the base region 240. Then, a conductive layer 270 and a protective layer 280 are sequentially formed on the dielectric layer 260 and the contact window 262. Finally, a back metal layer 290 is formed under the tantalum substrate 200. The above steps will be separately explained below.

Referring to FIG. 2G, first, a dielectric layer 260 is formed on the germanium epitaxial layer 210 in the structure of FIG. 2F. Next, a lithography etching step is performed to form a contact window 262 in the dielectric layer 260 to expose the field plate 224a and the source 250. Next, a regional third implantation step is performed to form contact doping regions 264 in the exposed substrate region 240 between the field plate 224a and the source 250, respectively. The contact doping region 264 is electrically identical to the substrate region 240 and has a higher doping concentration. A conductive layer 270 is then formed on the dielectric layer 260 and in the contact window 262 to electrically contact the field plate 224a, the contact doping region 264, and the source 250.

Next, a protective layer 280 is formed on the conductive layer 270 to protect the underlying trench power MOS field effect transistor array. The material of the sheath may be, for example, phosphor bismuth glass, borophosphoquinone glass or tantalum nitride. Finally, a back metal layer 290 is formed under the tantalum substrate 200.

Ditch-type power MOS half-field effect transistor array

Referring to FIG. 2F, a cross-sectional structural diagram of a trench-type power MOS field effect transistor array according to an embodiment of the present invention is shown. The structure of the trench type power MOS field-effect transistor array comprises a germanium substrate 200, a germanium epitaxial layer 210, a base region 240, a field trench 220, a field dielectric layer 222, and a trench power MOS transistor.

A germanium epitaxial layer 210 is disposed on the germanium substrate 200, and a base region is disposed in the germanium epitaxial layer 210. The electrical conductivity of the base region 240 is opposite to that of the tantalum substrate 200 and the tantalum epitaxial layer 210. For example, the dopant of the base region 240 may be, for example, a p-type, and the dopant of the tantalum substrate 200 and the tantalum epitaxial layer 210 may be, for example, an n-type.

A spaced field trench 220 is disposed in the germanium epitaxial layer 210. A conformal field dielectric layer 222 is disposed on the inner surface of the field trench 220 for electrically isolating the field plate 224a from the germanium epitaxial layer 210. A field plate 224a is disposed on the field dielectric layer 222, wherein the material of the field plate 224a may include a polysilicon.

A trench type power MOS transistor is disposed in the germanium epitaxial layer 210 and the germanium substrate 200 between adjacent field plates 224a. The trench-type power MOS transistor includes a gate dielectric layer 232 and a gate 234a, and a source 250 and a drain 212 in the gate trench 230.

A gate dielectric layer 232 is disposed on the inner surface of the gate trench 230. The gate trench 230 is located in the germanium epitaxial layer 210 between the adjacent field plates 224a, and the vertical depth of the gate trench 230 is smaller than the field trench 220. The gate dielectric layer 232 is used to electrically isolate the gate 234a from the germanium epitaxial layer 210. A gate 234a is disposed on the gate dielectric layer 232, a source 250 is disposed in a base region on both sides of the gate trench 230, and a drain 212 is disposed in the germanium epitaxial layer 210 and the germanium substrate 200 under the base region 240.

The trench-type power MOS field-effect transistor array may further include a dielectric layer 260, a conductive layer 270, and a cap layer 280 on the germanium epitaxial layer 210. Referring to FIG. 2G, first, a dielectric layer 260 is disposed on the gate 234a. The dielectric layer 260 has a contact window 262 for exposing the field plate 224a and the source 250. Further, a conductive layer 270 is disposed on the dielectric layer 260 and in the contact window 262. Next, a protective layer 280 is provided on the conductive layer 270. The trench type power MOS field effect crystal structure described above may also be provided with a back metal layer 290 under the ruthenium substrate 200.

In summary, the field plate structure can improve the profile of the depletion region of the bismuth epitaxial layer, change the electric field distribution, and increase the breakdown voltage of the trench-type power MOS field effect transistor. Moreover, the doping concentration of the germanium epitaxial layer can be increased due to the increase of the breakdown voltage of the trench-type power MOS field-effect transistor, so as to reduce the on-resistance per unit area of the trench-type power MOS field-effect transistor.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

100. . . N-type germanium substrate

110. . . N-type germanium epitaxial layer

120. . . Bungee

130. . . Gate

140. . . P-type basal region

150. . . Source

160. . . P-type contact doping region

200. . . Bismuth substrate

210. . .矽 晶 layer

212. . . Bungee

220. . . Field ditch

222. . . Field dielectric layer

224. . . First polycrystalline layer

224a. . . Field board

230. . . Gate ditch

232. . . Gate dielectric layer

234. . . Second polycrystalline layer

234a. . . Gate

240. . . Base area

250. . . Source

260. . . Dielectric layer

262. . . Contact window

264. . . Contact doping region

270. . . Conductive layer

280. . . Cover

290. . . Back metal layer

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood.

Figure 1 is a schematic cross-sectional view showing a general trench type power MOS field effect transistor.

2A-2G is a cross-sectional structural diagram showing a manufacturing process of a trench type power MOS field effect transistor according to an embodiment of the present invention.

200. . . Bismuth substrate

210. . .矽 晶 layer

212. . . Bungee

222. . . Field dielectric layer

224. . . First polycrystalline layer

224a. . . Field board

232. . . Gate dielectric layer

234. . . Second polycrystalline layer

234a. . . Gate

240. . . Base area

250. . . Source

Claims (8)

A method for manufacturing a trench-type gold-oxygen half-field effect transistor array, comprising the steps of: forming a germanium epitaxial layer on a germanium substrate; forming a plurality of field trenches in the germanium epitaxial layer; forming a total Forming a field dielectric layer and a first polysilicon layer on the inner surface of the field trenches, wherein the first polysilicon layer is used as a field plate; forming a plurality of gate trenches adjacent to the field trenches In the epitaxial layer, the vertical depth of the gate trenches is smaller than the field trenches; a conformal gate dielectric layer and a second polysilicon layer are sequentially formed on the inner surfaces of the gate trenches The second polysilicon layer is used as a gate; a first implantation step is performed to form a base region in the germanium epitaxial layer, the base region being electrically opposite to the germanium epitaxial layer, and The germanium epitaxial layer under the substrate region and the germanium substrate are used as a drain; a second implantation step is performed to form a plurality of sources on opposite sides of the gate trenches in the base region; An electrical layer is on the germanium epitaxial layer; a plurality of contact windows are formed in the dielectric layer to expose the field plates And performing a third implantation step to form a plurality of contact doping regions respectively in the substrate region between each of the exposed field plates and each of the plurality of sources, the contact doping The region is electrically identical to the substrate region; forming a conductive layer on the dielectric layer and the contact windows; A protective layer is formed on the conductive layer. The manufacturing method of claim 1, wherein the field dielectric layer has a thickness of 4000 to 10000 Å. The manufacturing method of claim 1, wherein the gate dielectric layer has a thickness of 100-1000 Å. The manufacturing method of claim 1, further comprising forming a back metal layer under the crucible substrate. A trench-type power MOS field-effect transistor array comprising: a germanium epitaxial layer on a germanium substrate; a base region in the germanium epitaxial layer, the electrical properties of the base region and the germanium The crystal layer is opposite; a plurality of field trenches are located in the epitaxial layer; the conformal plurality of field dielectric layers are respectively located on inner surfaces of the field trenches; and a plurality of field plates are respectively located in the fields a plurality of trench-type power MOS transistors in the trenches, and the germanium epitaxial layer between the adjacent field plates and the germanium substrate, wherein each of the trenches Power MOS semi-transistor contains: a gate dielectric layer is disposed on an inner surface of the gate trench, the gate trench is located in the germanium epitaxial layer between the adjacent field plates, and the vertical depth of the gate trenches is smaller than the field trenches; a gate electrode located on the gate dielectric layer and filling the gate trench; a source located in the base region on both sides of the gate trench; and a drain, the germanium epitaxial layer under the base region and And the plurality of contact doping regions are located in the substrate region between each of the field plates and each of the plurality of sources, and the contact doping regions are electrically identical to the substrate region. The transistor array of claim 5, wherein the material of the field plate comprises a germanium. The transistor array of claim 5, further comprising: a dielectric layer on the gate, the dielectric layer having a plurality of contact windows to expose the field plates and the source; a conductive layer Located on the dielectric layer and the contact windows; and a protective layer on the conductive layer. The transistor array of claim 5 further comprising a back metal layer underlying the germanium substrate.