JPH0362969A - High withstand-voltage lateral field effect transistor - Google Patents

Abstract

PURPOSE:To increase the radius of curvature of a depletion layer at a source side and improve withstand-voltage characteristics by setting the thickness of a semiconductor layer and concentration of impurities so that the depletion layer at the source side comes into contact with that at the substrate side when voltage is applied between the source and drain. CONSTITUTION:An N<-> type diffusion layer 2 is formed on a P-type silicon substrate 1 with such impurities concentration and depth as the depletion layers 13 at the source and substrate sides come into contact each other. After that, a gate polysilicon layer 7 is formed through a gate insulation film, a P-type base layer 3 is formed, and then N<+> type diffusion layers 4 and 6 and a P<+> type diffusion layer 5 are formed. After that, a silicon oxide film 8 is allowed to grow, a contact hole is formed, and an external gate electrode 9, a source electrode 10, and a drain electrode 11 consisting of aluminum are formed. Then, by grounding the external gate electrode 9, the source electrode 10, and the P-type semiconductor substrate 1 and by applying plus voltage to the drain, the depletion layers 13 at the source and substrate sides come into contact, thus increasing the radius of curvature of depletion layer being extended from the source to the drain and withstand voltage.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applied to a high voltage lateral field effect transistor,
In particular, DSA (Diffusion 5elfe)
The present invention relates to a high voltage lateral field effect transistor having an aluminum ignment structure.

〔overview〕

The present invention provides a high breakdown voltage lateral field effect transistor in which a semiconductor layer of an opposite conductivity type is formed on a semiconductor substrate of one conductivity type, and a field effect transistor having a DSA structure is formed on the upper surface of this semiconductor layer. By setting the thickness and impurity concentration of the semiconductor layer so that the depletion layer on the source side and the depletion layer on the substrate side come into contact when a voltage is applied, the radius of curvature of the depletion layer on the source side is increased. , which has improved voltage resistance characteristics.

[Conventional technology]

Conventionally, the structure of a lateral field effect transistor having a DSA structure, as shown in FIG. After forming at a high concentration, DSA
A lateral field effect transistor having a structure was formed.

FIG. 3 shows the case of an N-channel type, where 1 is a P-type semiconductor substrate, 2 is an N-type diffusion layer, 3 is a P-type base layer, 4 and 6
is an N-type scattered layer 5, a P°-type scattered layer 7 is a gate polysilicon layer, 8 is a silicon oxide film, 9 is an external gate electrode,
10 is a source electrode and 11 is a drain electrode.

As shown in the figure, when the external gate electrode 9, the source electrode 10, and the P-type semiconductor substrate 1 are set to the ground potential and ten voltages are applied to the drain electrode 11, the P-type semiconductor substrate 1 and the N-type diffusion layer 2 are connected to each other. A depletion layer 13a is formed between N-
A depletion layer 13b is formed between the type diffusion layer 2 and the P type base layer 3. At this time, depletion layers 13a and 13b are not in contact with each other.

[Problems to be Solved by the Invention] The above-described conventional high-voltage lateral field effect transistor having the DSA structure has a drawback that the radius of curvature of the depletion layer extending from the source side to the drain side is small, resulting in a low breakdown voltage.

As a countermeasure to this problem, it is possible to increase the radius of curvature of the depletion layer extending from the source side to the drain side by deepening the base layer, increasing the breakdown voltage. However, deepening the base layer increases the channel length. , has the disadvantage of high on-resistance.

An object of the present invention is to provide a high breakdown voltage lateral field effect transistor that can increase the breakdown voltage by increasing the radius of curvature of the source side depletion layer without increasing the channel length by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention includes a semiconductor substrate of one conductivity type, a first semiconductor layer of an opposite conductivity type formed on the semiconductor substrate, and an opposite conductivity type formed at a predetermined position on the upper surface of the first semiconductor layer. a high breakdown voltage lateral field effect transistor comprising a base layer of one conductivity type including a source region of the same type, and a drain region of the opposite conductivity type formed on the upper surface of the first semiconductor layer with the source region and the gate electrode sandwiched therebetween; In this case, the impurity concentration and the thickness of the first semiconductor layer are such that when a voltage is applied between the source and drain, the depletion layer formed between the semiconductor substrate and the first semiconductor layer and the The base layer and the depletion layer formed between the first semiconductor layer are set to be in contact with each other.

[Effect]

The first semiconductor layer of the opposite conductivity type formed on the semiconductor substrate of one conductivity type is made shallow and has a low impurity concentration so that the depletion layers on the source side and the substrate side are in contact with each other. Therefore, the depletion layer extending from the source to the drain side is expanded toward the substrate, and its radius of curvature becomes large.

Therefore, it is possible to increase the breakdown voltage without increasing the on-resistance by increasing the channel length.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic vertical sectional view showing the structure of a first embodiment of the present invention, and also shows bias connections.

The present embodiment includes a P-type semiconductor substrate 1, an N-type diffusion layer 2 as a first semiconductor layer of an opposite conductivity type formed on this semiconductor substrate 1, and this N''' type expanded layer. A P-type base layer 3 including an N+-type scattering layer 4 which becomes a source region of the conductivity type and a P+-type diffused layer 5 which becomes a long blocking region on the scattering layer 2, and an internal gate of the N+-type scattering layer 4. In a high-voltage lateral field effect transistor comprising an N-type resistive diffusion layer 6 which serves as a drain region of the opposite conductivity type and is formed on the upper surface of an N-type diffusion layer 2 with a gate polysilicon layer 7 serving as an electrode in between, the present invention The impurity concentration and thickness of the N-type diffusion layer 2, which is a feature of the invention, are such that when a voltage is applied between the source and drain, the impurity concentration and the thickness of the N-type diffusion layer 2 are such that the impurity concentration and the thickness of the N-type diffusion layer 2 are such that when a voltage is applied between the source and drain, The depletion layer formed between the P-type base layer 3 and the N-type diffusion layer 2 contacts and forms a common depletion layer 13.
is set so that it is formed.

This embodiment can be manufactured as follows.

First, an N- type diffusion layer 2 is formed on a P-type silicon substrate 1 with an impurity concentration and depth such that the depletion layer 13 on the source side and the substrate side are in contact with each other. Thereafter, a gate polysilicon layer 7 is formed via a gate insulating film, a P-type base layer 3 is formed, and further N-type scattering layers 4 and 6 and a P-type scattering layer 5 are formed.
form.

Thereafter, the silicon oxide film 8 is lengthened to form a contact hole, and an external gate electrode 9 made of aluminum is formed.
A source electrode IO and a drain electrode 11 are formed.

For this embodiment manufactured as described above,
As shown in the figure, by grounding the external gate electrode 9, the source electrode 10, and the P-type semiconductor substrate 1, and applying ten voltages to the drain, the depletion layers 13 on the source side and the substrate side come into contact, and the depletion layer 13 on the source side and the substrate side The radius of curvature of the depletion layer that extends over the area increases, and the withstand voltage increases.

FIG. 2 is a schematic vertical sectional view showing a second embodiment of the present invention,
Bias connections are also shown. In the second embodiment, an N-type epitaxial layer 12 is grown in place of the N-type diffusion layer 2 of the first embodiment shown in FIG. Since it is more uniform, it has the advantage that the withstand voltage can be further increased.

〔Effect of the invention〕

As explained above, the present invention provides a high breakdown voltage lateral field effect transistor having a DSA structure by forming a semiconductor layer of an opposite conductivity type on a semiconductor substrate of one conductivity type to be shallow and having a low concentration on the source side. By bringing the depletion layer on the substrate side into contact with the depletion layer, the radius of curvature of the depletion layer extending from the source to the drain side can be increased, which has the effect of increasing the breakdown voltage.

4,

[Brief explanation of drawings]

FIG. 1 is a schematic vertical sectional view showing a first embodiment of the present invention. FIG. 2 is a schematic vertical sectional view showing a second embodiment of the present invention. FIG. 3 is a schematic longitudinal sectional view showing a conventional example. DESCRIPTION OF SYMBOLS 1... P type semiconductor substrate, 2... N- type diffusion layer, 3...
...P-type base layer, 4.6...N'-type scattering layer 5...
・P′ type scattering layer 7...gate polysilicon layer, 8・
・Silicon oxide film, 9 ・External gate electrode, IO・
...Source electrode, 11...Drain electrode, 12...
N-type epitaxial layer, 13.13a, 13b
...Depletion layer.

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, a first semiconductor layer of an opposite conductivity type formed on this semiconductor substrate, and a semiconductor layer formed at a predetermined position on the upper surface of this first semiconductor layer. A high breakdown voltage comprising a base layer of one conductivity type including a source region of an opposite conductivity type therein, and a drain region of an opposite conductivity type formed on the upper surface of the first semiconductor layer with the source region and the gate electrode sandwiched therebetween. In the lateral field effect transistor, the impurity concentration and the thickness of the first semiconductor layer are such that when a voltage is applied between the source and drain, the impurity concentration is set between the semiconductor substrate and the first semiconductor layer. A high breakdown voltage lateral field effect transistor, wherein a depletion layer is set to be in contact with a depletion layer formed between the base layer and the first semiconductor layer.