RU205193U1 - DMOS transistor with increased threshold voltage - Google Patents

Abstract

The utility model relates to the field of electronic engineering, namely to a double diffusion metal-oxide-semiconductor (DMOS) transistor, and can be used both as a discrete device and as an element in the creation of integrated circuits for various purposes. The basis is the task of improving the DMOS transistor in order to increase its noise immunity. When operating in the key mode, it is often required that the transistor does not operate up to a certain value of the gate voltage, for example, in the presence of interference. The result can be achieved by raising the threshold voltage of the transistor. In the DMOS in an n-channel transistor containing a P + deep layer, P type active regions, N + type source regions, gate oxide and polysilicon gate, using p-type polycrystalline silicon films as a gate instead of the traditional n-type polycrystalline silicon allows you to get higher values of the threshold voltage, while there is no increase in the resistance of the transistor channel. Such DMOS transistors can be used in logic key circuits when it is necessary to counteract triggering from the influence of false interference.

Description

The utility model relates to the field of electronic engineering, namely to a DMOS transistor with double diffusion, and can be used both as a discrete device and as an element in the creation of integrated circuits for various purposes.

A known DMOS transistor, including an n + type layer, an n-type epitaxial layer on a silicon substrate, a gate oxide, a polycrystalline silicon layer, a p-type transistor base, an n-drift region, n + source regions, metal contacts to the gate, to the base, to the drain and source areas (RU No. 127514, IPC H01L 29/00, 04/27/2013).

One of the disadvantages of such a transistor is a low threshold voltage in the case of using phosphorus for doping the polysilicon gate, which leads to a decrease in the noise immunity of the transistor.

The task of the utility model is to increase the threshold voltage of the transistor and increase its noise immunity.

The technical result is an increase in the threshold voltage of the transistor and an increase in its noise immunity

The technical result is achieved by the fact that in a DMOS transistor, including an N-type epitaxial layer on a silicon N + substrate, P type active regions, N + type source regions, gate oxide, polysilicon gate, metal contacts to all transistor regions, films are used as a gate polycrystalline silicon p-type conductivity.

If the polysilicon gate is doped with boron, then a change in the energy diagram will lead to an increase in the work function of the polysilicon gate, which will increase the threshold voltage of the transistor and improve its noise immunity.

FIG. 1 shows a cross-section of the elementary cell of the proposed DMOS transistor, where:

1 - aluminum,

2 - interlayer insulation,

3 - polysilicon gate,

4 - gate dielectric.

An example of using the utility model.

Were manufactured DMOS transistors, the structure of which is shown in figure 1.

The transistors were formed on epitaxial nn ⁺ silicon structures, with a resistivity of the epitaxial film of 6 - 8 Ohm cm. To carry out a comparative analysis, transistors were manufactured with doping of the polysilicon gate with various impurities.

The p-type pocket was formed by ion implantation of boron with a dose of 10-15 µC / cm ² , followed by distillation to a depth of about 4.0 µm. The n ⁺ pockets formed by the diffusion of phosphorus to a depth of 0.6 μm served as the source of the transistor. Diffusion of phosphorus was carried out in the same windows as ion doping of boron (p-pocket), this made it possible to carry out the operation of self-alignment of the transistor channel.

To reduce the influence of a vertical parasitic bipolar n ⁺ -pn ^- -n ⁺ -transistor, boron was diffused into the center of the transistor cells to a depth of about 2.0 μm (p ⁺ pocket). _{A combination of SiO 2} -Si ₃ N ₄ films with a total thickness of about 0.15 μm was used as the gate dielectric of the transistor. A film of polycrystalline silicon, about 0.5 µm thick, acting as a gate, was deposited over the gate dielectric by the decomposition of monosilane. To reduce the gate resistance, an impurity was diffused into the polycrystalline silicon film. In this case, in the first group of transistors, polysilicon was doped at a temperature of 870 ° C with phosphorus, and in the second - with boron.

The configuration of the polysilicon gate in the central part of the crystal between the transistor cells was formed by photolithography, followed by the removal of polysilicon in the CF ₄ plasma in unnecessary regions. The insulation between the source electrodes and the polysilicon gate was carried out by sequential deposition of dielectric films Si ₃ N ₄ -SiO ₂ -Si ₃ N ₄ , followed by etching the contact windows to the transistor cells and the polysilicon gate. Further, on top of the formed insulator, an aluminum film with a thickness of 1-1.4 μm was deposited by a vacuum-thermal method, followed by the formation of the source electrodes (uniting all transistor cells) and the gate. For contact to the drain, a Ti-Ni-Au metallization system was deposited on the reverse side of the plate, and galvanic gold 3-4 µm thick was deposited.

Upon completion of the technological cycle, the electrical characteristics of the transistors were measured on an L2-56 semiconductor device parameter meter. The controlled parameters were: voltage of the avalanche breakdown of transistors in the mode: Uz = 0 V, Ic = 10 μA; drain current of transistors in the mode: Uzi = 3.5 V, Usi = 0.5 V; and the threshold voltage of transistors in the mode: Uzi = Usi; Iс = 1.0 mA.

Table 1 shows the results of measurements of the electrical parameters of transistors with different types of conductivity of the polysilicon gate. It can be seen that when the polysilicon gate was doped with boron, instead of phosphorus, the threshold voltage of the transistors increased from 1.1-1.2 V to 1.4-1.5 V. At the same time, no drop in the drain current of the transistors was observed in the given mode.

Thus, the use of p-type polycrystalline silicon films as a gate in n-channel transistors makes it possible to obtain higher threshold voltages. The use of n-channel DMOS transistors with p-type polysilicon gates in logic key circuits can be recommended to increase their noise immunity.

Table 1

Iс, mA
(Usi = 0.5 V;
Uzi = 3.5 V) Usi samples, V
(Uzi = 0 V,
Ic = 10 μA) Uzi pore, V
(Usi = Usi;
Iс = 1 mA) Transistors with
n ⁺ polysilicon shutter 105 - 115 260 - 275 1.1 - 1.2 Transistors with
p ⁺ -polysilicon shutter 105 - 115 260 - 275 1.4 - 1.5

Claims (1)

DMOS transistor, including an N- type epitaxial layer on an N + silicon substrate, P type active regions, N + type source regions, gate oxide, polysilicon gate, metal contacts to all transistor regions, characterized in that polycrystalline silicon films p are used as the gate -type of conductivity.

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