TW529135B - Semiconductor device and fabrication process thereof - Google Patents

Semiconductor device and fabrication process thereof Download PDF

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Publication number
TW529135B
TW529135B TW088121525A TW88121525A TW529135B TW 529135 B TW529135 B TW 529135B TW 088121525 A TW088121525 A TW 088121525A TW 88121525 A TW88121525 A TW 88121525A TW 529135 B TW529135 B TW 529135B
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Taiwan
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substrate
semiconductor device
semiconductor
semiconductor wafer
manufacturing
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TW088121525A
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Chinese (zh)
Inventor
Ryoji Sato
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Nec Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A fabrication process is adapted for fabricating a semiconductor device having a substrate in a form of a film holding a semiconductor chip having an electrode on one side thereof, a though opening formed through the substrate at a position corresponding to the semiconductor chip, a conductor formed within the through opening by a plated layer and connected to the electrode of the semiconductor chip, and the through opening having a first opening portion on the semiconductor chip side whose width is smaller than that of a second opening portion on the other side. The process comprises the steps of forming a through opening through a substrate after holding a semiconductor chip on one surface of the substrate as a film, and forming a conductor formed of a plating layer within the through opening to connect the conductor to an electrode of the semiconductor chip.

Description

529135529135

〔發明背景〕 〔發明領域〕 法。尤其, 合用於高封 本發明係關於一 本發明關於一種半導 裝密度之安裝。 種半導體裝置及其製造 體裝置及其製造方法, 〔相關技術之說明〕 半導體封裝之新形態業已接二連三發展, 子=備之較高性能、較小尺寸、較輕重量、以 之需求、。舉例而言,藉由半導體裝置尺寸降低 減少,達成半導體晶片之較高封裝密度,則較 輕重量之電子設備可達成。 為了實現半導體晶片之較高封裝密度,半 之f針數目已增加。隨著半導體晶片中插針之 體晶片與導線架間之連接時常採用無配線接合 線接合系統係一接合系統,用以使半導體晶片 墊以重疊方式連接至配線導線架或外界電極, 線’亦稱為集團接合(gang bonding)。卷帶自 (tape automated bonding,TAB)系統係作為一 接合系統。 在T A B系統中,複數條配線之形成係,藉廷 式,使重複形成於一基板上成卷帶狀形態之導 疊於對應於半導體晶片電極之部分。其間,在 晶片之電極接合墊以及基板内部導線架之對應 用以滿足電 及較高速度 以及厚度之 小尺寸與較 導體晶片中 增加,半導 系統。無配 之電極接合 以作為配 動接合 -種無配線 ί適當方 體導線架重 重疊半導體 部分之後, 529135 五、發明說明(2) 藉由熱壓縮接合或埶超音 其被稱為内部導線架;:波:=合使重疊部分相連接, 已揭露於日本未實審專二f例而5,内部導線架接合業 圖9A至9H顯示習知的::平成第8_1 02466號中。 體裝置之製造方法^ 耵述内部導線架接合之半導 首先’如圖9A中所示,在半導 一由聚醯亞胺有機類絕綾胺^牛=體凌置之製造中,使用 數十//m之範圍内。、一牌部、1 、之基板72,其厚度位於 之—主要表面上。另一;;面(aiheSiVe)73塗覆於基板72 電材料例如Cu或諸如此類者’:板公中形成貫通孔71。導 741。美柘7?夕去命帝 '者’填入貝通孔71,以形成導體 土板72之未塗覆膠黏劑73之 其接觸於導體741。|诵^ 71 + y 办成配線74, 者所構成之鍍製物(Plating)7/_如銅、至或諸如此類 :::如圖9B中所示,在精確的定位條件中,基 秒m導體晶片1上。隨後’藉由持續加熱且施壓若干 ‘導二f H2與半導體晶片1互相接合。電極接合墊1 〇沿著 ^體曰曰片1之外周緣部分設置。然而,電極接合墊 用己置於主動區域中。-金屬’典型地為銘型合金,得 邪為用以形成電極接合墊丨〇之材料。 件 人隨後,如圖9C中所示,進行内部導線架接合,藉 ς =具76以熱超音波配線接合之方式,連接基板?2^半 ,曰曰^ 1。在此例子中,既然在熱壓縮配線接合中需 ^ 貝上尚溫條件,故使用熱超音波配線接合。藉此接合,貝/ 口 ’形 529135 五、發明說明(3) ' --- 曰曰片1之電極接合墊10之鋁與形成基板72之銅被 鑄成合金。因此,可強化連接部分。 繼之,如圖q D由& 一 1之表面的相對表面上V/基板72之接合… ,, 矛面上,形成一具有預定的圖案之銲錫球 全卞。隨後,如圖9Ε中所示,銅或銅+ 之π刀(在後績製程步驟中用以設置外界電極之部分)上。 此,2圖9F中所示,對於鍍製物78在後續製程 =處::成銲錫突塊79,作為外界電極。隨後,“ 不在刀剎外圍輪廓(未圖示)之後,由玻璃環氧# :或ΪΓ;ΐ:形成之印刷板710,與焊錫突㈣相接 。。最後,為了確保印刷板71 〇與銲錫突塊79間之連 ^強化樹注人印刷板71G與基板72間,藉由加 β又定。經由岫述製造方法,製成半導體裝置。 ’、’、 另-方,,半導體裝置之習知的製造方法之另 係,日本未貫審專利公報平成第1〇 —15〇116號中揭露之羽 知的半導體裝置之製造方法,顯示於圖⑽至刚 白 在圖1 Ο Α至丨Ο Η所顯示之半導體裝置之習知的製造方:使 如圖10Α所示,半導體裝置之製造中仍使用聚醢亞胺中’ 絕緣基板8 2,類似於圖9 Α至9 Η中所示之製造方法。十 10Α至10Η所示之半導體裝置之習知的製造方法中,—^ 84丨沉積於基板W之一主要表面上。藉由餘刻移除沉—鋼^ 基板82上之銅泊之不必要部分,以形成如 f 、 配線84。 τ岍不之 529135 五、發明說明(4) lase〇'^A^〇82l^ ? # t t ^(carbon gas Γ面开成=甬=,成配線84之表面之相對邊的 表面形成貝通口 81。此時,由於貫 ^ ^ ^ 可能造成殘留樹脂83之不完全移81中之軋泡殘遠, 示,移除此等殘留樹脂83。移除。因而,如圖1〇D中所 —繼之,如圖10E中所示,在配線84之義 行鑛製以形成一鑛製層8 8。再者 ^ 、 裝半導體晶片i至基板82上之\者半如曰F中所示,在安 ⑵所密封。並且,如圖10G中所示密封材料 810,與鮮錫突塊89相接合,以完成半導以之印刷板 中所示…半導體裝置 〃 + V體歧置之習知製造方法遭遇下列問題。 體事Ϊ由3 中所示之製造方法所製成之習知的半導 品。ί 加熱與冷卻製造步驟’以完成最終產 口口牛例而吕,在如圖9G所示之製造步驟中,録吟 與主板71 0間之連接係形成於溫度約為24〇它、。並^ Α —tU-偏塵二,度 度約為125t時進行24小時’其中半導體裝置受 文熱。再者,為了驗證半導體裝置之晶片電 體741上鍍製層75間之連接部分之可靠度,以及 7於9;;p:rr,之連接部分之可靠度,熱備_^^ 、干v體衣置上。在此熱循環測試中,半導體裝置放置於 529135[Background of the Invention] [Field of the Invention] More particularly, the present invention relates to a high-density mounting. A semiconductor device and a manufacturing device thereof and a manufacturing method thereof. [Explanation of the related technology] New forms of semiconductor packaging have been developed one after another, with high performance, smaller size, lighter weight, and more demand. For example, by reducing the size of the semiconductor device and achieving a higher packaging density of the semiconductor wafer, lighter weight electronic equipment can be achieved. In order to achieve a higher packing density of semiconductor wafers, the number of half-pins has been increased. With the connection between the body chip of the semiconductor chip and the lead frame, a wireless bonding wire bonding system is often used as a bonding system to allow the semiconductor wafer pad to be connected to the wiring lead frame or external electrodes in an overlapping manner. This is called gang bonding. A tape automated bonding (TAB) system is used as a bonding system. In the TAB system, a plurality of wirings are formed in a tape-like manner by overlapping the guides formed on a substrate in a tape-like manner on a portion corresponding to the electrodes of the semiconductor wafer. In the meantime, the correspondence between the electrode pads of the wafer and the internal lead frame of the substrate is used to meet the requirements of electricity and higher speed and thickness in small size and increase in conductor wafers, semiconducting systems. Unmatched electrode bonding is used as a splicing joint-a kind of non-wiring. After a suitable rectangular solid lead frame overlaps the semiconductor part, 529135 V. Description of the invention (2) It is called an internal lead frame by thermal compression bonding or supersonic; : Wave: = The overlapping parts are connected together, which has been disclosed in Japanese Unexamined Specialist Example 2f. The internal lead frame joining industry is shown in Figures 9A to 9H. Known :: Heisei No. 8_1 02466. Manufacture method of the body device ^ The semi-conductor of the internal lead frame bonding is first described as shown in FIG. 9A. Within the range of ten // m. The thickness of the base plate 72 of a card portion 1 is located on its main surface. Another surface (aiheSiVe) 73 is coated on the substrate 72. An electrical material such as Cu or the like is used: a through hole 71 is formed in the plate. Guide 741. The deceased emperor of the United States will fill the through-hole 71 to form a conductor earth plate 72 which is not coated with the adhesive 73 and contacts the conductor 741. | ^ ^ 71 + y is formed as a wiring 74, such as copper, to or the like ::: As shown in Figure 9B, in the precise positioning conditions, the base second m On the conductor wafer 1. Subsequently, 'H 2 and H 2 are bonded to the semiconductor wafer 1 by continuous heating and pressure. The electrode bonding pad 10 is provided along the outer peripheral portion of the body sheet 1. However, electrode bonding pads have been placed in the active area. -Metal 'is typically a type alloy, which is a material used to form electrode bonding pads. The person then, as shown in FIG. 9C, performs internal lead frame bonding, and the substrate is connected to the substrate in the manner of thermal ultrasonic wiring bonding with the following method: 2 ^ half, said ^ 1. In this example, since thermal conditions are required in thermal compression wiring bonding, thermal ultrasonic wiring bonding is used. By this joining, the shell / mouth shape 529135 V. Description of the invention (3) '--- The aluminum of the electrode bonding pad 10 of the sheet 1 and the copper forming the substrate 72 are cast into an alloy. Therefore, the connection portion can be strengthened. Then, as shown in Fig. QD, the bonding of V / substrate 72 on the opposite surface of the & 1 1 surface, ... ,, on the spear surface, a solder ball with a predetermined pattern is formed. Subsequently, as shown in FIG. 9E, the copper or copper + π knife (the part used to set the external electrode in the subsequent process steps) is placed. Therefore, as shown in FIG. 9F, for the plated product 78 in the subsequent process = where: a solder bump 79 is formed as an external electrode. Subsequently, "the printed board 710 formed by glass epoxy #: or ΪΓ; ΐ: is not after the outer contour of the knife brake (not shown), and is connected to the solder bump. Finally, in order to ensure that the printed board 71 〇 and solder The connection between the protrusions 79 ^ strengthen the tree injection between the printed board 71G and the substrate 72, and is determined by adding β. A semiconductor device is manufactured through the described manufacturing method. ',', Another-side, the practice of semiconductor devices Another known manufacturing method is the manufacturing method of the known semiconductor device disclosed in Japanese Unexamined Patent Publication No. Heisei 10-1510116, which is shown in FIGS. 1 to 2 and is shown in FIGS. 1 to 10. Η The conventional manufacturer of the semiconductor device shown: As shown in FIG. 10A, the polyimide 'insulating substrate 8 2 is still used in the manufacture of semiconductor devices, similar to that shown in FIGS. 9A to 99. Manufacturing method. In the conventional manufacturing method of the semiconductor device shown in 10A to 10A, ^ 84 丨 is deposited on one of the major surfaces of the substrate W. The copper deposit on the substrate 82 is removed by the remaining time. Unnecessary part to form such as f, wiring 84. τ 岍 不 之 529135 five Description of the invention (4) lase〇 ′ ^ A ^ 〇82l ^? # Tt ^ (carbon gas Γ plane opening = 甬 =, the surface of the opposite side of the surface forming the wiring 84 forms a bayonet port 81. At this time, since ^ ^ ^ May cause incomplete removal of the residual resin 83 from the foaming residue in 81, as shown in Fig. 10E-followed by as shown in Fig. 10E. As shown, the wiring at the wiring 84 is mined to form a mineral layer 88. Furthermore, the semiconductor wafer i mounted on the substrate 82 is sealed as shown in F, and sealed in Ahn. As shown in FIG. 10G, the sealing material 810 is engaged with the fresh tin bump 89 to complete the semiconductor board shown in the printed board ... The conventional manufacturing method of the semiconductor device 〃 + V-body divergence encounters the following problems.习 Conventional semiconducting product made by the manufacturing method shown in 3. ‚Heating and cooling manufacturing steps' to complete the final production example, recorded in the manufacturing steps shown in Figure 9G, The connection between the Yin and the main board 71 0 is formed at a temperature of about 240 ° C, and ^ Α —tU-Partial Dust II, which is performed for 24 hours at a degree of about 125t. Semiconductor devices are subject to heat. In addition, in order to verify the reliability of the connection parts between the plating layer 75 on the wafer body 741 of the semiconductor device, and 7 to 9; p: rr, the reliability of the connection parts, hot standby _ ^^, put on a dry v body suit. In this thermal cycle test, the semiconductor device was placed in 529135

溫度於-50至+150 t:之範圍中變化之環境中,以In environments where the temperature varies from -50 to +150 t:

變化數百循環,檢查連接部分之破裂或斷開之笋 驗連接部分之可靠度 X 力 ·/ μ ,可肌π且心1固別部分之膨 此不同。舉例而·言,當半導體晶片i、基板72、以及印刷 板710 ’分別為Si晶片、聚醯亞胺有機 -/〇---〇ρρ- c以及16至50 ppm/ C。既然當經 的熱膨脹係數,故介於半導體裳置之晶反片1 電°極==同 席J板710間之連接部分遭受壓力,、/ 72間之膨脹係數之差里, 牛導體日日片1與基板 膨脹俜數^ 乂及基板72與印刷板710間之熱 外導致破裂或斷開。尤其,既然作為 料,例如r ^ a 1塊79 ’接觸各種具有不同膨脹係數之材 的應= 印刷板m等等,實質 上,由於此望2 與印刷板710間之連接部分 斷開。作為避,免:差j:容易造成前述之破裂或 印刷板71 〇與半導體衣/汗之*係、,提供一較大距離於 72、盥印刷上導體曰曰片1間’以容許半導體晶片1、基板 接表面之太a接表面,以及基板72與印刷板710間之連 由提供較大厚声:接部分上之應力。舉例而言’藉 子度之基板72,可使印刷板71〇與半導體晶片工Change hundreds of cycles, check the rupture or disconnection of the connected part. Check the reliability of the connected part. X force · / μ, the muscle π and the expansion of the solid part of the heart 1 are different. For example, when the semiconductor wafer i, the substrate 72, and the printed board 710 'are Si wafers, polyimide organic- / 〇 --- 〇ρρ-c, and 16 to 50 ppm / C, respectively. Since the thermal expansion coefficient of the current time, the semiconductor wafer placed between the wafer 1 and the electric pole == the joint between the J plate 710 under the same pressure, the difference between the expansion coefficient between / 72, 1 and the expansion of the substrate 俜 ^ 乂 and the heat outside the substrate 72 and the printed board 710 cause cracking or disconnection. In particular, since as a material, for example, r ^ a 1 79 ′ should be in contact with various materials having different expansion coefficients = printed board m, etc., in essence, since the connection between this terminal 2 and the printed board 710 is broken. As a avoidance: poor j: easy to cause the aforementioned rupture or the printing board 71 〇 and semiconductor clothing / sweat, provide a larger distance to 72, printed on the conductor, said 1 piece of film to allow semiconductor wafers 1. The a surface of the substrate connection surface and the connection between the substrate 72 and the printed board 710 provide a thicker sound: the stress on the connection portion. For example, a substrate 72 of a degree allows the printed board 71

529135 五、發明說明(6) 間之距離變得較大,以吸收連接部分上之應力。 迭方t方面,在圖9A至9請示之半導體裝置之習知的製 中,包含圖9C中所示之接合步驟。在接合製程中, =片電極1〇與基板72接合之後,從基板72之侧邊,藉由 連具76之熱超音波配線接合,使晶片電極1〇被機械性 f而’倘若基板72具有較大厚度,以吸收施加於連接 ::士Π ’在接合製造步驟中,接合工具76所施加之 合之能量,於達到連接部分之前,被吸收 或ί=:材Γ,俾使能量不傳送至晶片電極 飞作為連接部分之鍍製層75上,以避免連接失誤。529135 V. Description of the invention (6) The distance between (6) becomes larger to absorb the stress on the connecting part. In the superposition t, the conventional manufacturing method of the semiconductor device shown in Figs. 9A to 9 includes the bonding step shown in Fig. 9C. In the bonding process, after the sheet electrode 10 is bonded to the substrate 72, the side of the substrate 72 is bonded by the thermal ultrasonic wiring of the connector 76, so that the wafer electrode 10 is mechanically f and 'if the substrate 72 has Larger thickness to absorb the energy applied to the connection :: 士 Π 'In the joint manufacturing step, the energy applied by the joint tool 76 is absorbed or reached before reaching the joint part, so that energy is not transmitted The wafer electrodes fly onto the plated layer 75 as a connection portion to avoid connection errors.

再者,既然使用熱超音波配線接合作A ;,削之位於連接部分附近之部作:二^ …:收而損壞。因而,受損的連接部分附用: 小,導致難以足夠地吸收應力。 女7炎 ::所二’在圖9八謂所示之半導體裝 =方法中,為了在接合製造步驟中避免 ς 〇誤,必須限制基板72之厚度為小於或等於夂接 了面•藉由使基板72之厚度變小’使吸收施加於 連接部/刀上之應力變得困難,導致連接部分中之破 齡 開,降低連接之可靠度戋降&產。良& 、或斷 力之降低。 #厪次降低產-良旱,且因此導致生產 、此外’在圖9Α至9Η所示之半導體裝置之習知的 法中’如圖9Η中所示,為了確定地獲得主板71 〇與銲錫突Furthermore, since the thermosonic wiring is used to connect to A; the part near the connection part is cut as follows: two ^…: received and damaged. Thus, the damaged connection portion is attached: small, making it difficult to sufficiently absorb the stress. Female 7 Yan :: So, in the semiconductor device = method shown in FIG. 9, in order to avoid errors in the bonding manufacturing steps, the thickness of the substrate 72 must be limited to be less than or equal to the contact surface. Making the thickness of the substrate 72 smaller makes it difficult to absorb the stress applied to the connection part / knife, which leads to the breakage of the connection part and reduces the reliability of the connection. Good &# 厪 次 Reduce production-good drought, and therefore lead to production, in addition, in the conventional method of the semiconductor device shown in Figs. 9A to 9 (), as shown in Fig. 9 (), in order to obtain the main board 71 〇 and solder bumps with certainty

第10頁 529135 五、發明說明(7) 塊79間之連接強度,進行一製造步驟,以加熱且設定一注 入於印刷板710與基板72間之強化樹脂714。當失誤發生於 半導體晶片或位於半導體晶片】與印刷板71 〇間之部^,例 如配線或諸如此類者時,既然強化樹脂714注入^刷板71〇 與基板7 2間,用以密封,故無法修復有缺陷的部分。因 而’保持力(maintenance ability)變低。 另 方面 • 、 在圖10A至1011所示之半導體裝置之習知的 製造方法,在藉由雷射使基板82中之貫通口 83形之 連接基板8 2與半導體晶片1。亦即,如圖丨〇 F中所示,在 ϋ曰:片1安置於基板82上之後,半導體晶片】被密封材料 85饴封二通常地,熱硬化型樹脂經常作為密封材料π。因 而,半導體晶片1與密封材料之接合製程典型地包含加熱 製程。另-方® ’在此例子中,在加熱條件下由校準 設置於基板82與半導體晶片】上之位置標誌,使用曰定位以 進行基板8 2與半導體晶片1之接合。 然而,如前所述,在圖10A至10H所示之半 習知的製造方法中,加熱製程被包含於基板82與半導體工 之接合中。在此例子中,既然半導體晶片i與基板82之埶 膨脹係數彼此不同’故在加熱製程中,半導體晶片心 板82以不同之比率發生熱膨脹。因而,當安置時, 晶片1與基板82間發生錯位(disl〇cati〇n),導致難以在正 確位置處接合基板82與半導體晶片!。偏若基板82盥半導 體晶片1並未接合於正確位置,則連接阻值增加,由於連 接面積之減少’使作為外界電極之鲜錫突塊89與印刷板 529135Page 10 529135 V. Description of the invention (7) The connection strength between the blocks 79 is subjected to a manufacturing step to heat and set a reinforcing resin 714 injected between the printed board 710 and the substrate 72. When the error occurs between the semiconductor wafer or the semiconductor wafer] and the printed board 71 °, such as wiring or the like, since the reinforced resin 714 is injected between the brush plate 71o and the substrate 72 to seal, it cannot be sealed. Repair the defective parts. Therefore, the 'maintenance ability' becomes low. On the other hand, in the conventional manufacturing method of the semiconductor device shown in FIGS. 10A to 1011, a through-hole 83 in the substrate 82 is connected to the substrate 8 2 and the semiconductor wafer 1 by laser. That is, as shown in FIG. 10F, after the wafer 1 is placed on the substrate 82, the semiconductor wafer is sealed by a sealing material 85. Generally, a thermosetting resin is often used as the sealing material π. Therefore, the bonding process of the semiconductor wafer 1 and the sealing material typically includes a heating process. In addition, in this example, the position mark on the substrate 82 and the semiconductor wafer] is calibrated under heating conditions, and the positioning is used to join the substrate 8 2 and the semiconductor wafer 1. However, as described above, in the semi-conventional manufacturing method shown in FIGS. 10A to 10H, a heating process is included in the bonding of the substrate 82 and the semiconductor process. In this example, since the expansion coefficients of the semiconductor wafer i and the substrate 82 are different from each other ', during the heating process, the semiconductor wafer core 82 undergoes thermal expansion at different ratios. Therefore, when placed, a dislocation (disccation) occurs between the wafer 1 and the substrate 82, making it difficult to join the substrate 82 and the semiconductor wafer at the correct position! . If the substrate 82 and the semiconductor wafer 1 are not bonded to the correct position, the connection resistance value increases, and the fresh tin bump 89 and the printed board 529135 as external electrodes are reduced due to the reduction of the connection area.

81 0間連接部分之連接力降低,容易導致連接部分中之破 裂或斷開。因此,半導體裝置之製造良率以及生產力降 〔發明概述〕 本發明業已製作出,以解決前述習知技術中之問題。 因而,本發明之目的在於,提供一種半導體裝置之製 造方法,達成高生產力與一可以高良率製造之半導體裝衣 置。 、The connection force of the 81 joints is reduced, which may easily cause cracks or disconnections in the joints. Therefore, the manufacturing yield and productivity of semiconductor devices are reduced. [Summary of the Invention] The present invention has been made to solve the problems in the aforementioned conventional technologies. Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device, which achieves high productivity and a semiconductor device that can be manufactured with a high yield. ,

本發明之另一目的在於,提供一種半導體裝置之製造 方法以及該半導體裝置,可吸收施加於外界電極上之應° 本發 方法以及 依據 法,包含 在使 上之後, 形成 口中,以 較佳 片之該電 在前 穿過基板 明之又一 該半導體 本發明之 下列步驟 一半導體 形成一穿 一導體, 使該導體 地,貫通 極之位置 述之本發 而形成, 禋牛等體裝置之製造 目的在於,提供一 裝置,可改善保持能力 第一態樣,一種半導體裝置之製造方 晶片保持於作為一膜之一基板之一 過該基板貫通口;以及 ::體由一鍍製層所形&,位於該貫通 連接至該半導體晶片之一電極。貝通 =係e又置於基板中之對應於該半導體晶 月t,在保持半導體晶片之後,貫通口 且精由錢製使導體形成於貫通口中,導Another object of the present invention is to provide a method for manufacturing a semiconductor device and the semiconductor device capable of absorbing a stress applied to an external electrode. The method and method according to the present invention are included in a mouth after being applied, and a preferred chip is formed. The electricity is passed through the substrate in advance. Another semiconductor is described in the following steps of the present invention. A semiconductor is formed into a conductor, and the conductor is formed at the position of the penetrating pole. The purpose of manufacturing the yak and other devices The first aspect is to provide a device that can improve the holding capacity. A semiconductor device manufacturing wafer is held at one of the substrates as a film through the substrate through-hole; and: the body is formed by a plating layer &; Is located on one of the electrodes connected to the semiconductor wafer. Beton = Department e is placed in the substrate corresponding to the semiconductor crystal t. After the semiconductor wafer is held, the through-hole is made of money and the conductor is formed in the through-hole.

五、發明說明(9) 體可連接至半導體晶片之電#。“ 基板。所以,印刷板與半導體曰 可提供足夠厚度之 分地吸收施加於基板與半 :二之距離足夠寬,以充 ;力接=,在半導體裝置=接部分之 用之接ά步驟中,能量不僅 方法中所典型使 至配線、導體、或環繞連接部八=、接的部分,亦傳送 接合中所使用之接合工具之^ 〃他部分。再者,藉由 響。所以,其他部分被損壞,二降低^能造成惡劣影 力。然而,藉由依據本發明之製造方二、%連接部分之連接 體晶片之電極間可在不影響1他;八1袢既然基板與半導 藉此,可成功地;方連接部… 體裝置之生產率之改Ϊ Ρ刀處之破裂或斷開,導致半導 片之Π或:法,既然可修復半導體晶 線,故可改善料與印刷板間之部分,例如配 成於ί板::貫ΐ本ί明中’由鍍製層所組成之配線可形 成於基板上之貝通口中,與導體積合成一體。 而旦/ ^ ^ ^體裝置之習知的製造方法中’隨著基板之使用 Τ曰半導體晶片之連接,該基板上預先提供有配線圖 η、二因而’在形成有相同的半導體晶片與基板之半導體晶 :’用以準備,有不同配線圖案之半導體晶圓,半導體 :,連接係進仃於每一具有不同配線圖案之基板上,以 ’母具有不同配線圖案之基板之不同的層製造方法。 529135 五、發明說明(10) 然而’在本發明中’既然由鑛製層所組成之配線可形 成於基板上,與導體積合成一體,故於使半導體晶片接合 於基板之後,配線圖案可形成於基板上。因而,從相同的 半導體晶片與基板之組合,可形成具有各種配線圖案之半 體晶圓’以有意義地縮短半導體裝置之製造方法。因 此,可以低成本製造半導體裝置。 方面,在習知的製造方法中 另 板上形成有配線圖案,用以在導體形成於貫通口中之後接 觸導體。既然基板係與導體及配線分離地 :成於雜質沉積於基板上之條件下,則連接:分; :思谷易造成破裂或斷開。然❿,依據本發明,既然由 成之配線且配線可與導體基合成-•,故絕不 間之破裂或斷開1製造具有高連接可 於a f =面’在本發明中,#複數個半導體晶片被保持 亘二戶日守,樹脂填入半導體晶片間。因此,可容易庐尸 絕於半導體曰片二二 +導體裝置,其中外界電極隔 部與位於半‘㈡二。此外,ι然可修復配線晶片之内 改善保持2 片與印刷板間之…例如配線,故可 法U本發明之第二態樣’—種半導體裝置之製造方 使複數個半導體晶 面上; 片保持於作為一膜之一基板之 表 529135 五、發明說明(11) 形成一貫通口於該基板之預定的位置處; 使樹脂填入該複數個半導體晶片間;以及 形成一由鍍製層所形成之導體於該貫通口中,且使該 導體連接至該半導體晶片之一電極。 依據本發明之第三態樣,一種半導體裝置之製造方 法,包含: 使複數個半導體晶片保持於作為一膜之一基板之一表 面上; 形成一貫通口於該基板之預定的位置處; 使樹脂填入該複數個半導體晶片間;以及 形成一由鍍製層所形成之導體於該貫通口中,且使該 導體連接至該半導體晶片之一電極,且形成一由鍍製層所 形成之配線於該基板上,與該導體積合成一體。 依據本發明之第四態樣,一種半導體裝置,包含: 一具有膜形式之基板’保持有一^半導體晶片5該半導 體晶片之一側上具有一電極; 一貫通口形成於對應於該半導體晶片之位置上,穿過 該基板, 藉由一鍍製層,形成一導體於該貫通口中,且連接至 該半導體晶片之該電極,以及 該貫通口具有一第一開口部分於該半導體晶片之側 上,該第一開口之寬度小於在其他側上之第二開口部分之 寬度。 藉由前述之半導體裝置,既然在半導體晶片之侧之相5. Description of the invention (9) The body can be connected to a semiconductor wafer. "Substrate. Therefore, printed boards and semiconductors can provide sufficient thickness to absorb and apply to the substrate and half: the distance between the two is wide enough to charge; force connection =, in the semiconductor device = connection part of the connection steps The energy is not only the part typically connected to the wiring, the conductor, or the surrounding connection part in the method, but also the ^ and other parts of the bonding tool used in the bonding. Furthermore, by ringing. So, the other parts If it is damaged, it can cause bad shadow. However, by the manufacturing method according to the present invention, the electrodes of the connector chip of the% connection part can not affect one another; 8 1 袢 Since the substrate and semiconductor Therefore, the success rate of the square connection part ... The productivity of the body device is broken or disconnected at the P-knife, which leads to the π or: method of the semiconductor. Since the semiconductor crystal line can be repaired, the material and the printed board can be improved. The part between them is, for example, prepared on the board :: The printed wiring composed of the plating layer can be formed in the shell port on the substrate to be integrated with the guide volume. Dan / ^ ^ ^ 体In the conventional manufacturing method of the device ' The connection to the substrate is referred to as a semiconductor wafer connection, and a wiring pattern η is provided in advance on the substrate. Therefore, 'Semiconductor crystals with the same semiconductor wafer and substrate formed:' are used to prepare semiconductor wafers with different wiring patterns. Semiconductor: The connection is made on each substrate with different wiring patterns, and the method of manufacturing different layers of the substrate with different wiring patterns is used. 529135 V. Description of the invention (10) However, 'in the present invention' Since the wiring composed of the mineral layer can be formed on the substrate and integrated with the guide volume, the wiring pattern can be formed on the substrate after the semiconductor wafer is bonded to the substrate. Therefore, from the same combination of the semiconductor wafer and the substrate It is possible to form a half-wafer with various wiring patterns to significantly shorten the manufacturing method of a semiconductor device. Therefore, a semiconductor device can be manufactured at a low cost. On the other hand, in the conventional manufacturing method, a wiring pattern is formed on another plate, and To contact the conductor after it has been formed in the through hole. Since the substrate is separated from the conductor and wiring: Under the condition that the impurities are deposited on the substrate, then the connection: points;: Sigu easily breaks or disconnects. However, according to the present invention, since the wiring is formed and the wiring can be synthesized with the conductor base-•, it is never Breaking or disconnecting between the 1 manufacturing with a high connection can be af = face 'In the present invention, # a plurality of semiconductor wafers are kept at the second house, and the resin is filled between the semiconductor wafers. Therefore, it can be easily destroyed. Semiconductor chip 22 + conductor device, in which the external electrode partition is located in the half of the second. In addition, it can repair the wiring chip to improve the retention between the 2 and the printed board ... such as wiring, so the invention can be used The second aspect'—manufacturer of a semiconductor device uses a plurality of semiconductor crystal planes; the sheet is held on a table as a film and a substrate 529135 V. Description of the invention (11) A predetermined opening is formed on the substrate At a position; filling resin between the plurality of semiconductor wafers; and forming a conductor formed by a plating layer in the through hole, and connecting the conductor to an electrode of the semiconductor wafer. According to a third aspect of the present invention, a method for manufacturing a semiconductor device includes: holding a plurality of semiconductor wafers on a surface of a substrate as a film; forming a through hole at a predetermined position on the substrate; Resin is filled between the plurality of semiconductor wafers; and a conductor formed by a plating layer is formed in the through hole, and the conductor is connected to an electrode of the semiconductor wafer, and a wiring formed by the plating layer is formed It is integrated with the guide volume on the substrate. According to a fourth aspect of the present invention, a semiconductor device includes: a substrate in the form of a film 'holds a semiconductor wafer 5 having an electrode on one side of the semiconductor wafer; a through-hole is formed corresponding to the semiconductor wafer In position, a conductor is formed in the through hole through the substrate through a plating layer, and is connected to the electrode of the semiconductor wafer, and the through hole has a first opening portion on the side of the semiconductor wafer The width of the first opening is smaller than the width of the second opening portion on the other side. With the aforementioned semiconductor device, since the phase on the side of the semiconductor wafer

第15頁 529135 五、發明說明(12) 對側上的貫通口之開口部 ^ 有導體,可使導體與外展、、=,该貫通孔中形成 大,以使連接阻值較小:且二:;連=分之面積製得較 度。藉此,可成功地防止、卓:二強J接一分處之連接強 成較高的製造良率。連接^刀處之破裂與斷開,以達 較佳地,貫通口之直徑大於半導體晶 度。猎此,可增加連接部分 電極之見 之阻值。 刀之強度且可降低連接部分處 較佳之情形,基板之厚度係位於5〇至 内。藉此,基板與印刷板間之距離變 巳八圍 :施加於基板與印刷板間之連接部分上之應力。因= 接部分處之破裂與斷開,以達成高製造良率 當貫通Π中連接於導體之外界電極被連接至印刷板 呀,剝除強度係設定於14至18 kgf/cmi範圍内。藉此, 可充分地吸收施加於基板與印刷板間之連接部分上9之應 力。因此,可成功地防止連接部分處之破裂與斷開,以達 成具有高製造良率之半導體裝置。 依據本發明之第五態樣,一種半導體裝置,包含: 具有膜形式之基板,保持有一半導體晶片,該半導 體晶片之一側上具有一電極; 一貫通口形成於一對應於該半導體晶片之位置上,穿 過該基板; 藉由一鍍製層,形成一導體於該貫通口中,且連接至Page 15 529135 V. Description of the invention (12) The opening of the through-hole on the opposite side ^ has a conductor, which can make the conductor and the abduction, and =, the through-hole is formed large so that the connection resistance is small: and Two :; even = the area is made comparative. In this way, it can be successfully prevented that the connection between the second strong J and the second strong office can force a higher manufacturing yield. The rupture and disconnection at the connecting blade is preferably to achieve that the diameter of the through opening is larger than the semiconductor crystallinity. By doing this, you can increase the resistance of the electrodes in the connected part. It is preferable that the strength of the blade can be reduced at the connection portion, and the thickness of the substrate is within 50 to. As a result, the distance between the substrate and the printed board is changed. Eighth: The stress applied to the connection portion between the substrate and the printed board. Because of the fracture and disconnection at the junction part to achieve a high manufacturing yield. When the electrodes connected to the outer boundary of the conductor are connected to the printed board, the peel strength is set within the range of 14 to 18 kgf / cmi. Thereby, the stress applied to the connection portion 9 between the substrate and the printed board can be sufficiently absorbed. Therefore, it is possible to successfully prevent cracking and disconnection at the connection portion to achieve a semiconductor device with a high manufacturing yield. According to a fifth aspect of the present invention, a semiconductor device includes: a substrate in the form of a film, which holds a semiconductor wafer having an electrode on one side of the semiconductor wafer; a through hole formed at a position corresponding to the semiconductor wafer Through the substrate; through a plated layer, a conductor is formed in the through hole and is connected to

第16頁 529135 五、發明說明(13) 該半導體晶片之該電極; 一鍵製層之配線形成於該貫通口中,與該導體積合成 一體;以及 該貫通口具有一第一開口部分於該半導體曰曰片之側 上,該第一開口之寬度小於在其他侧上之第二開口部分之 寬度。 依據本發明之第六態樣,一種半導體裝置,包含: 一具有膜形式之基板,保持有一半導體晶片,該半導 體晶片之一側上具有一電極;Page 16 529135 V. Description of the invention (13) The electrode of the semiconductor wafer; a wiring of a keying layer is formed in the through hole and integrated with the guide volume; and the through hole has a first opening portion in the semiconductor On the side of the sheet, the width of the first opening is smaller than the width of the second opening portion on the other side. According to a sixth aspect of the present invention, a semiconductor device includes: a substrate in the form of a film, holding a semiconductor wafer, and an electrode on one side of the semiconductor wafer;

一貫通口形成於一對應於該半導體晶片之位置上,穿 過該基板; 藉由一鍍製層,形成一導體於該貫通口中,且連接 該半導體晶片之該電極; 一鍍製層之配線形成於該貫通口中,與該 一艚:以芬 T肢WS成 一外界電極形成於該基板上,且連接至該 除強度位於14至18 kgf/cm之範圍内,使該 -’在制 於該印刷板上。 卜界電極接合 〔車父佳實施例之詳細說明〕 茲將參照圖示,以本發明之較佳實 細探討依據本發明之較佳實施例如下。、下乍為參考,詳 ♦多的具體特定細節係用以提供本發明~文之說明中, 而,顯然地,對於熟習此項技藝之人士,=全了解。然 件不需此等具體A through hole is formed at a position corresponding to the semiconductor wafer, and passes through the substrate; a conductor is formed in the through hole through a plating layer, and the electrode of the semiconductor wafer is connected; a wiring of the plating layer It is formed in the through hole and is connected with the ridge: fen T limb WS is formed as an external electrode on the substrate, and is connected to the removal strength within the range of 14 to 18 kgf / cm, so that the-'is made in the Printing board. Boundary electrode bonding [Detailed description of Che Fujia's embodiment] With reference to the drawings, the preferred embodiment of the present invention will be discussed in detail below with reference to the preferred embodiment of the present invention. For reference, the following details. ♦ Many specific details are provided in the description of the present invention. However, obviously, for those who are familiar with this technology, = fully understand. However, such details are not required

529135529135

特定細節而實施本發明。 第一 rn顯示依據本發明半導體裝置之製造方法之 每貝也例圖2係顯示依據本發明之半導體裝置镇一 貝鼽例。圖3係顯示依據本發明之半導體裝置之第一每 ,之一例子。圖4係顯示依據本發明之半導體裝置之二二 實施例之另一例子。 第一 •依據本發明之半導體裝置之第一實施例係内建 (built-in)於一封裝,例如 BGA(BaU Grid Array, 陣列)或CSP(Chip Size Package,晶片尺寸封裝)。二: 不之半導體裝置實施例具有一扇出(Fan —〇ut)結構,其#中 一外界電極被配置於半導體晶片表面之外部。另一方面, 依據本發明半導體裝置之第一實施例係由TAB系統所製 成’用以提供複數條配線,藉由適當方式,以重疊且連接 重複形成的導體之配線導線架與對應於複數個半導體晶片 之電極之部分。詳言之,半導體裝置之製造係藉由一 5部 導線架接合系統,其中在半導體晶片之電極接合墊與基板 内部導線架之對應部分重疊之後,半導體晶片之電極接合 墊與基板之内部導線架之對應部分相互接合。 繼之’參照圖1A至1 Η,討論依據本發明半導體裝置之 製造方法之實施例。 如圖1Α中所示,當製造半導體裝置時,使用一基板 12 ’该基板之一表面上塗覆有膠黏劑13。基板12之厚度最 好位於5 0至3 5 0 // m之範圍内。考量經濟性,基板1 2之厚 度之較佳範圍係5 0至1 0 0 // m之範圍。藉由設定基板1 2之The invention is implemented with specific details. The first rn shows an example of a semiconductor device manufacturing method according to the present invention. FIG. 2 shows an example of a semiconductor device according to the present invention. FIG. 3 shows an example of a semiconductor device according to the present invention. Fig. 4 shows another example of the second embodiment of the semiconductor device according to the present invention. First • A first embodiment of a semiconductor device according to the present invention is built-in in a package, such as a BGA (BaU Grid Array) or a CSP (Chip Size Package). Second: The embodiment of the semiconductor device has a fan-out structure, in which an external electrode is arranged outside the surface of the semiconductor wafer. On the other hand, the first embodiment of the semiconductor device according to the present invention is made of a TAB system to provide a plurality of wirings, and in a suitable manner, a wiring lead frame that overlaps and connects repeatedly formed conductors with a plurality of corresponding wirings. The electrode portion of a semiconductor wafer. In detail, the semiconductor device is manufactured by a 5-lead frame bonding system. After the electrode pads of the semiconductor wafer and the corresponding portion of the inner lead frame of the substrate overlap, the electrode pads of the semiconductor wafer and the inner lead frame of the substrate The corresponding parts are joined to each other. Next, referring to Figs. 1A to 1A, an embodiment of a method for manufacturing a semiconductor device according to the present invention will be discussed. As shown in Fig. 1A, when manufacturing a semiconductor device, a substrate 12 'is used, and one surface of the substrate is coated with an adhesive 13 thereon. The thickness of the substrate 12 is preferably in a range of 50 to 3 5 0 // m. In consideration of economy, a preferable range of the thickness of the substrate 12 is in a range of 50 to 100 0 // m. By setting the substrate 1 to 2

第18頁 529135 五、發明說明(15) 厚度,基板12與主板110間之厚度可做 力之吸收,該應力係施加於基板丨2歲于軚大,以允許應 分以及作為外界電極之銲錫突鱼卩刷板11間之連接部 接。另-方面,基板12係由一ί機:::板110間之連 亞胺樹脂’環氧樹脂或諸如此類者:曰所形成’例如聚醯 隨後,如圖1Β中所示,基板12之 劑,半導體晶Η 1 >本& u + # φ Jl塗覆有勝黏 10,在基板12之表面與半導體曰熱片形成-晶片電極 Γ所示,-樹_:半導;:=面=後 :m ί諸如此類者施加於半導體晶片1之表面上, 然而,為簡化揭露說明,圖示中忽略此保匕片 物層。應注意者為,此時所進行之使樹脂i 6填入半匕 片1間之製造步驟’得被t代為進行於後續製程進行之晶 (參照圖1F),下文中將探討該後續製程。再者,藉 \ 射照射於基板12之一側,位於基板12中對應於半導體晶= 1之晶片#電極1 0之部分處,使貫通口 11之開口形成於二曰曰表^ 面上’穿過基板1 2。在此實施例中,使用u v - γ a g (Ultraviolet-Yttrium Argon Garium)作為雷射。貫通 口 11之直桎係設定於1〇至5〇 //m之範圍内。另一方面,貫、 口 11之開口部分之尺寸係設定為:使得半導體晶片之二$ 上之開口部分之寬度小於位於相對侧上(作為外界電極之’ 鲜錫突塊1 9之一侧上)之開口部分之寬度。因此,貫通〇 11形成為截錐形(truncated cone)型態。Page 18 529135 V. Description of the invention (15) Thickness. The thickness between the substrate 12 and the main board 110 can absorb the force. The stress is applied to the substrate. 2 years old and older, to allow application and soldering as an external electrode. The connection portions between the tuna brush plates 11 are connected. On the other hand, the substrate 12 is made of an imide resin: epoxy resin or the like of the plate 110: epoxy resin or the like: formed, for example, polyfluorene. Then, as shown in FIG. , Semiconductor wafer 1 > 本 & u + # φ Jl is coated with Succeed adhesive 10, and the surface of the substrate 12 is formed with a semiconductor thermal sheet-as shown by the wafer electrode Γ-tree_: semiconductor;: = surface = After: m ί and the like are applied to the surface of the semiconductor wafer 1, however, to simplify the disclosure description, the object layer of the dagger is omitted in the illustration. It should be noted that, at this time, the manufacturing step of filling the resin i 6 into the half dagger 1 'must be replaced by t in the subsequent process (see FIG. 1F), which will be discussed later. Furthermore, by irradiating one side of the substrate 12 at a portion of the substrate 12 corresponding to the wafer #electrode 1 of the semiconductor crystal = 1, the opening of the through hole 11 is formed on the surface of the second surface. Pass through the substrate 1 2. In this embodiment, u v-γ a g (Ultraviolet-Yttrium Argon Garium) is used as the laser. The straightness of the through hole 11 is set in a range of 10 to 50 // m. On the other hand, the size of the opening portion of the gate 11 is set so that the width of the opening portion on the semiconductor wafer 2 $ is smaller than on the opposite side (on the side of the fresh electrode bump 19 as the external electrode). ) The width of the opening. Therefore, the through hole 11 is formed into a truncated cone shape.

第19頁Page 19

529135 五、發明說明(16) 隨後’如圖1 D中所示’在基板1 2上,藉由濺鑛形成作 為導體之一 Cu層15,其厚度約為1 //m。在Cu層15上,使 用Cu形成一電解液鍍製層,其厚度為1〇至15 。藉此, 半導體晶片1之晶片電極10連接於貫通口 Η中之導體。— 由鑛製層所开>成之配線14形成於基板12上,與Cu層15 —體 =成為導體。因此,可獲得具有高連接可靠度之半導體裝 繼之,如圖1E中所示,在配線14上,塗覆具有一 圖案之阻膜1Π。再者,在曝光與顯影阻膜1;11之後, =1 淨4ί ’ 成阻膜111之部☆,進行⑶之圖案韻刻, 膜17。繼而,對於銲錫阻膜”,進行曝 提供一開口部分η 2位阻於m 顯/之部分被移除,以 者,鍵製進行於開口部分112=中(失二再 例中,藉由金或諸如此類之盔制"、、圖)。在此貫施 其厚度約為0.1 。鈇而…、電鍍衣,形成一鍍製層18, 藉由通常使用之電解液、梦再不僅可藉由無電鍍製,亦得 隨後,如圖製:成鐘製層18。 安置於開口部分丨丨2上,下、乍為外界電極之銲錫突塊1 9係 分11 2間之連接。麩接用以建立半導體突塊1 9與開口部 面)中,進行外部在樹脂16之部分(此處為A-A,表 上’ 2得半導體裝置之實二’。错由安置於印刷板u〇 經由圖以至丨!!所示 j 表W方去之實施例所獲得之半導 第20頁 529135529135 V. Description of the invention (16) Subsequently, as shown in FIG. 1D, a Cu layer 15 as a conductor is formed by sputtering on the substrate 12 and has a thickness of about 1 // m. On the Cu layer 15, an electrolytic plating layer is formed using Cu to a thickness of 10 to 15. Thereby, the wafer electrode 10 of the semiconductor wafer 1 is connected to the conductor in the through hole Η. — A wiring 14 made of a mineral layer is formed on the substrate 12 and forms a conductor with the Cu layer 15. Therefore, a semiconductor device having high connection reliability can be obtained. As shown in FIG. 1E, on the wiring 14, a resist film 1Π having a pattern is coated. Furthermore, after the exposure and development of the resist film 1; 11, = 1, the portion 4 becomes the portion of the resist film 111 ☆, and the pattern rhyme engraving of the film 17 is performed. Then, for the solder resist film ", the exposure provided an opening portion η 2 where the steric hindrance at m / was removed, so that the bonding was performed at the opening portion 112 = middle (in the second example, by gold Or helmets and the like), and its thickness is about 0.1. Here, ..., electroplated clothing, to form a plating layer 18, with the commonly used electrolyte, dream can not only be achieved by Without electroplating, it must be followed, as shown in the figure: the bell layer 18. It is placed on the opening 丨 2 and the bottom and top are the solder bumps of the external electrode 19 and the connection between 11 and 12. The bran is used for brazing. In order to establish the semiconductor bump 19 and the surface of the opening), the external part of the resin 16 (here, AA, the table "2 is the second real semiconductor device". It is placed on the printed board u〇丨 !!!! The semiconducting guide obtained by the example shown in Table W, page 20, 529135

如圖2中所示,從半導體晶片1與膠黏劑 ㈣之範圍内。二刷板:1;之寬度位於約為35 0 _至650 # ^ ^ ^ /、間,攸半導體晶片1與膠黏劑1 3間之連接 = 銲錫阻膜17之厚度位於約為50至350 "m之範圍 ^且!!銲錫阻膜17至印刷板110間之厚度約為3G。_。 膜17二ί導體晶片1與膠黏劑13間之連接表面至銲锡阻 曰、 見度之大部分係由基板1 2所佔用。因而,從半導 ϊΓΛ膠Λ齊ΓΓ之連接表面至鲜錫阻膜17之厚度變得 焉貝上等於基板12之厚度。 據此,半導體裝置之實施例所提供之基板丨2之厚产 2於50至35〇 ”之範圍内。考量經濟性,基板12之又^ ^旱度係位於50至1〇〇 之範圍内。在半導體裝置之實 轭例中,基板12之厚度之較佳範圍係位於5〇至35〇 以足夠吸收施加於半導體晶片丨上應力,以及施加於 “導體晶片1與基板1 2間之連接部分之應力。 、另一方面,半導體裝置之實施例之形成:由鍍製層所 組成之配線1 4形成於基板1 2上,與貫通口丨2中之。層丨5 一 體形成導體,以獲得高連接可靠度之具有半導體層。 另一方面’在圖2所示之半導體裝置之實施例中,連 接於印刷板110之銲錫突塊19被沿著箭頭B之方向拉引,以 $量印刷板11 0與作為外界電極之銲錫突塊丨9間之連接部 分之剝除強度(Peel strength)。因此,銲錫突塊19與印 刷板間之連接部分之剝除強度係位於14至18 kgf/cm之範 圍内。 529135 五、發明說明(18) ' ------ 另一方面,藉由圖9A至9H所顯示之羽 獲得之半導體裝置中,連接部分之剝卜二°的衣把方法所 16kgf/cm之範圍内。據此,與藉由習二,係位於12至 之半導體裝置之剝除強度相比較,所 J斤 實施例降低大剝除強度的殘留扭曲。如前所述,在戶"匕 之半導體裝置之貫,例中,銲錫突塊與印刷板間; 分之強度業已被改善。 & ^ 另-方面’在所顯示之實施例中,開口部分ιΐ2係 置於位於基板1 2上之配線1 4上’且銲錫突塊】9係設於開口 部分112。然而,如圖3中所示之半導體裝置,開口部 212可被設置於配線14上’以取代開口部分"2,該配線14 設於貫通口 11中。此外,如圖4所示半 圖3所示之,導體裝置,藉由提供一開 上,忒鍍製層没置於貫通口中,且設定貫通口 31之直徑大 於晶片電極1 0之寬度,可成功地吸收施加於半導體晶片盥 基板間之連接部分上之應力。再者,可降低晶片電極丨0之 阻值。應注意者為,在圖3與4中顯示保護層213盥313,直 省略於圖1與2中。 ~ 八 繼之’參照圖示,說明半導體裝置之製造方法盥 體裝置之另一實施例。 π 卜至5G係顯示依據本發明半導體裝置之製造方法之 ,二貫施例,圖6係顯示依據本發明之半導體裝置之第二 實施例,圖7係顯示依據本發明半導體裝置之製造方法之 第二貫施例之一製造步驟之平面圖,圖8係顯示依據本發As shown in FIG. 2, the range from the semiconductor wafer 1 to the adhesive ㈣. Two brush plates: 1; the width is located at about 35 0 _ to 650 # ^ ^ ^ /, the connection between the semiconductor chip 1 and the adhesive 1 3 = the thickness of the solder resist film 17 is located at about 50 to 350 The range of " m ^ and !! The thickness between the solder resist film 17 and the printed board 110 is about 3G. _. The connection surface between the film 17 and the conductor chip 1 and the adhesive 13 to the solder resistance, most of the visibility is occupied by the substrate 12. Therefore, the thickness from the connection surface of the semiconducting 胶 ΓΛ glue Λ Qi ΓΓ to the fresh tin resist film 17 becomes equal to the thickness of the substrate 12 on the shell. According to this, the thickness of the substrate 2 provided by the embodiment of the semiconductor device 2 is within the range of 50 to 35. In consideration of economic efficiency, the substrate 12 is within the range of 50 to 100. In the actual yoke example of the semiconductor device, the preferred range of the thickness of the substrate 12 is 50 to 35 to sufficiently absorb the stress applied to the semiconductor wafer, and to apply the "connection between the conductor wafer 1 and the substrate 12" Part of the stress. On the other hand, the embodiment of the semiconductor device is formed: a wiring 14 composed of a plating layer is formed on the substrate 12 and one of the through holes 2. The layer 5 forms a conductor as a whole to obtain a semiconductor layer with high connection reliability. On the other hand, in the embodiment of the semiconductor device shown in FIG. 2, the solder bump 19 connected to the printed board 110 is pulled in the direction of the arrow B, and the printed board 110 and the solder as an external electrode are printed in the amount of $. Peel strength of the connection part between the bumps and 9 pieces. Therefore, the peeling strength of the connection portion between the solder bump 19 and the printed board is in the range of 14 to 18 kgf / cm. 529135 V. Description of the invention (18) '------ On the other hand, in the semiconductor device obtained by the feathers shown in Figs. 9A to 9H, the connecting part is peeled at a temperature of 16 kgf / cm. Within range. Accordingly, compared with the peeling strength of the semiconductor device located at 12 to by Xier II, the embodiment reduces the residual distortion of the large peeling strength. As mentioned above, in the semiconductor device of household appliances, for example, the strength between the solder bump and the printed board has been improved. & ^ Another aspect: In the embodiment shown, the opening portion 2 is placed on the wiring 14 on the substrate 12 and the solder bump 9 is provided on the opening portion 112. However, as in the semiconductor device shown in FIG. 3, the opening portion 212 may be provided on the wiring 14 ′ instead of the opening portion 2, and the wiring 14 is provided in the through-hole 11. In addition, as shown in FIG. 4 and FIG. 3, the conductor device is provided with an opening, and the hafnium plating layer is not placed in the through hole, and the diameter of the through hole 31 is set to be greater than the width of the wafer electrode 10, which can Successfully absorbed the stress applied to the connection portion between the semiconductor wafer substrates. In addition, the resistance of the chip electrode 0 can be reduced. It should be noted that the protective layers 213 and 313 are shown in FIGS. 3 and 4, and are omitted in FIGS. 1 and 2. ~ 8 Followed on, another embodiment of a toilet device according to a method of manufacturing a semiconductor device will be described with reference to the drawings. π to 5G show the manufacturing method of the semiconductor device according to the present invention, which is a coherent embodiment. FIG. 6 shows the second embodiment of the semiconductor device according to the present invention, and FIG. 7 shows the manufacturing method of the semiconductor device according to the present invention. A plan view of a manufacturing step of the second embodiment, FIG. 8 shows

第22頁 529135 五、發明說明(19) 施例之一製造步驟之平 明半導體裝置之製造方法之第 面圖。 如圖5A至5請6中所示,依據本發明之半導體裝置之 第::施例係内建(bui 1 t-in)於一封裝中,例如B〇A(Bai i Π ΪΓ 球/ ^csp(Chlp Size Pac_,晶片 尺寸封裝)。所顯示之半導體裝置之實施例具有一扇入 構’其中一外界電極排列於半導體晶片表面之 m 了使半導體晶片1間填滿樹脂a之製 例實質上相同於,半導體裝置之製造^ 另一方面,在所顯示之實施例中,圖7顯 圓0之平面圖’該半導體晶圓上形成有貫通口U,直係夢 〇由上雷之射,所示之基板12而形成。在半導體晶圓 0上之基板12中’貝通σ11之形成速度約為每分鐘2〇〇〇〇 個。 另―方® ’在圖5G所示之切割外部輪靡(晶粒切割 00之表面上,在切割表面61與62之箭頭之方向上, 鑽石切割器或諸如此類者而切割,如圖8所示,從切= 面61 ΐ : ΐί表面6 2 ’半導體晶圓0被分割成個別的晶粒: 错前述之製程,使用依據本發明之半導體裝置 造方法之實施例’如圖6所示,可獲得未使樹脂16填入半衣 v體晶片1間之具有扇入(fan_in)結構之半導體裝置。Page 22 529135 V. Description of the invention (19) The first view of the manufacturing method of the semiconductor device in the manufacturing step of the embodiment. As shown in FIG. 5A to FIG. 5, the semiconductor device according to the present invention is: built in a package (bui 1 t-in) in a package, such as B0A (Bai i Π ΪΓ ball / ^ csp (Chlp Size Pac_, chip size package). The embodiment of the semiconductor device shown has a fan-in structure, in which one of the external electrodes is arranged on the surface of the semiconductor wafer m, so that the semiconductor wafer 1 is filled with resin a. Same as the manufacturing of a semiconductor device ^ On the other hand, in the embodiment shown, FIG. 7 shows a plan view of circle 0. 'The semiconductor wafer is formed with a through-hole U, which is directly related to the dream. The substrate 12 shown in FIG. 5 is formed on substrate 12 on semiconductor wafer 0 at a rate of about 2,000 per minute. The “Fang®” shown in FIG. 5G is popular. (On the surface of the crystal cutting 00, in the direction of the arrows of the cutting surfaces 61 and 62, a diamond cutter or the like is used to cut, as shown in FIG. 8, from the cutting = the surface 61 ΐ: ΐί surface 6 2 'semiconductor crystal Circle 0 is divided into individual grains: the process is incorrect, the use of A method of manufacturing a semiconductor device according to the embodiment 'shown in FIG. 6, the resin obtained is not half filled 16 v wafer coating of a semiconductor device having a fan (fan_in) structures.

第23頁 529135 五、發明說明(20) 如前所述’依據本發明之半導體裝置之製造方法,可 將基板之厚度製成足夠大,以使印刷板與半導體晶片間之 距離足夠大。因而,可充分吸收施加於半導體晶片上之基 板與晶片電極間之連接部分上之應力。因此可成功地避免 連接部分之破裂或斷開。因此,可改善半導體裝置之製造 率。再者,既然可修復半導體晶片之内部,以及位於半導 體晶片與印刷板間之部分,故半導體裝置可達成高保持能 力0 另一方面,藉由 外界電極之側邊上之 體晶片之侧邊上之貫 外界電極間之連接部 增加連接部分之連接 或斷開。因此可獲得 另一方面,依據 藉由T A B系統所製造 式’以重疊且連接重 複數個半導體晶片之 係藉由内部導線架接 之電極接合墊與基板 半導體晶片之電極接 相互接合。再者,既 片與印刷板間之部分 導體裝置。 依據本發明之半導體裝置,經由使在 貫通口之開口部分之寬度大於在半導 通口之開口部分之寬度,可使導體與 分之面積變大,以使連接阻值小,且 強度。藉此,可避免連接部分之破裂 高良率之半導體裝置。 本發明之半導體裝置之第一實施例係 用以提供複數條配線,藉由適當方 複形成的導體之配線導線架與對應於 電極之部分。詳細言之,半導體裝置 合系統所製造,其中在使半導體晶片 之内部導線架之對應部分重疊之後, 合墊與基板之内部導線架之對應部分 然半導體晶片之内部與位於半導體晶 可被修復,故可達成高保持能力之半Page 23 529135 V. Description of the invention (20) As mentioned above, according to the manufacturing method of the semiconductor device of the present invention, the thickness of the substrate can be made sufficiently large so that the distance between the printed board and the semiconductor wafer is sufficiently large. Therefore, the stress applied to the connection portion between the substrate and the wafer electrode on the semiconductor wafer can be sufficiently absorbed. Therefore, breakage or disconnection of the connecting portion can be successfully prevented. Therefore, the manufacturing rate of the semiconductor device can be improved. Furthermore, since the inside of the semiconductor wafer and the portion between the semiconductor wafer and the printed board can be repaired, the semiconductor device can achieve a high holding capacity. On the other hand, by the side of the body wafer on the side of the external electrode The connection part between the external electrodes increases the connection or disconnection of the connection part. Therefore, on the other hand, according to the manufacturing method of the TAB system, a plurality of semiconductor wafers are overlapped and connected, and the electrode pads connected to the substrate via the internal lead frame and the substrate semiconductor electrode are bonded to each other. Furthermore, a part of the conductor device between the existing sheet and the printed board. According to the semiconductor device of the present invention, by making the width of the opening portion in the through hole larger than the width of the opening portion in the semi-conductive opening, the area of the conductor and the component can be made larger, so that the connection resistance is small and the strength is small. Thereby, it is possible to avoid cracking of the connection portion of the semiconductor device with a high yield. A first embodiment of the semiconductor device of the present invention is a wiring lead frame for providing a plurality of wirings, a conductor formed by an appropriate method, and a portion corresponding to an electrode. In detail, the semiconductor device and the system are manufactured in which after the corresponding portions of the internal lead frame of the semiconductor wafer are overlapped, the corresponding portions of the bonding pad and the internal lead frame of the substrate can be repaired inside the semiconductor wafer and the semiconductor wafer. Therefore, half of the high holding capacity can be achieved

第24頁 529135 五、發明說明(21) 雖然業已參照例示用之實施例顯示與說明本發明,但 熟習此項技藝之人士應明瞭,得對本發明進行前述與各種 其他改變、省略、以及添加,而皆不偏離本發明之精神與 範圍。因而,本發明不應僅限於前述之特定的實施例,反 而包含所有可能的實施例,該可能的實施例皆可實施於申 請專利範圍所設定之特徵所包含之範圍與均等物中。Page 24 529135 V. Description of the invention (21) Although the present invention has been shown and described with reference to the examples for illustration, those skilled in the art should understand that the present invention may be subjected to the aforementioned and various other changes, omissions, and additions, Without departing from the spirit and scope of the present invention. Therefore, the present invention should not be limited to the specific embodiments described above, but includes all possible embodiments, and the possible embodiments can be implemented in the scope and equality included in the features set by the scope of the patent application.

第25頁 529135 圖式簡單說明 〔圖示之簡單說明〕 從本發明之較佳實施例之圖示,以及下文中之詳細說 明,將更充分明瞭本發明,然而,較佳實施例並非用以限 制本發明,僅係作為說明與了解之用。 圖示為: 圖1 A至1 G係顯示依據本發明半導體裝置之製造方法之 第一實施例; 圖2係顯示依據本發明之半導體裝置之第一實施例; 圖3係顯示依據本發明之半導體裝置之第一實施例之 一例子; 圖4係顯示依據本發明之半導體裝置之第一實施例之 另一例子; 圖5A至5G係顯示依據本發明半導體裝置之製造方法之 第二實施例; 圖6係顯示依據本發明之半導體裝置之第二實施例; 圖7係顯示依據本發明半導體裝置之製造方法之第二 實施例之一製造步驟之平面圖; 圖8係顯示依據本發明半導體裝置之製造方法之第二 實施例之一製造步驟之平面圖; 圖9A至9H係顯示半導體裝置之習知的製造方法之一例 子;以及 圖10A至10H係顯示半導體裝置之習知的製造方法之另 一例子 °Page 529135 Brief description of the drawings [Simplified description of the diagrams] The present invention will be more fully understood from the diagrams of the preferred embodiments of the present invention and the detailed description below, however, the preferred embodiments are not intended to The present invention is limited only for the purpose of illustration and understanding. The diagrams are: FIGS. 1A to 1G show a first embodiment of a method for manufacturing a semiconductor device according to the present invention; FIG. 2 shows a first embodiment of a semiconductor device according to the present invention; FIG. 3 shows a first embodiment according to the present invention An example of a first embodiment of a semiconductor device; FIG. 4 shows another example of a first embodiment of a semiconductor device according to the present invention; FIGS. 5A to 5G show a second embodiment of a method of manufacturing a semiconductor device according to the present invention 6 is a plan view showing a second embodiment of a semiconductor device according to the present invention; FIG. 7 is a plan view showing a manufacturing step of a second embodiment of a method for manufacturing a semiconductor device according to the present invention; FIG. 8 is a plan view showing a semiconductor device according to the present invention FIG. 9A to 9H show an example of a conventional manufacturing method of a semiconductor device; and FIGS. 10A to 10H show another example of a conventional manufacturing method of a semiconductor device An example °

第26頁 529135 圖式簡單說明 〔符號說明〕 1〜半導體晶片 10〜電極接合墊/晶片電極 11〜貫通口 1 2〜基板 13〜膠黏劑 1 4〜配線 1 5〜Cu層 1 6〜樹脂 1 7〜銲錫阻膜 18〜鍍製層 1 9〜銲錫突塊 11 0〜主板/印刷板 111〜阻膜 11 2〜開口部分 2 1 2〜開口部分 2 1 3〜保護層 3 1 3〜保護層 31〜貫通口 6 1〜切割表面 6 2〜切割表面 71〜貫通孔 72〜基板 7 3〜膠黏劑Page 26 529135 Brief description of drawings [Description of symbols] 1 to semiconductor wafer 10 to electrode bonding pads / wafer electrodes 11 to through holes 1 2 to substrate 13 to adhesive 1 4 to wiring 1 5 to Cu layer 1 6 to resin 1 7 ~ solder resist film 18 ~ plated layer 1 9 ~ solder bump 11 0 ~ motherboard / printing board 111 ~ resist film 11 2 ~ opening 2 1 2 ~ opening 2 1 3 ~ protective layer 3 1 3 ~ protection Layer 31 ~ through hole 6 1 ~ cutting surface 6 2 ~ cutting surface 71 ~ through hole 72 ~ substrate 7 3 ~ adhesive

第27頁 529135 圖式簡單說明 74 741 75 76 77 78 79 710 714 81 82 83 84 841 85 88 89 810 配線 導體 鍍製物 接合工具 銲錫球阻膜 鑛製物 銲錫突塊 印刷板 強化樹脂 貫通口 基板 樹脂 配線 銅猪 密封材料 鍍製層 銲錫突塊 印刷板Page 27 529135 Brief description of drawings 74 741 75 76 77 78 79 710 714 81 82 83 84 841 85 88 89 810 Wiring conductor plating material bonding tool solder ball resist film mineral solder bump printed board reinforced resin through hole substrate Resin wiring copper pig sealing material plated solder bump printed board

第28頁Page 28

Claims (1)

529135 _案號88121525_年月日__ 六、申請專利範圍 5. 如申請專利範圍第4項之半導體裝置,其中,該基板之 厚度係位於5 0至35 0 之範圍内。 6. 如申請專利範圍第4項之半導體裝置,其中,於基板之 一面上,保持複數半導體晶片,並於該半導體晶片間填入 樹脂。 7. 如申請專利範圍第4項之半導體裝置,其中,於與半導 體晶片之相反侧,於基板上具有與貫通口内之導體相連接 之外界電極,將此外界電極接合於印刷板上,其剝除強度 位於14至18 kgf/cm之範圍内。529135 _Case No. 88121525_Year Month Date__ VI. Patent Application Range 5. For the semiconductor device under patent application item 4, the thickness of the substrate is in the range of 50 to 35 0. 6. The semiconductor device according to item 4 of the patent application, wherein a plurality of semiconductor wafers are held on one side of the substrate, and a resin is filled between the semiconductor wafers. 7. For the semiconductor device according to item 4 of the patent application, wherein, on the side opposite to the semiconductor wafer, there is an outer boundary electrode connected to the conductor in the through hole on the substrate, and this outer electrode is bonded to the printed board, and the peeling The removal strength is in the range of 14 to 18 kgf / cm. 第30頁Page 30
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