TW529088B - Manufacturing method of stacked gate flash memory device - Google Patents

Abstract

A manufacturing method of stacked gate flash memory device comprises the following steps: providing a substrate; forming many stacked gates on the substrate, each stacked gate consisting of a first insulated layer, a first gate layer on the first insulated layer, a second insulated layer on the first gate layer, a second gate layer on the second insulated layer and a third insulated layer on the second gate layer; making many source/drain doped areas on the substrate among the stacked gates; forming spacers on the sidewalls of the stacked gates and filling a first conductive layer in the stacked gates spacing; making a forth insulated layer on the first conductive layer for being connected to the source doped area; depositing a second conductive layer that is connected to the first conductive layer above the drain doped area and is isolated from the first conductive layer above the source doped area by the forth insulated layer.

Description

529088

Note: The month t is related to a manufacturing method of stacking gate flash (跖 Γ: Tian), and more particularly to a method of manufacturing a stack memory flash memory device that can shorten the stack gate distance. Figure 8C of the Institute shows the method for manufacturing a flash memory device of Lu Zhidui Fengzha Gate Patent Application m & Among them, M times', ,, and = diagrams, and XB and xc diagrams are cross-sectional views along XX, and γγ in the XA diagram. Shi Qiqi = 9n As shown in Figures 1A, 1B & 1C, a silicon substrate 20 is provided, on which an oxide layer 21, a nitride layer 22, an oxide layer 23,

He 9 (1 :, and etch the deposition layers and silicon substrate 20 to form deep and silicon-based: middle and deep grooves 261 for shallow trench isolation (STI). Along the grooves 261 bis and: 1 wall A lining oxide layer 25 is formed, and an oxide layer 26 for insulation is filled in the groove 261. Next, as shown in Figs. 2A, 2B, and 2C, the nitride layer 24 and the oxide layer 23 are removed by an etching step. Since the oxide layer 23 is etched in the rest of the time, the layer 26 is also etched, so part of the oxide The sidewalls of layer 26 are removed at the same time. Thus, a stepped sidewall is formed on the cross section of the oxide layer 26 in the YY direction. Then, as shown in FIGS. 3A, 3B, and 3C, the etching step is used to remove the nitride layer 22 and the oxide layer 21 to form an exposed active region (the groove 262 on the surface of the active silicon substrate 20), thereby completing a ladder-like structure. A shallow trench isolation structure with oxidized reeds on the sidewalls. A Then, as shown in Figures 4A, 4B, and 4C, a two-gate oxide layer 27 is formed on the surface of the exposed silicon substrate 20. A polycrystalline silicon layer 28 is then deposited. The ladder-shaped sidewall of the oxide layer 26 causes the polycrystalline silicon layer 2 8 to be formed above the groove 2 6 2

^ 29088 «V. Description of the Invention (2) ---------- Depression of" V "shape. Next, as shown in Figures 5A, 5B, and R%, the remaining part is in the groove 262, which is not shown in the figure. The polycrystalline silicon layer 28 is etched back, and only the layer 28 has a "text contamination gate" function above the groove 262. Because the polycrystalline silicon has a v ″ -shaped depression, the result of the etch-back will then be as follows: 6A, B, and 20% / end 281. Then, remove part of the side wall to make more; Second, the oxide layer 26 is engraved on the surface of the polycrystalline stone layer 28, and the tip portion 281 is exposed. 30. It is used to control the closed-electrode opening; layer 29 'deposit-polycrystalline, Shixi layer section 282, so there is a depression Nie's voice in the middle of the gate of Xiyuyouxijing silicon layer 28. Opposite the three poles will form a protrusion 3 0 1. The stack: the recessed holes 302 and the two gate electrodes are etched 'to form recessed holes 3G2 and 303 exposing the surface of the silicon substrate 20 to judge each stack gate. Deaf 261 / / Λ As shown in Figures 7A, 7B, and 7C, the oxide layer 26 and the shallow isolation layer are formed-lining: J-layer 25 is etched so that the recessed holes 302 in the same row are connected / formed into an exposure path The groove 302 ′ on the surface of the silicon substrate 20. Using ions: 'in the groove 302' and the silicon substrate 20 at the bottom of the recess 303, respectively, a common source doped region 201, and a plurality of drain doped layers; and then a tempering (an n step, so that The impurities are diffused outward: under the floating gate 28. Finally, as shown in Figures 8A, 8B, and 8C, a dielectric layer 31 is deposited, and a dielectric layer is formed in the dielectric layer 31孔 311。 Hole 311. The metal layer 32 is deposited and used for the wires and plugs to make the same column, meaning-electrical connection.歹 "The doping of the hidden cell

529088 V. Description of the invention (3) However, in the above-mentioned manufacturing method of the stacked gate flash memory device, 'the reason for the distance between the two stacked gates is that the metal plug is used to capture the signal of the source and the drain. It is difficult to shorten due to the influence of the hole of the dielectric layer. At the same time, the drain voltage must be directly coupled from the drain region in the substrate to the floating gate, and both sides of the auxiliary drain region must be extended below the floating gate. Remembrance = Ϊ problem, ί invention provides-a method of stacked closed-pole flash memory I, W method, using polycrystalline silicon layer as a plug, can shorten the distance between the reactor I ", and do not need to expand the doped region The system to the floating gate is to provide a stacked closed-pole flash memory device door: including: the next step. Provide-substrate. One of the first interlayers on the first insulating layer is formed on the substrate, “two are located on the second insulating layer, and are located on the second insulating layer”; The third first gate layer above and a plurality of source and drain electrodes formed in the bottom: ㈣, the side wall of the intermediate electrode forms a gap wall. Today I pile the Fengzha layer. The doping interval with the source is filled with a -first-conductive insulating layer. Deposition-the second conductive layer is formed-the first conductive layer above the fourth region is continuously connected, the electrical layer and the first conductive layer above the non-doped doped region must be equal to the fourth insulating layer With the source, another object of the present invention is to provide a manufacturing method 'including the following steps. Raised; polar, flash memory equipment sequentially deposited-first-and second deposited layers. The first base layer on the base, a first deposited layer and

0503-6914TWF; TSMC2001-0760; Vincnet.ptd page 6 529088 5. Description of the invention (4): A first insulating layer deep in the substrate and a first groove in the substrate is formed. Remove the second tank. A side is formed to fill the insulating layer. The first deposition layer and the buildup layer are etched to expose the first first insulation layer-ladder-shaped sidewall, and the m insulation layer is moved, and the second groove of the substrate is exposed in the first. On this exposure-deposition layer, two insulating layers are formed. A first-gate layer is deposited and etched back, and two bottom surfaces form a first recessed portion and a tip portion of the first gate layer in the second groove and in the first gate layer. Each of the sides of the first insulating layer is etched to form a tip portion exposed *. On the surface of the first gate layer; forming a gate layer: A second gate layer is accumulated to fill the second groove. Xi two insulation layers. Shen: The fourth insulation layer. The second insulating layer is sequentially etched; the gate 1 layer is deposited, the second insulating layer, the first gate electrode layer, and the second gate-gate j: ·, the third plural number of =. The third grooves are formed on the two side walls of the third groove to the soil: column memory cells. In the -s- conductive layer. * Into the wall. The third groove is filled with this, so that the invention controls the idler and floating gate knowing part and recessed part, which is beneficial for the hot electrons to pass through the tip of the floating gate (when erasing ±) or by controlling Gate tunneling to floating gate (when writing): = poles are dry, expand the doped region of the drain to below the floating gate, 2: move, close to the floating gate to help control the generation of idler Attraction of hot electron transport ::: The difference in the region potential can be-erased only once-a memory cell essence and extremely doped. The following is a schematic illustration of a stack flash memory device according to the present invention.

529088 V. Description of the invention (5) An embodiment of the manufacturing method. Brief Description of the Drawings Figs. 1A to 8C show the structure of a conventional stacked gate flash memory device; Figs. 9A to 15C show a method for manufacturing the stacked gate flash memory device according to an embodiment of the present invention. [Explanation of symbols] 20, 40 ~ Shi Xi substrate; 2 0 1, 4 0 1 ~ Drain doped region; 2 0 2, 4 0 2 ~ Source doped region; 21, 23, 25, 26, 27, 29, 31, 41, 43, 45, 46, 47, 49, 51, 55 ~ 4 layers of oxygen; 28, 48 ~ floating gates; 30, 50 ~ control gates; 3 ~ 2 metal layers; 22, 24, 42, 44, 52 ~ nitride layers; 261 > 262, 461, 462 ~ grooves;

302, 303, 502, 503 to female L 281, 481 to floating gate tip Φ 282, 481 to floating gate recess 3 0 1, 5 0 1 to control gate protrusion; 3 11 to Layer holes; 5 3 ~ spacer wall; 5 4,5 6 ~ polycrystalline stone layer.

0503-6914TWF; TSMC2001-0760: Vincnet.ptd Page 8 529088 V. Description of the Invention (6) " Embodiment 9A ~ 1 5C shows the manufacturing of a stacked gate flash memory device in an embodiment of the present invention method. Among them, X A diagram is a top view, and X b and X ◦ diagrams are cross-sectional views along XX ′ and γγ, in XA diagram. First, as shown in FIGS. 9A, 9B, and 9C, a silicon substrate 40 is provided, and an oxide layer 41, a nitride layer 42, an oxide layer 43, and a nitride layer 44 are sequentially deposited on the stone evening substrate 40, and then etched. The deposited layers and the silicon substrate 40 form deep grooves 461 in the deep and stone substrate 40 as shallow trench isolation (STI). A lining oxide layer 45 is formed along the bottom and side walls of the groove 461, and the insulating oxide layer 46 is filled in the groove 461. Next, as shown in FIGS. 10A, 10B, and 10C, the etching step is used to move the nitride layer 44 and the oxide layer 43. When the oxide layer 43 is etched, the oxide layer 46 is also etched, so part of the oxide is oxidized. The sidewalls of layer 46 are removed at the same time. In this way, the oxide layer 46 is formed with a stepped sidewall on a cross section in the YY direction. Then, as shown in FIGS. 11A, 11B, and 11C, the etched layer 42 and the oxide layer 41 are removed by an etching step to form a recess 462 that exposes the surface of the active area silicon substrate 40 to complete a Shallow trench isolation structure with ladder-like sidewall oxide layer. Further, as shown in Figs. 12A, 12B, and 12C, a gate oxide layer 47 is formed on the surface of the exposed silicon substrate. A polycrystalline silicon layer 48 is deposited. Due to the stepped sidewalls of the oxide layer 46, the polycrystalline silicon layer 48 forms a "V" shaped depression over the groove 462. Next, as shown in FIGS. 13A, 13B, and 13C, the polycrystalline silicon layer 48 is etched back

529088

0503-6914TW; TSMC2001-0760; Vincnet.ptd Page 10 ^^ 9088 L. Description of the invention (8)-Intermediate pole, therefore, the drain is dominated by this, and the in impurity & will not extend below the floating gate. . For example, the width between stacking poles can be as follows: ° The area of Jiyi cell has been reduced. Although the present invention has been disclosed in a preferred embodiment, such as 纟, but it is not invented by God / Ϊ t, any person skilled in this art can be used without departing from the fine armor and stem of the present invention. The changes and retouchings of this #turning # 翻 保 笳 m A, a β 』1 卞 II Hui, therefore, the Baomanwei of the present invention shall be subject to the definition of the scope of the attached patent.

0503-6914TW; TSMC2001-0760; Vincnet.ptd $ 11 pages

Claims (1)

529088 VI. Steps for applying patent scope 丨 ·· A method of manufacturing a stacked gate flash memory device, providing a substrate; forming a plurality of stacked gates on the substrate, each stacked today; absolutely no sound T at the first One of the first gates on the insulation layer, the first, second and third gates, the third and second gates on the second and third gates, and the stacked gates A plurality of gaps formed in the substrate form a gap wall on the side walls of the stacked gates; a first conductive layer is filled between the stacked gates; the first connection layer connected to the source doped region -"Layer-shaped insulating layer; and > a second conductive layer is connected to the first conductive layer of the drain side, and the fourth insulating layer is connected to the first conductive layer above the region A conductive layer is insulated. 2. A method for manufacturing a stacked gate flash memory device, including the following steps: including the following electrodes including a layer on the edge layer; a source electrode and a source electrode on a fourth doped region; The inclusions include the following: providing a substrate; sequentially depositing a substrate on the substrate / And a second deposited layer; forming a deep and first groove in the substrate in the second and first deposited layers and the substrate; forming a first insulating layer filling the first groove; removing The second deposited layer exposes the sidewall of the first insulating layer; 529088 6. The scope of the patent application I worms the first deposition layer and the first insulation layer, and forms a ladder-shaped side wall on the first insulation layer, and removes the first deposition layer to form an exposed groove; A second insulating layer is formed on the exposed surface of the substrate; the first gate layer is left over so that the first gate layer is located on the second and second sides of the first gate layer respectively forming a recessed base substrate Depositing one or two grooves and the tip portion in the exposure; etching the first-deposited groove in the first-deposited sequence in the first-deposited area; in the doped area, and in the first-deposited area 3. The etched area should be etched by the manufacturer. 4. If the first insulating layer is applied, the tip of the first gate layer is exposed; a third insulating layer is formed on the surface of a gate layer; the second gate layer fills the second groove; _ two gates A fourth insulating layer is deposited on the layer; the fourth insulating layer, the second gate layer, the third insulating layer, and the second insulating layer are etched to form a plurality of third grooves exposed to expose the substrate. A drain and a source are formed in the substrate to form at least one row of memory cells; a sidewall is formed on both side walls of the three grooves; and a first conductive layer is filled in the three grooves. The stacked gate flash memory mounting method described in item 2 of the patent, further includes the following steps: a first insulating layer to communicate the third grooves; and the substrate exposed by the connected third grooves In the formation of the source, the stacked gate flash memory device described in item 3 of the patent scope is incorporated. 0503-6914TWF; TSMC2001-0760; Vincnet.ptd Page 13 529088 6. The manufacturing method of the patent application scope, which further includes the following steps: forming a first on the first conductive layer connected to the source doped region Five insulating layers; and depositing a second conductive layer, the second conductive layer is connected to the first conductive layer above the drain doped region, and through the fifth insulating layer and the first conductive layer above the source doped region A conductive layer is insulated. 5. The method for manufacturing a stacked gate flash memory device according to item 2 of the scope of patent application, wherein the conductive layer is a polycrystalline silicon layer. 6. The manufacturing method of the stacked gate flash memory device according to item 2 of the scope of patent application, wherein the substrate is a silicon substrate. 7. The method for manufacturing a stacked gate flash memory device according to item 2 of the scope of patent application, wherein the first and second gate layers are polycrystalline silicon layers. 8. The method for manufacturing a stacked gate flash memory device as described in item 2 of the patent application scope, wherein the first deposited layer is an oxide layer. 9. The method for manufacturing a stacked gate flash memory device according to item 2 of the scope of patent application, wherein the second deposited layer is a nitride layer. 10. The method for manufacturing a stacked gate flash memory device according to item 2 of the scope of the patent application, wherein the first, second and third insulating layers are oxide layers. 11. The method for manufacturing a stacked gate flash memory device according to item 2 of the scope of the patent application, wherein the fourth insulating layer is an oxide layer and a nitride layer. 0503-6914TWF; TSMC2001-0760; Vincnet.ptd page 14