TW577115B - Split gate flash memory having independent erasing gate and its manufacturing method - Google Patents
Split gate flash memory having independent erasing gate and its manufacturing method Download PDFInfo
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577115577115
發明領域: 本發明係有關於一種分離蘭梅★ ^〗· 記憶體及其製造方法,式(Spllt _e)快閃 、衣仏乃床,特別是有關於一 極之分離閘極式快閃記憶體及其製造方法除閘 相關技術說明: 之製ΐ Ϊ Ϊ合It至1^圖說明一傳統分離閘極快閃記憶體 美底1 0卜把&古,凊參照第1 Α圖,提供一矽基底1 0,此 ϊΐ ϋί 一閘極氧化層11、一複晶石夕層12及-氮化 #參照第⑺圖,利用微影蝕刻步驟在氮 數開口131,並使開口131底部之複晶梦 層1 2亦被餘刻而產生凹陷。 接下來,請參照第1C圖,在氮化矽層丨3上沉積一 矽層1 4並填滿開口丨3 i。接著回蝕刻氧化矽層丨4至露出氮 化石夕層1 3而僅留下填滿開口丨31之氧化矽層丨4。 接下來,請參照第…圖,使用一光阻圖案層15作為罩 幕、,對氮化矽層1 3及複晶矽層丨2進行蝕刻而形成開口丨32 ,並露出開口 1 32底部之閘極氧化層丨丨。接著實施一離子 佈值以在開口132下方之矽基底10中形成一源極摻雜區 101 。 接下來,請參照第1 E圖,移除光阻圖案層丨5。接著於 開口 1 32侧壁形成一由氧化矽層所構成之絕緣間隙壁 (spacer ) 16。然後,於氮化矽層13及氧化矽層14上再沉 積一複晶矽層1 7並填滿開口 1 3 2,並回蝕刻複晶矽層1 7至 露出氮化矽層1 3與氧化矽層1 4而留下填滿開口 1 3 2之複晶Field of the Invention: The present invention relates to a separate Lanmei ★ ^〗 · memory and its manufacturing method, the formula (Spllt_e) flash, clothing is a bed, and in particular, the one-pole split gate flash memory Relevant technical description of the gate and its manufacturing method: The system ΐ Ϊ It It ^ 图 It 闸 至 至 至 至 至 至 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 1 说明A silicon substrate 10, a gate oxide layer 11, a polycrystalline stone layer 12 and -nitriding. Referring to the first figure, the lithography etching step is used to open the nitrogen number 131 and make the bottom of the opening 131 The polycrystalline dream layer 12 is also recessed after being etched. Next, referring to FIG. 1C, a silicon layer 14 is deposited on the silicon nitride layer 丨 3 and fills the opening 丨 3i. Then, the silicon oxide layer 4 is etched back to expose the nitrided silicon layer 13 and only the silicon oxide layer 4 filling the opening 31 is left. Next, referring to the figure, using a photoresist pattern layer 15 as a mask, the silicon nitride layer 13 and the polycrystalline silicon layer 丨 2 are etched to form an opening 丨 32, and the bottom of the opening 1 32 is exposed. Gate oxide layer 丨 丨. Next, an ion distribution is performed to form a source doped region 101 in the silicon substrate 10 under the opening 132. Next, referring to FIG. 1E, the photoresist pattern layer 5 is removed. An insulating spacer 16 made of a silicon oxide layer is formed on the side wall of the opening 1 32. Then, a polycrystalline silicon layer 17 is deposited on the silicon nitride layer 13 and the silicon oxide layer 14 to fill the opening 1 3 2, and the polycrystalline silicon layer 17 is etched back to expose the silicon nitride layer 13 and the oxide. The silicon layer 1 4 leaves the compound crystal filling the opening 1 3 2
577115 五、發明說明(2) 矽層1 7。 接下來,請參照第丨F圖所示,對複晶矽層丨7進行氧化 而在複晶矽層1 7上形成氧化矽層1 8,再使用氧化矽層i 4, 1 8為罩幕進行姓刻,使複晶矽層1 7兩側之氮化矽層1 3、複 晶石夕層1 2及閘極氧化層丨丨被移除而露出矽基底丨〇。 接下來,請參照第1G圖所示,形成一附著於可見沉積 層表面與側壁之氧化矽層丨9,再沉積一附著於氧化矽層i 9 表面之複晶矽層20。接著,請參照第1H圖,對複晶矽^2〇 進行餘刻,以形成間隙壁狀之複晶矽層2〇來做為字元&之 最後’请參照第11圖,沉積一介電層2 1,並餘刻介電 層21及氧化矽層19而形成露出矽基底1〇之接觸窗 h〇le)211 ,接著實施離子佈值,以在接觸窗2ιι下方之矽 基底ίο中形成一汲極摻雜區102。然後,於介電層21上沉 $ 一金屬層22,並填滿接觸窗21ι以做為位元線之接觸插 富 化石々® Q述快閃記憶體進行抹除時,仪於石夕基底1 0上的^ 3 4層12㈣之氧切層19之厚度“要較薄,以辦 “ 3 Lit:方面,當進行寫广時,位於複晶石夕層;〗 。同樣地,a^厚度c需要較薄,以利於熱電子注入 快電流。然而,上述 又限於母處之氧化矽層丨9具有一樣的577115 V. Description of the invention (2) Silicon layer 17. Next, as shown in Figure 丨 F, the polycrystalline silicon layer 丨 7 is oxidized to form a silicon oxide layer 18 on the polycrystalline silicon layer 17, and then the silicon oxide layers i 4 and 18 are used as a mask. Carry out the last name engraving so that the silicon nitride layer 1 3 on both sides of the polycrystalline silicon layer 17 and the polycrystalline silicon layer 12 and the gate oxide layer are removed to expose the silicon substrate. Next, referring to FIG. 1G, a silicon oxide layer 9 is formed on the surface and sidewalls of the visible deposition layer, and a polycrystalline silicon layer 20 is deposited on the surface of the silicon oxide layer i 9. Next, referring to FIG. 1H, the polycrystalline silicon ^ 20 is etched to form a gap-shaped polycrystalline silicon layer 20 as a character & Finally, please refer to FIG. 11 to deposit a dielectric The electrical layer 21 and the dielectric layer 21 and the silicon oxide layer 19 are etched to form a contact window 211) that exposes the silicon substrate 10, and then an ionic layout is performed to place the silicon substrate under the contact window 2m. A drain doped region 102 is formed. Then, a metal layer 22 is sunk on the dielectric layer 21, and the contact window 21m is filled as a contact line of the bit line to insert the fossil-rich Fossil® Q flash memory for erasing. The thickness of the ^ 3 4 layer 12 氧 oxygen cut layer 19 on 10 is "to be thinner to handle" 3 Lit: In terms of writing, it is located in the polycrystalline stone layer;〗. Similarly, the thickness a and thickness c need to be thin to facilitate hot electron injection with fast current. However, the above is limited to the silicon oxide layer at the mother place. 9 has the same
577115 五、發明說明(3) 厚度(a=b=c) 狀態之需求。 發明概述: 有鑑於此, 閘極之分離閘極 ’以有效避免在 本發明之另 分離閘極式快閃 增加抹除、寫入 根據上述之 之分離閘極式快 ’因此無法同時兼顧抹除、寫入及讀 取 本發明 式快閃 第一摻雜區及一 上,且與第一摻 導電層下半部側 第一絕緣層,設 置閘極側壁,且 壁,設置於控制 成一開口; 一穿 ,設置於開口内 ;一第二絕緣層 絕緣層 據上述 及 又根 極之分離閘極式 提供一基底 進行高 一目的 記憶體 及讀取 目的, 閃記憶 第二摻 雜區電 壁,且 置於浮 分別與 閘極上 隧氧化 ,·一第 ,設置 ,設置 之目的 快閃記 ’基底 之目的 記憶體 壓抹除 在於提 ’其利 之效能 本發明 體,包 雜區; 性接觸 分別與 置閘極 浮置閘 ,且與 層,形 在於提 ’其藉 時發生 供一種 用不同 供一種 由一獨 電壓崩 具有獨 的閘極 上;一 極及基 第一絕 成於開 二導電層,電 於抹除閘極及 於第一導電層 明提供 製造方 種具有 基底, 導電層 置閘極 電層及 控制閘 底絕緣 緣層間 口内壁 性連接 該控制 具有獨立抹除 立之抹除電壓 潰。 立抹除閘極之 氧化層厚度來 除閘極 具有一 於基底 於第一 緣;— :置於浮 …緣間隙 之間形 除閘極 摻雜區 間;以 ,本發 憶體之 中具有 第 上。 一種具 法,包 摻雜區 有獨立抹除閘 括下列步驟: ,第一摻雜區 0503-8056TW(N) ; TSMC2002-0083 ; SPIN.ptd 第6頁 577115577115 V. Description of the invention (3) Requirements for thickness (a = b = c) status. Summary of the invention: In view of this, the separation of the gates of the gates is effective to avoid the addition of erasing and flashing of the separate gate-type flashes of the present invention, so that the erasing of the gate-types of the gate-separating gates cannot be performed simultaneously. , Write and read the first fast doped region and the first doped region of the present invention, and the first insulating layer on the lower half side of the first doped conductive layer, a gate sidewall is provided, and the wall is arranged to be controlled into an opening; A penetrating, disposed in the opening; a second insulating layer, an insulating layer, according to the above and the separated gate electrode type, provides a substrate for high-order memory and reading purposes, flash memory of the second doped region electrical wall, And placed on the floating and gate oxidation on the gate separately, the first, set, set the purpose of flash memory, the purpose of the memory pressure erasure is to improve the effectiveness of its benefits, the body of the invention, inclusion zone; sexual contact and placement The gate is floating, and the layer is in the form of “the borrowing occurs when one is used, the other is different, the one is provided by a single voltage and has a unique gate; the first pole and the base are first formed in the second. Electrical layer, electrically wipe the gate and provide a substrate on the first conductive layer. The conductive layer is connected to the gate and the bottom of the insulation edge of the gate bottom is connected to the inner wall of the gate. In addition to voltage collapse. The thickness of the gate oxide layer is removed by erasing the gate electrode. The gate electrode has a first edge on the base;-: placed between the floating ... edge gaps to remove the gate doping interval; on. A method comprising the independent erasing gate of the doped region includes the following steps:, the first doped region 0503-8056TW (N); TSMC2002-0083; SPIN.ptd page 6 577115
一第一絕緣層 及一第二 上依序 層側壁 閘極分 第一絕 層,其 導電層 層以形 ;在控 雜區上 層以作 制閘極 較佳實 形成有一第一 依序形成有一 別與第一導電 緣層及第二絕 中第二導電層 之側壁形成一 成一開口,其 制閘極;在開 制閘極外側之 方形成一接觸 為位元線。再 之間形成一第 施例之詳細說 導電層及 浮置閘極 層及基底 緣層之表 分別與基 絕緣間隙 中開口下 口内形成 基底中形 窗;以及 者,上述 二絕緣層 明: 絕緣; 面上順 底及浮 壁;非 方所殘 一穿隧 成一第 在接處 方法更 之步驟 絕緣層 在基底、 應性形成 置閘極絕 等向性餘 留之第二 氧化層及 二摻雜區 窗内填入 包括在抹 且第一導電 ,其中浮置 浮置閘極、 一第二導電 緣;在第二 刻第二導電 導電層係作 一抹除閘極 ,在第二推 一第三導電 除閘極及控 以下配合第2 Α到2L圖說明本發明一實施例之具有獨立 除閘極之製造方法。首先,請參照第2A圖,提供一基底 ’例如一半導體基底,接著在基底3〇上依序形成一氧化 矽層32、一複晶矽層34、一氮化矽層及一光阻圖案層38。 其中光阻圖案層38具有複數開口 381。 _接下來,請參照第2B圖,以光阻圖案層38為罩幕,蝕 刻氮化矽層3 6而形成複數開口 3 6 1,並使開口 3 6 1底部之複 晶矽層34被蝕刻到而產生凹陷。 一接下來,請參照第2 C圖,剝除光阻圖案層3 8。接著, 在氮化矽層36形成一氧化矽層4〇並填滿開口36ι。之後, 回餘刻氧化矽層4 0至露出氮化矽層3 6而僅留下填滿開口A first insulation layer and a second upper sequential layer side wall gate are divided into a first insulating layer, the conductive layer of which is shaped; the upper layer of the impurity-controlling area is preferably formed as a gate electrode, and is formed in a first sequential order Do not form an opening with the side wall of the first conductive edge layer and the second conductive second conductive layer to make a gate electrode; form a contact as a bit line on the outside of the gate electrode. Then, a detailed description of the first embodiment is formed between the surface of the conductive layer, the floating gate layer, and the base edge layer, respectively, and a base-shaped window is formed inside the opening in the base insulation gap; The bottom surface and the floating wall on the surface; the remaining one is tunneled to form a first step in the connection method. The insulating layer is on the substrate, and the second oxide layer and the doped isotropic layer are formed. The miscellaneous area window is filled with the first conductive layer, in which the floating gate electrode and a second conductive edge are floating; in the second moment, the second conductive layer is used as a wipe gate electrode, and the second conductive layer The three-conductor gate-eliminating electrode and the following control are shown in FIGS. 2A to 2L to illustrate a manufacturing method with independent gate-eliminating electrodes according to an embodiment of the present invention. First, referring to FIG. 2A, a substrate such as a semiconductor substrate is provided, and then a silicon oxide layer 32, a polycrystalline silicon layer 34, a silicon nitride layer, and a photoresist pattern layer are sequentially formed on the substrate 30. 38. The photoresist pattern layer 38 has a plurality of openings 381. _Next, please refer to FIG. 2B, with the photoresist pattern layer 38 as a mask, the silicon nitride layer 36 is etched to form a plurality of openings 3 6 1, and the polycrystalline silicon layer 34 at the bottom of the opening 3 6 1 is etched. Then a depression occurs. First, referring to FIG. 2C, the photoresist pattern layer 38 is removed. Next, a silicon oxide layer 40 is formed on the silicon nitride layer 36 and fills the opening 36m. After that, the silicon oxide layer 40 is etched back to the silicon nitride layer 36 to be exposed, leaving only the filled opening.
0503-8056TWF(N) ; TSMC2002-0083 ; SPIN.ptd0503-8056TWF (N); TSMC2002-0083; SPIN.ptd
577115 五、發明說明(5) " ' --- 361之氧化矽層40。 ,下來,请參照第2d圖,使用一光阻圖案層42作為罩 ,二=氮化矽層36及複晶矽層34進行蝕刻而形成開口421 :路出開口 42 1底部之氧化矽層3 2。接著實施一離子佈 乂在開口 421下方之基底30中形成一源極摻雜區3〇1。 接下來,請參照第2E圖,剝除光阻圖荦層42。接著, :擇性地實施一之退火(annealing)處理步曰驟,:度者約 至J 8 0 〇 c,以加強源極摻雜區3 〇 1之側向擴散。之後, 利用習知形成間隙壁之方法,在開口421内壁形成一由氧 化矽層所構成之間隙壁44,其厚度約400到5〇〇埃,同時, 去除開口421底部之氧化矽層32。接著,在氮化矽層36及 氧化矽層40上沉積一複晶矽層46,並填滿開口421而與源 極摻雜區3 〇 1電性接觸。隨後,回姓刻複晶矽層4 6至露出 氮化矽層36及氧化矽層40而留下開口 421中的複晶矽層 46,以作為源極線。 曰 接下來’請參照第2F圖,對作為源極線之複晶矽層46 進行熱氧化以在複晶矽層4 6上形成厚度約1 5 〇到2 5 0埃之氧 化矽層48。接著,以氧化矽層40, 48作為罩幕來進行蝕刻 ’使複晶矽層46兩側之氮化矽層36、複晶矽層34及氧化矽 層32被移除而形成開口 4〇1並露出基底3〇。其中留下的複 晶石夕層34 (即,位於源極線46下半部側壁)係作為浮置閉 極0 接下來’請參照第2 G圖,在露出的基底3 0、浮置間極 34及氧化矽層4〇, 48表面上依序順應性形成一氧化矽層5〇577115 V. Description of the invention (5) " '--- 361 silicon oxide layer 40. Next, please refer to Figure 2d, using a photoresist pattern layer 42 as a cover, two = a silicon nitride layer 36 and a polycrystalline silicon layer 34 to etch to form an opening 421: a way out of the opening 42 1 a silicon oxide layer 3 at the bottom 2. Next, an ion cloth is implemented to form a source doped region 301 in the substrate 30 below the opening 421. Next, referring to FIG. 2E, the photoresist layer 剥 is removed. Then, an annealing treatment step is selectively performed, and the degree is about J 8 0 c, so as to enhance the lateral diffusion of the source doped region 3 01. Then, a conventional method of forming a spacer wall is used to form a spacer wall 44 made of a silicon oxide layer on the inner wall of the opening 421, with a thickness of about 400 to 500 angstroms. At the same time, the silicon oxide layer 32 at the bottom of the opening 421 is removed. Next, a polycrystalline silicon layer 46 is deposited on the silicon nitride layer 36 and the silicon oxide layer 40, and fills the opening 421 to be in electrical contact with the source doped region 301. Subsequently, the polycrystalline silicon layer 46 is etched back to the exposed silicon nitride layer 36 and the silicon oxide layer 40, leaving the polycrystalline silicon layer 46 in the opening 421 as the source line. Next, referring to FIG. 2F, the polycrystalline silicon layer 46 as a source line is thermally oxidized to form a silicon oxide layer 48 having a thickness of about 150 to 250 angstroms on the polycrystalline silicon layer 46. Then, the silicon oxide layers 40 and 48 are used as a mask to perform etching, so that the silicon nitride layer 36, the polycrystalline silicon layer 34, and the silicon oxide layer 32 on both sides of the polycrystalline silicon layer 46 are removed to form an opening 401. And the substrate 30 is exposed. The polycrystalline spar layer 34 (that is, located on the lower side wall of the source line 46) is used as the floating closed electrode 0. Next, please refer to FIG. 2G, between the exposed substrate 30 and the floating layer. The electrode 34 and the silicon oxide layer 40, 48 are sequentially and compliantly formed on the surface of the silicon oxide layer 50.
577115 月 曰 修正 91112399 五、發明說明(7) 2 J圖所示。 接:來,請參照第21(圖,去除開口4〇1底部之 曰 以路出基底3 〇。接著實施一離+德# v + 夕 3〇 (即,栌制門抓佈值以在露出的基底 302, 成-金屬層:介電声j層:2/並藉由微影蝕刻步驟而構 且在沒極摻二 yer,dielectric’ ild), 2二在介電層62上沉積1金接屬觸:二1例::金照: ί 1 ΐ "30i ^ ^ ^ ^: 閘極式快閃記憶體之製造:明之具有獨立抹除閘極之分離 猫二地’請參照第2L圖,其繪示出根據本發明之呈有 獨立J =極之分離閑極式快閃記憶體之 月匕: 34= 二;$晶:層46、一氧化彻、-浮置Li 穿隨氧化开58 S ϋ &制閘極52、一絕緣間隙壁54、一 =0中且:閘極6〇、一氮化石夕層56及金屬層“ 複晶;層“I置雜= 一及-汲極摻雜區…。 區301電性接觸。'、、/'置-n # q 源極線而與源極摻雜 卷日茲山 4設置於複晶石夕層46下半部侧 :3〇i:i石夕層32及間隙壁44分別與複晶石夕㈣及基 二置二石夕層48設置於複晶石夕層詞上,且氧化石夕層 、孚Ϊ門桎二::上。作為字元線之控制閘極52設置於 汙置閘極3 4側壁,日莊出氧儿a a r n m ^ ^ 9虱化矽層50而分別與浮置閘極34 及基底30 I緣。絕緣間隙壁54設置於控制閘極,且盘577115 Month Revision 91112399 V. Description of the invention (7) 2 J Figure. Next: Come, please refer to Figure 21 (figure, remove the bottom of the opening 401, and the way out of the base 3 〇. Then implement a departure + German # v + Xi 30) (that is, the value of the door grabbing cloth to expose the The substrate 302 is formed by a metal layer: a dielectric acoustic j layer: 2 / and constructed by a lithographic etching step and doped with a second electrode (dielectric 'ild), 22 and a gold layer is deposited on the dielectric layer 62 Contact: 2 Example 1: Jinzhao: ί 1 ΐ " 30i ^ ^ ^ ^: Manufacture of gate-type flash memory: Mingzhi has separate cat two places with independent erasing gate 'Please refer to Section 2L Figure, which depicts a separate flash memory with independent J = pole according to the present invention: 34 = two; $ crystal: layer 46, monolithic oxide, -floating Li penetrating oxidation Open 58 S ϋ & gate 52, an insulation barrier 54, one = 0 and: gate 60, a nitride layer 56 and a metal layer "complex; layer" I doped = one and- The drain-doped region ... is in electrical contact with the region 301. ',, /' 置 -n # q The source line and the source-doped coil Rizishan 4 are disposed on the lower half side of the polycrystalline stone layer 46: 30i: i The stone evening layer 32 and the spacer 44 are respectively The second stone evening layer 48 is provided on the polycrystalline stone evening layer, and the oxide stone evening layer and Fusuomen Temple 2 :: are on. The control gate 52 as a character line is disposed on the side wall of the dirty gate 34. Nizhuang produces oxygen aarnm ^ ^ 9 silicon layer 50 and the floating gate 34 and the base 30 I edge respectively. The insulating gap 54 is provided on the control gate, and the disk
0503-8056TWFl(N);TSMC2002.0083.ptc ,矽層4"^^之間形成開口 541。穿隨氧化層58形、0503-8056TWFl (N); TSMC2002.0083.ptc, an opening 541 is formed between the silicon layer 4 " ^^. Pass through the oxide layer 58 shape,
第10頁 577115 j號9ηι乃QQ 五、發明說明(8) __ 成於開口 541内壁,且技叭P 矽層56及氧化矽層55嗖置除二極60設置於開口541内。氮化 間,以作為兩閘極6/於抹除閘極6〇及控制極52之 Μ厚度在2〇__的^間之/緣插塞,其中氮化石夕層 電性連接於沒極摻雜區3〇2為屬層64_’例如銅金屬層, 層間介電層(叫62而與= 且藉由金屬 化層厚度a L 間極)52,且控制閉極52之氧 ^ 田進仃抹除時, 萚 及絕緣插塞56來解決電^ 猎由獨立的㈣閘極60 :穿曝_,而提;:::;。,:=由;程控 寫入或讀取時時,同樣可藉由製程杵面,虽進行 度a,及c’而提高寫入及讀取之效能。二甲本乳化層50的厚 雖然本發明已以較佳實施例揭露如 限定本發明,任何熟習此項技藝者,;·,、、、其並非用以 神和範圍内,當可作更動與潤^,因此太f離本發明之精 當視後附之申請專利範圍所界定者為準本毛明之保護範圍 曰 修正 0503-8056TWF1 (N); TSMC2002-0083. pt c 第11頁 577115 圖式簡單說明 為讓本發明之上述目的、特徵和優點能更明顯易懂, 下文特舉較佳實施例,並配合所附圖式,作詳細說明如 下: 第1 A到1 I圖係繪示出傳統分離閘極式快閃記憶體之製 造方法剖面圖。 第2 A到2L圖係繪示出根據本發明實施例之分離閘極式 快閃記憶體之製造方法剖面圖。 [符號說明] 10、30〜基底; 11〜閘極氧化層; 12、 17、20、34、46、52、60〜複晶石夕層; 13、 36、56〜氮化石夕層; 14 、1« 、19 、32 、40 、48 、50 、55 、58〜氧化石夕層; 15、 38、42〜光阻圖案層; 16、 44、54〜間隙壁; 2 1、6 2〜介電層; 22、64〜金屬層; 1 0 1、3 0 1〜源極摻雜區; 102、302〜汲極摻雜區; 131、132、361、381、401、421、54卜開口; 211、621〜接觸窗。Page 10 577115 j number 9ηι is QQ V. Description of the invention (8) __ is formed on the inner wall of the opening 541, and the silicon P layer 56 and the silicon oxide layer 55 are disposed in the opening 541. Nitriding is used as the edge plug between the two gate electrodes 6 / the erase gate 60 and the control electrode 52 with a thickness of 20 mm, and the nitride layer is electrically connected to the electrode The doped region 30 is a metal layer 64_ ', such as a copper metal layer, an interlayer dielectric layer (called 62 and = and by the thickness of the metallization layer a L interpole) 52, and controls the oxygen of the closed electrode 52 ^ Tian Jin仃 When erasing, 萚 and the insulation plug 56 are used to solve the electric problem. ^ Hunting by the independent ㈣ gate electrode 60: through exposure, and mention; :::;. , ==; Program control When writing or reading, the performance of writing and reading can also be improved by the process of the pestle surface, although the degrees a and c 'are performed. Although the thickness of the dimethyl ester emulsion layer 50 is thick, although the present invention has been disclosed in a preferred embodiment, anyone who is familiar with the art, such as limiting the present invention, is not intended to be used within the scope of God. ^^ Therefore, too far from the essence of the present invention as defined by the scope of the attached patent application shall be the scope of Maoming's protection. Amendment 0503-8056TWF1 (N); TSMC2002-0083. Pt c page 11577115 Schematic In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a detailed description is given below with reference to the preferred embodiments and the accompanying drawings, as follows: Figures 1A to 1I are illustrated A cross-sectional view of a traditional manufacturing method of a gate-type flash memory. 2A to 2L are cross-sectional views showing a method for manufacturing a split gate flash memory according to an embodiment of the present invention. [Symbol description] 10, 30 ~ substrate; 11 ~ gate oxide layer; 12, 17, 20, 34, 46, 52, 60 ~ polycrystalline stone layer; 13, 36, 56 ~ nitride stone layer; 14, 1 «, 19, 32, 40, 48, 50, 55, 58 ~ stone oxide layer; 15, 38, 42 ~ photoresist pattern layer; 16, 44, 54 ~ spacer wall; 2 1, 6 2 ~ dielectric Layers; 22, 64 ~ metal layers; 1 0 1, 3 0 1 ~ source doped regions; 102, 302 ~ drain doped regions; 131, 132, 361, 381, 401, 421, 54 openings; 211 621 ~ Contact window.
0503-8056TWF(N) ; TSMC2002-0083 ; SPIN.ptd 第12頁0503-8056TWF (N); TSMC2002-0083; SPIN.ptd page 12
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