TW577115B - Split gate flash memory having independent erasing gate and its manufacturing method - Google Patents

Abstract

A kind of separate gate flash memory having independent erasing gate is disclosed in the present invention. The invention includes a substrate, the first conduction layer, a floating gate, the first insulation layer, a control gate, an insulation spacer, a tunneling oxide layer, an erasing gate and the second conduction layer. The first and the second doped regions are provided in the substrate. The first conduction layer is disposed in the first doped region; and the floating gate and the first insulation layer are disposed on the lower half portion and the upper half portion, respectively, of sidewall of the first conduction layer. The control gate is disposed on the floating gate sidewall; and the insulation spacer is disposed on the control gate so as to form an opening between the insulation spacer and the first insulation layer that is separated from the insulation spacer. The tunneling oxide layer is formed on the inner wall of the opening; and the erasing gate is disposed inside the opening. The second conduction layer is disposed in the second doped region.

Description

577115

Field of the Invention: The present invention relates to a separate Lanmei ★ ^〗 · memory and its manufacturing method, the formula (Spllt_e) flash, clothing is a bed, and in particular, the one-pole split gate flash memory Relevant technical description of the gate and its manufacturing method: The system ΐ Ϊ It It ^ 图 It 闸 至 至 至 至 至 至 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 说明 1 说明A silicon substrate 10, a gate oxide layer 11, a polycrystalline stone layer 12 and -nitriding. Referring to the first figure, the lithography etching step is used to open the nitrogen number 131 and make the bottom of the opening 131 The polycrystalline dream layer 12 is also recessed after being etched. Next, referring to FIG. 1C, a silicon layer 14 is deposited on the silicon nitride layer 丨 3 and fills the opening 丨 3i. Then, the silicon oxide layer 4 is etched back to expose the nitrided silicon layer 13 and only the silicon oxide layer 4 filling the opening 31 is left. Next, referring to the figure, using a photoresist pattern layer 15 as a mask, the silicon nitride layer 13 and the polycrystalline silicon layer 丨 2 are etched to form an opening 丨 32, and the bottom of the opening 1 32 is exposed. Gate oxide layer 丨 丨. Next, an ion distribution is performed to form a source doped region 101 in the silicon substrate 10 under the opening 132. Next, referring to FIG. 1E, the photoresist pattern layer 5 is removed. An insulating spacer 16 made of a silicon oxide layer is formed on the side wall of the opening 1 32. Then, a polycrystalline silicon layer 17 is deposited on the silicon nitride layer 13 and the silicon oxide layer 14 to fill the opening 1 3 2, and the polycrystalline silicon layer 17 is etched back to expose the silicon nitride layer 13 and the oxide. The silicon layer 1 4 leaves the compound crystal filling the opening 1 3 2

577115 V. Description of the invention (2) Silicon layer 17. Next, as shown in Figure 丨 F, the polycrystalline silicon layer 丨 7 is oxidized to form a silicon oxide layer 18 on the polycrystalline silicon layer 17, and then the silicon oxide layers i 4 and 18 are used as a mask. Carry out the last name engraving so that the silicon nitride layer 1 3 on both sides of the polycrystalline silicon layer 17 and the polycrystalline silicon layer 12 and the gate oxide layer are removed to expose the silicon substrate. Next, referring to FIG. 1G, a silicon oxide layer 9 is formed on the surface and sidewalls of the visible deposition layer, and a polycrystalline silicon layer 20 is deposited on the surface of the silicon oxide layer i 9. Next, referring to FIG. 1H, the polycrystalline silicon ^ 20 is etched to form a gap-shaped polycrystalline silicon layer 20 as a character & Finally, please refer to FIG. 11 to deposit a dielectric The electrical layer 21 and the dielectric layer 21 and the silicon oxide layer 19 are etched to form a contact window 211) that exposes the silicon substrate 10, and then an ionic layout is performed to place the silicon substrate under the contact window 2m. A drain doped region 102 is formed. Then, a metal layer 22 is sunk on the dielectric layer 21, and the contact window 21m is filled as a contact line of the bit line to insert the fossil-rich Fossil® Q flash memory for erasing. The thickness of the ^ 3 4 layer 12 氧 oxygen cut layer 19 on 10 is "to be thinner to handle" 3 Lit: In terms of writing, it is located in the polycrystalline stone layer;〗. Similarly, the thickness a and thickness c need to be thin to facilitate hot electron injection with fast current. However, the above is limited to the silicon oxide layer at the mother place. 9 has the same

577115 V. Description of the invention (3) Requirements for thickness (a = b = c) status. Summary of the invention: In view of this, the separation of the gates of the gates is effective to avoid the addition of erasing and flashing of the separate gate-type flashes of the present invention, so that the erasing of the gate-types of the gate-separating gates cannot be performed simultaneously. , Write and read the first fast doped region and the first doped region of the present invention, and the first insulating layer on the lower half side of the first doped conductive layer, a gate sidewall is provided, and the wall is arranged to be controlled into an opening; A penetrating, disposed in the opening; a second insulating layer, an insulating layer, according to the above and the separated gate electrode type, provides a substrate for high-order memory and reading purposes, flash memory of the second doped region electrical wall, And placed on the floating and gate oxidation on the gate separately, the first, set, set the purpose of flash memory, the purpose of the memory pressure erasure is to improve the effectiveness of its benefits, the body of the invention, inclusion zone; sexual contact and placement The gate is floating, and the layer is in the form of “the borrowing occurs when one is used, the other is different, the one is provided by a single voltage and has a unique gate; the first pole and the base are first formed in the second. Electrical layer, electrically wipe the gate and provide a substrate on the first conductive layer. The conductive layer is connected to the gate and the bottom of the insulation edge of the gate bottom is connected to the inner wall of the gate. In addition to voltage collapse. The thickness of the gate oxide layer is removed by erasing the gate electrode. The gate electrode has a first edge on the base;-: placed between the floating ... edge gaps to remove the gate doping interval; on. A method comprising the independent erasing gate of the doped region includes the following steps:, the first doped region 0503-8056TW (N); TSMC2002-0083; SPIN.ptd page 6 577115

A first insulation layer and a second upper sequential layer side wall gate are divided into a first insulating layer, the conductive layer of which is shaped; the upper layer of the impurity-controlling area is preferably formed as a gate electrode, and is formed in a first sequential order Do not form an opening with the side wall of the first conductive edge layer and the second conductive second conductive layer to make a gate electrode; form a contact as a bit line on the outside of the gate electrode. Then, a detailed description of the first embodiment is formed between the surface of the conductive layer, the floating gate layer, and the base edge layer, respectively, and a base-shaped window is formed inside the opening in the base insulation gap; The bottom surface and the floating wall on the surface; the remaining one is tunneled to form a first step in the connection method. The insulating layer is on the substrate, and the second oxide layer and the doped isotropic layer are formed. The miscellaneous area window is filled with the first conductive layer, in which the floating gate electrode and a second conductive edge are floating; in the second moment, the second conductive layer is used as a wipe gate electrode, and the second conductive layer The three-conductor gate-eliminating electrode and the following control are shown in FIGS. 2A to 2L to illustrate a manufacturing method with independent gate-eliminating electrodes according to an embodiment of the present invention. First, referring to FIG. 2A, a substrate such as a semiconductor substrate is provided, and then a silicon oxide layer 32, a polycrystalline silicon layer 34, a silicon nitride layer, and a photoresist pattern layer are sequentially formed on the substrate 30. 38. The photoresist pattern layer 38 has a plurality of openings 381. _Next, please refer to FIG. 2B, with the photoresist pattern layer 38 as a mask, the silicon nitride layer 36 is etched to form a plurality of openings 3 6 1, and the polycrystalline silicon layer 34 at the bottom of the opening 3 6 1 is etched. Then a depression occurs. First, referring to FIG. 2C, the photoresist pattern layer 38 is removed. Next, a silicon oxide layer 40 is formed on the silicon nitride layer 36 and fills the opening 36m. After that, the silicon oxide layer 40 is etched back to the silicon nitride layer 36 to be exposed, leaving only the filled opening.

0503-8056TWF (N); TSMC2002-0083; SPIN.ptd

577115 V. Description of the invention (5) " '--- 361 silicon oxide layer 40. Next, please refer to Figure 2d, using a photoresist pattern layer 42 as a cover, two = a silicon nitride layer 36 and a polycrystalline silicon layer 34 to etch to form an opening 421: a way out of the opening 42 1 a silicon oxide layer 3 at the bottom 2. Next, an ion cloth is implemented to form a source doped region 301 in the substrate 30 below the opening 421. Next, referring to FIG. 2E, the photoresist layer 剥 is removed. Then, an annealing treatment step is selectively performed, and the degree is about J 8 0 c, so as to enhance the lateral diffusion of the source doped region 3 01. Then, a conventional method of forming a spacer wall is used to form a spacer wall 44 made of a silicon oxide layer on the inner wall of the opening 421, with a thickness of about 400 to 500 angstroms. At the same time, the silicon oxide layer 32 at the bottom of the opening 421 is removed. Next, a polycrystalline silicon layer 46 is deposited on the silicon nitride layer 36 and the silicon oxide layer 40, and fills the opening 421 to be in electrical contact with the source doped region 301. Subsequently, the polycrystalline silicon layer 46 is etched back to the exposed silicon nitride layer 36 and the silicon oxide layer 40, leaving the polycrystalline silicon layer 46 in the opening 421 as the source line. Next, referring to FIG. 2F, the polycrystalline silicon layer 46 as a source line is thermally oxidized to form a silicon oxide layer 48 having a thickness of about 150 to 250 angstroms on the polycrystalline silicon layer 46. Then, the silicon oxide layers 40 and 48 are used as a mask to perform etching, so that the silicon nitride layer 36, the polycrystalline silicon layer 34, and the silicon oxide layer 32 on both sides of the polycrystalline silicon layer 46 are removed to form an opening 401. And the substrate 30 is exposed. The polycrystalline spar layer 34 (that is, located on the lower side wall of the source line 46) is used as the floating closed electrode 0. Next, please refer to FIG. 2G, between the exposed substrate 30 and the floating layer. The electrode 34 and the silicon oxide layer 40, 48 are sequentially and compliantly formed on the surface of the silicon oxide layer 50.

577115 Month Revision 91112399 V. Description of the invention (7) 2 J Figure. Next: Come, please refer to Figure 21 (figure, remove the bottom of the opening 401, and the way out of the base 3 〇. Then implement a departure + German # v + Xi 30) (that is, the value of the door grabbing cloth to expose the The substrate 302 is formed by a metal layer: a dielectric acoustic j layer: 2 / and constructed by a lithographic etching step and doped with a second electrode (dielectric 'ild), 22 and a gold layer is deposited on the dielectric layer 62 Contact: 2 Example 1: Jinzhao: ί 1 ΐ " 30i ^ ^ ^ ^: Manufacture of gate-type flash memory: Mingzhi has separate cat two places with independent erasing gate 'Please refer to Section 2L Figure, which depicts a separate flash memory with independent J = pole according to the present invention: 34 = two; $ crystal: layer 46, monolithic oxide, -floating Li penetrating oxidation Open 58 S ϋ & gate 52, an insulation barrier 54, one = 0 and: gate 60, a nitride layer 56 and a metal layer "complex; layer" I doped = one and- The drain-doped region ... is in electrical contact with the region 301. ',, /' 置 -n # q The source line and the source-doped coil Rizishan 4 are disposed on the lower half side of the polycrystalline stone layer 46: 30i: i The stone evening layer 32 and the spacer 44 are respectively The second stone evening layer 48 is provided on the polycrystalline stone evening layer, and the oxide stone evening layer and Fusuomen Temple 2 :: are on. The control gate 52 as a character line is disposed on the side wall of the dirty gate 34. Nizhuang produces oxygen aarnm ^ ^ 9 silicon layer 50 and the floating gate 34 and the base 30 I edge respectively. The insulating gap 54 is provided on the control gate, and the disk

0503-8056TWFl (N); TSMC2002.0083.ptc, an opening 541 is formed between the silicon layer 4 " ^^. Pass through the oxide layer 58 shape,

Page 10 577115 j number 9ηι is QQ V. Description of the invention (8) __ is formed on the inner wall of the opening 541, and the silicon P layer 56 and the silicon oxide layer 55 are disposed in the opening 541. Nitriding is used as the edge plug between the two gate electrodes 6 / the erase gate 60 and the control electrode 52 with a thickness of 20 mm, and the nitride layer is electrically connected to the electrode The doped region 30 is a metal layer 64_ ', such as a copper metal layer, an interlayer dielectric layer (called 62 and = and by the thickness of the metallization layer a L interpole) 52, and controls the oxygen of the closed electrode 52 ^ Tian Jin仃 When erasing, 萚 and the insulation plug 56 are used to solve the electric problem. ^ Hunting by the independent ㈣ gate electrode 60: through exposure, and mention; :::;. , ==; Program control When writing or reading, the performance of writing and reading can also be improved by the process of the pestle surface, although the degrees a and c 'are performed. Although the thickness of the dimethyl ester emulsion layer 50 is thick, although the present invention has been disclosed in a preferred embodiment, anyone who is familiar with the art, such as limiting the present invention, is not intended to be used within the scope of God. ^^ Therefore, too far from the essence of the present invention as defined by the scope of the attached patent application shall be the scope of Maoming's protection. Amendment 0503-8056TWF1 (N); TSMC2002-0083. Pt c page 11577115 Schematic In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a detailed description is given below with reference to the preferred embodiments and the accompanying drawings, as follows: Figures 1A to 1I are illustrated A cross-sectional view of a traditional manufacturing method of a gate-type flash memory. 2A to 2L are cross-sectional views showing a method for manufacturing a split gate flash memory according to an embodiment of the present invention. [Symbol description] 10, 30 ~ substrate; 11 ~ gate oxide layer; 12, 17, 20, 34, 46, 52, 60 ~ polycrystalline stone layer; 13, 36, 56 ~ nitride stone layer; 14, 1 «, 19, 32, 40, 48, 50, 55, 58 ~ stone oxide layer; 15, 38, 42 ~ photoresist pattern layer; 16, 44, 54 ~ spacer wall; 2 1, 6 2 ~ dielectric Layers; 22, 64 ~ metal layers; 1 0 1, 3 0 1 ~ source doped regions; 102, 302 ~ drain doped regions; 131, 132, 361, 381, 401, 421, 54 openings; 211 621 ~ Contact window.

0503-8056TWF (N); TSMC2002-0083; SPIN.ptd page 12

Claims (1)

577115 VI. The scope of patent application is 300 angstroms. 5. The independent flash gate flash memory with independent erase gate as described in item 1 of the scope of patent application, further comprising a third insulating μ on the first conductive layer. Since then, the flash memory with independent erasing closed pole separation gate type flash memory as described in item 5 of the scope of patent application, wherein the third insulating layer is a silicon oxide layer 0 7 The flash memory with independent erasing idler-separated gates described in item 1, wherein the first conductive layer is a polycrystalline layer. -Day 8: As described in item 1 of the scope of patent application, a split gate flash memory having an independent erase gate, wherein the first insulating layer is a monolithic oxide layer. 9. The separated gate type flash memory with independent erasing gates as described in item 1 of the scope of the patent application, wherein the insulating partition wall is composed of an oxide formed by tetraethylmetarate. Soil fragmentation I. As described in item 1 of the scope of the patent application, the flash memory with independent erasing idler and separated gate type flash memory, wherein the second conductive layer is a copper-gold layer. II · A method for manufacturing a split gate flash memory with independent erasing gates, comprising the following steps: A substrate is provided orally, the substrate has a first doped region, and the first impurity regions are sequentially formed on the substrate. There is a first conductive layer and a first insulating layer, and a side wall of the conductive layer is sequentially formed with a floating gate and a second insulating layer. 0503-8056TWF (N); TSMC2002-0083; SPIN.ptd Page 14 577115 Six 'Application Outline® ----- The floating gate is insulated from the first conductive layer and the substrate, respectively; on the substrate A second conductive layer is formed on the surface of the floating gate, the first insulating layer and the second insulating layer in conformity, wherein the second conductive layer is insulated from the substrate and the floating gate respectively; An sidewall of the second conductive layer forms an insulating gap; the second conductive layer is anisotropically etched to form an opening, and the second conductive layer remaining below the opening serves as a control gate; A through oxide layer and an erase gate are formed in the opening; a second doped region is formed in the substrate outside the control gate; a contact window is formed above the second doped region; and the junction A third conductive layer is filled in the window as a bit line. 1 2 · The method for manufacturing a separate gate flash memory having an independent erase gate as described in item 丨 丨 of the scope of the patent application, further comprising forming a gap between the erase idle pole and the control gate. Step of the third insulating layer. 1 3 · The method for manufacturing a separate gate flash memory with independent erasing closed poles as described in item 2 of the scope of patent application, wherein the third insulating reed is a layer of gasified fossil. '14. The method for manufacturing a split gate flash memory with independent erasing closed poles as described in item 2 of the patent application scope, wherein the thickness of the third insulating layer is in a range of 200 to 300 angstroms. 15. The method for manufacturing a separate gate flash memory with an independent erase gate as described in item 11 of the scope of the patent application, wherein the first doped region is a source doped region and the The second doped region is a drain doped region. 1 6 · With independent erase gate as described in item 11 of the scope of patent application 577115 The manufacturing method of the flash-type flash memory is a polycrystalline silicon layer. Wherein, the first conductive layer has an independent erase gate, and the first insulating layer is 8 17. The manufacturing method of the knife-off gate flash memory as described in item 11 of the patent application scope is a silicon oxide layer. . Octopus P. Application for the manufacturing method of flash memory with independent erasing gate knife as described in item 11 of the patent scope, wherein the second silicon oxide layer 819. The method for manufacturing a separate gate flash memory with an independent erase gate, wherein the second system is a polycrystalline silicon layer. That is, the method for manufacturing a separate gate flash memory with an independent erase gate as described in item 11 of the scope of the patent application, wherein the insulating spacer is an oxide formed of tetraethyl silicate Made up. 21 · The method for manufacturing a separate gate flash memory having an independent erase gate as described in item 丨 丨 of the scope of the patent application, wherein the third conductive layer is a copper metal layer. 9 0503-8056TWF (N); TSMC2002-0083; SPIN.ptd page 16