526592526592
五、發明説明（） 發明領域： 本毛明係有關於一種半導體元件結構及製程，且特別 =有關於一種堆疊間隙壁結構及製程，可有效地降低耦合 電谷（coupling capacitance)。 發明背景： 電fe和電子工業不僅要求增加其整體之性能表現並且 也在乎製造整體積體電路之成本的降低。就電腦而言，無 疑的’積體電路（例如動態隨機存取記憶體，DRAM)佔有一 決定性的角色。因為積體電路不只大量使用且也關係著電 腦之輸出入的速度表現。因Λ，追求積體電路的微小化以 降低成本以及其高速的表現幾為業者共同的目標。 (請先閲讀背面之注意事項再填寫本頁) 噘· -訂· 經濟部智慧財產局員工消費合作社印製 為求達到高積集度與高操作速度之要求，半導體元件 依照比例原則微小化，並且不斷地改善金氧半場效電晶體 (M〇SFET)元件的效能。為了製作次微米以下的元件^須 降低寄生電容與電&，方能提昇元件效能。經由各種半導 體技術上的改進，已可逵刭+婵氺 」運引-人倣未以下的尺寸。例如，對 於自對準㈣f-aligned)M0SFET幻牛，一般具有複晶石夕問 極，以及鄰接於問極之自對準源極/没極接觸區域。这些自 對準刪窗元件之性能優於其他Μ，因為其具有較小 着 526592V. Description of the invention () Field of the invention: This Maoming is related to a semiconductor device structure and process, and in particular = a stacked spacer structure and process, which can effectively reduce the coupling capacitance. Background of the invention: The electrical and electronic industries not only require an increase in their overall performance, but also a reduction in the cost of manufacturing integrated circuits. As far as computers are concerned, there is no doubt that 'integrated circuit (such as dynamic random access memory, DRAM) plays a decisive role. Because integrated circuits are not only used in large quantities, but also related to the speed performance of the computer's input and output. Because of Λ, the pursuit of miniaturization of integrated circuits has been the common goal of industry players to reduce costs and high-speed performance. (Please read the notes on the back before filling this page) 噘 · -Order · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. And continuously improve the performance of metal oxide half field effect transistor (MOSFET) devices. In order to make sub-micron devices, the parasitic capacitance and electricity must be reduced to improve device performance. With the improvement of various semiconductor technologies, the size of 逵 刭 + 婵 氺 can be introduced. For example, for self-aligned ㈣f-aligned) MOSFETs, they usually have polycrystalline spar internodes and self-aligned source / non-contact regions adjacent to interfacial poles. The performance of these self-aligned window-cutting elements is better than other M's, because
、發明説明（） 的尺寸，較高的密度，較低的能量損耗與製作成本 一般傳統自對準MOSFET元件之製作，係藉由定義單 晶半導體基板之元件區域上的堆疊閣極層而形成，此堆疊 閘極層包括在閘極氧化層上之複晶矽層以及氧化矽頂^ 層。在堆疊閘極層側壁上之側壁絕緣間隙壁，通常由氧化 石夕所構成，用以隔離導電的閘極層以及相鄰的自對準插 塞〇 然而很不幸地，為了達到高元件密度的目的，必須使 用更薄的氧化矽間隙壁，因而造成一個嚴重的問題。當使 用清洗步驟，移除基底表面自然生成氧化層時，薄的氧化 石夕間隙壁亦同時受到侵蝕，導致閘極與自對準插塞之間形 成電性短路。· (請先閱讀背面之注意事項再填寫本頁) %· 訂 經濟部智慧財產局員工消費合作社印製 為解決上述問題，改善自對準MOSFET元件，曾有多 種解決方案被提出。其中一種係使用氮化石夕間隙壁取代氧 化矽間隙壁。雖然氮化矽間隙壁可作為蝕刻中止層，減少 間隙壁的4貝耗’但疋當臨界尺寸進入到低於次微米的世代 時’而達7的介電常數（dielectric constant)造成嚴重的電容 輕合效應，降低元件的操作速度，因而限制積集度的提昇。 發明目的及概述： 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 4 526592 A7 B7 五、發明説明（） (請先閱讀背面之注意事項再填寫本頁) 本發明之一目的在提供一種堆疊間隙壁結構，可以P爷 低閘極側壁間隙壁受到侵蝕，減少損耗，可有效地隔離兩 個相鄰的導電層。 本發明之另一目的在提供一種堆疊間隙壁結構，可有 效地隔離兩個相鄰的導電層，並且具有更低的等效介電常 數，降低相鄰導電層之間的電容耦合效應。 本發明提供一種堆疊間隙壁之製造方法，此方法至少 包括下列步驟。首先提供一半導體基底，且在半導體基底 上已形成至少一堆疊層，由下而上依序包括一導電層與一 頂蓋層。接著在半導體基底上形成一介電層，約略高於導 電層之南度’然後在半導體基底上形成一第一氮化石夕層。 之後蝕刻氮化矽層與介電層，在堆疊層之側壁上形成一第 一間隙壁。接著在半導體基底上形成一第二氮化矽層，然 後蝕刻第二氮化矽層，在第一間隙壁之側壁上形成一第二 間隙壁。 經濟部智慧財產局員工消費合作社印製 本發明亦提供一種半導體結構之製造方法，此方法至 少包括下列步驟。首先在一半導體基底上形成一堆疊層， 由下而上依序包括一導電層與一第一介電層。接著在半導 體基底上形成一第二介電層，約略高於導電層之高度，然 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 526592 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 後在半導體基底上形成一第三介電層。之後蝕刻第三介電 層與第二介電層，在堆疊層之側壁上形成一第一間隙壁。 接著在半導體基底上形成一第四介電層，然後蝕刻第四介 電層，在第一間隙壁之側壁上形成一第二間隙壁。其中， 第二介電層之介電常數低於第一、第三與第四介電層之介 電常數。 本發明提供一種堆疊間隙壁結構，形成於一半導體基 底上之一堆疊層的側壁上，堆疊層由下而上包括一導電層 與一頂蓋層。此結構至少包括一低介電底部，形成於半導 體基底上，且位於堆疊層之側壁上，低介電底部約略高於 導電層之高度。一氮化矽頂部，形成於低介電底部上，且 位於堆疊層之側壁上，氮化矽頂部與低介電底部形成一内 部間隙壁。以及一氮化矽外部，形成於低介電底部與氮化 矽頂部之側壁上，完全覆蓋低介電底部與氮化矽頂部，形 成一外部間隙壁。 經濟部智慧財產局員工消費合作社印製 本發明亦提供一種半導體結構，係架構在一半導體基 底上。此結構至少包括一堆疊層，形成於半導體基底上， 堆疊層由下而上包括一導電層與一第一介電層。一第二介 電層，形成於半導體基底上，且位於堆疊層之側壁上，第 二介電層約略高於導電層之高度。一第三介電層，形成於 第二介電層上，且位於堆疊層之側壁上，第三介電層與第 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 526592 A7 B7 五、發明説明（) 二介電層形成一内部間隙壁。以及一第四介電層，形成於 第二介電層與第三介電層之側壁上，完全覆蓋第二介電層 與第三介電層，形成一外部間隙壁。其中，第二介電層之 介電常數低於第一、第三與第四介電層之介電常數。 圖式簡單說明： 本發明的較佳實施例將於往後之說明文字中辅以下列 圖形做更詳細的闡述，其中： 第1 A-1 D圖繪示本發明之一較佳實施例之製程剖面示 意圖。 第2A-2D圖繪示本發明之另一較佳實施例之製程剖面 示意圖。 圖號對照說明： (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 100 基底 102 閘極氧化層 104 複晶矽層 105 側壁 106 鎢層 108 氮化矽頂蓋層 110 氮化矽襯裡層 112 介電層 112a 底部間隙壁 114 氮化矽層 114a 頂部間隙壁 116 氮化矽間隙壁 1 18 導電區 120 導電層 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 526592 A7 B7 五、發明説明（) 200 基底 202 導電區 210 介電層 212 導電層 214 氮化矽頂蓋層 215 側壁 216 氮化矽襯裡層 218 介電層 218a 底部間隙壁 220 氮化矽層 220a 頂部間隙壁 221 側壁 222 開口 224 氮化矽間隙壁 226 導電插塞 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 發明詳細說明： 本發明提供一種堆疊間隙壁結構，在氮化矽間隙壁下 製作具有低介電常數之間隙壁，並且再覆蓋上氮化矽外間 隙壁，不僅可以降低整個間隙壁的等效介電常數，而且可 以精確控制間隙壁的厚度，降低每個元件的尺寸，進而提 高元件積集度。 第1 A-1 D圖是繪示本發明之一較佳實施例之製程剖面 示意圖。首先請參照第1 A圖，首先提供一半導體基底1 00， 比如是具有<100>晶格結構之早晶碎基底。在完成元件隔離 (未顯示）製作之後，在主動區域上形成閘極堆疊層，其可 為字元線，或是連接字元線之分支。閘極堆疊層由下而上 依序包括閘極介電層、閘極導電層與閘極頂蓋層。閘極介 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 5265922. Description of the invention () The size, higher density, lower energy loss, and manufacturing cost of the conventional self-aligned MOSFET device are generally formed by defining stacked electrode layers on the element area of a single crystal semiconductor substrate. The stacked gate layer includes a polycrystalline silicon layer and a silicon oxide top layer on the gate oxide layer. The side wall insulation gap on the side wall of the stacked gate layer is usually composed of oxidized stone to isolate the conductive gate layer and adjacent self-aligned plugs. Unfortunately, in order to achieve high component density For this purpose, thinner silicon oxide spacers must be used, thus causing a serious problem. When the cleaning step is used to remove the naturally formed oxide layer on the surface of the substrate, the thin oxide stone gap wall is also eroded at the same time, resulting in an electrical short between the gate and the self-aligned plug. · (Please read the notes on the back before filling this page)% · Order Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs To solve the above problems and improve self-aligned MOSFET components, various solutions have been proposed. One of them is to replace the silicon oxide spacer with a nitride spacer. Although the silicon nitride spacer can be used as an etch stop layer to reduce the 4 watts of the spacer 'but when the critical dimension enters sub-micron generations', a dielectric constant of 7 causes serious capacitance The light-on effect reduces the operating speed of the component, thus limiting the increase in the degree of accumulation. Purpose and summary of the invention: The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 4 526592 A7 B7 V. Description of the invention () (Please read the notes on the back before filling this page) One of the objectives of the invention In providing a stacking spacer structure, the side walls of the low gate can be eroded, reducing losses, and effectively separating two adjacent conductive layers. Another object of the present invention is to provide a stacked spacer structure, which can effectively isolate two adjacent conductive layers, has a lower equivalent dielectric constant, and reduces the capacitive coupling effect between adjacent conductive layers. The present invention provides a method for manufacturing a stacked spacer wall. The method includes at least the following steps. First, a semiconductor substrate is provided, and at least one stacked layer has been formed on the semiconductor substrate, and includes a conductive layer and a cap layer in this order from bottom to top. Next, a dielectric layer is formed on the semiconductor substrate, which is slightly higher than the south of the conductive layer ', and then a first nitride layer is formed on the semiconductor substrate. Then, the silicon nitride layer and the dielectric layer are etched to form a first gap wall on the sidewall of the stacked layer. A second silicon nitride layer is then formed on the semiconductor substrate, and then the second silicon nitride layer is etched to form a second spacer on the sidewall of the first spacer. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economics The present invention also provides a method for manufacturing a semiconductor structure. The method includes at least the following steps. First, a stacked layer is formed on a semiconductor substrate, and a conductive layer and a first dielectric layer are sequentially included from bottom to top. Next, a second dielectric layer is formed on the semiconductor substrate, which is slightly higher than the height of the conductive layer. However, the size of this paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 526592 A7 B7 V. Description of the invention () (please (Read the precautions on the back before filling this page), and then form a third dielectric layer on the semiconductor substrate. Then, the third dielectric layer and the second dielectric layer are etched to form a first gap wall on a sidewall of the stacked layer. A fourth dielectric layer is then formed on the semiconductor substrate, and then the fourth dielectric layer is etched to form a second gap wall on the sidewall of the first gap wall. The dielectric constant of the second dielectric layer is lower than that of the first, third and fourth dielectric layers. The present invention provides a stacked spacer structure formed on a sidewall of a stacked layer on a semiconductor substrate. The stacked layer includes a conductive layer and a cap layer from bottom to top. This structure includes at least a low-dielectric bottom formed on a semiconductor substrate and located on a side wall of the stacked layer. The low-dielectric bottom is approximately higher than the height of the conductive layer. A silicon nitride top is formed on the low dielectric bottom and is located on the side wall of the stacked layer. The silicon nitride top and the low dielectric bottom form an internal gap wall. And a silicon nitride outer part is formed on the sidewalls of the low dielectric bottom and the silicon nitride top, completely covering the low dielectric bottom and the silicon nitride top, and forming an external gap wall. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The present invention also provides a semiconductor structure, which is constructed on a semiconductor substrate. This structure includes at least one stacked layer formed on a semiconductor substrate. The stacked layer includes a conductive layer and a first dielectric layer from bottom to top. A second dielectric layer is formed on the semiconductor substrate and is located on the side wall of the stacked layer. The second dielectric layer is slightly higher than the height of the conductive layer. A third dielectric layer is formed on the second dielectric layer and is located on the side wall of the stacked layer. The third dielectric layer and the first paper size apply the Chinese National Standard (CNS) A4 specification (210X297 mm) 526592 A7 B7 V. Description of the Invention (2) The two dielectric layers form an internal partition wall. A fourth dielectric layer is formed on the sidewalls of the second dielectric layer and the third dielectric layer, and completely covers the second dielectric layer and the third dielectric layer to form an external gap wall. The dielectric constant of the second dielectric layer is lower than that of the first, third, and fourth dielectric layers. Brief description of the drawings: The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures, where: Figures 1 A-1 D show a preferred embodiment of the present invention Schematic cross-section of the process. Figures 2A-2D are schematic cross-sectional views of a manufacturing process according to another preferred embodiment of the present invention. Comparison of drawing numbers: (Please read the precautions on the back before filling this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, 100 substrate 102 gate oxide layer 104 polycrystalline silicon layer 105 sidewall 106 tungsten layer 108 silicon nitride top Cover layer 110 Silicon nitride backing layer 112 Dielectric layer 112a Bottom spacer 114 Silicon nitride layer 114a Top spacer 116 Silicon nitride spacer 1 18 Conductive area 120 Conductive layer This paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 526592 A7 B7 V. Description of the invention (200) 202 substrate 202 conductive area 210 dielectric layer 212 conductive layer 214 silicon nitride cap layer 215 sidewall 216 silicon nitride liner layer 218 dielectric layer 218a bottom gap 220 Silicon nitride layer 220a Top spacer 221 Side wall 222 Opening 224 Silicon nitride spacer 226 Conductive plug (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Detailed description of the invention: This The invention provides a stacked spacer structure. A spacer with a low dielectric constant is fabricated under a silicon nitride spacer and covered with a silicon nitride outer space. Wall, not only can reduce the effective permittivity of the whole spacer, and a gap can be precisely controlled thickness of the wall, reducing the size of each element, and further improve product set of elements. Figures 1A-1D are schematic cross-sectional views illustrating a process of a preferred embodiment of the present invention. First, please refer to FIG. 1A. First, a semiconductor substrate 100 is provided, such as an early-crystal crushed substrate having a < 100 > crystal structure. After the device isolation (not shown) is completed, a gate stack layer is formed on the active area, which can be a word line or a branch connected to the word line. The gate stack layer includes a gate dielectric layer, a gate conductive layer, and a gate cap layer in this order from bottom to top. Gate electrode This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 526592
、發明說明( 電層例如是以熱氧化法形成之氧化 例如包括複晶…04以及…二層10 _導電層 介雷馬 及鎢層106，而閘極頂蓋層為一 後續二例如包括氮切層108、氮氧化石夕層或是其他對 佳。、問上！良好㈣選擇比之材質[且以氮化梦層較 成氧Γ堆豐層之製作方法，例如先在基&⑽上依序形 1〇8，二層102、複晶矽層104、鎢層106以及氮化矽層 閘枉堆Γ以傳統微影及㈣技術定義出所需的圖案，形成 層4形成閘極堆疊層之後’可選擇性地在基底 太、面形成一層共形且薄的氮化矽層110,厚度約為3-30 「(nm) ’因此氮化矽’ ！ 1〇會覆蓋閘極堆疊層的側壁 作為概層（liner layer)。 .........1: (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 °月參fe第1 B圖，接著在基底！ 〇〇上且在閘極堆疊層之 間形成-層介電層112,且介電層"2約略高於閘極導電 層(亦即複晶矽層104與鎢層106)之高度，介電層112係由 低介電常數材質所構成，且其介電常數⑷……丨…μ㈣ 必須小於閘極頂蓋層之介電常數，若閘極頂蓋層由氮化矽 =構成，則其介電常數需小於7。介電層丨1 2所選用之材 質例如是氧化矽，其介電常數約為4左右，亦可選用其他 ”有更低介電常數之材質，例如旋塗式玻璃（s〇G)，旋塗式 聚合物（SOP)等，至於其形成方法均不在此限。介電層112 的製作方法首先在基底100上覆,蓋一層介電層，然後再以 均勻性蝕刻的方式，控制蝕刻速率，去除閘極頂蓋層上之 訂 # 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公董) 526592 五、發明説明（） 口 P刀僅留下在閘極堆聂屏 μ 隹宜層之間所需之部分。 然後再於美广 (請先閲讀背面之注意事項再填寫本頁} 、土氐100上形成一層介電層114，此介電層 1 1 4必須可良好 工制其厚度，以利於控制後續形成之間隙 壁的寬度。介雷爲彳，^ 、θ 9 1 14所選用之材質比如是氮化矽、氮氧 ^或疋其他易於控制厚度且具有良好蝕刻選擇比之材 、、、氮化矽較佳。介電層1 1 4比如可使用化學氣相沉 積法（CVD)所形成之氮化石夕層，其厚度控制遠優於氧化石夕層 或其他介電層，可逵 運5-60奈米（nrn)，甚至更低。 請參昭g ^ r m “、、禾丨L圖’然後進行回蝕刻，在閘極堆疊層之側 壁105上形成間隙壁頂部1 14a，例如以反應性離子蝕刻 (με)去除閘極頂蓋層1〇8以及基底1〇〇上的部分，僅剩下 在閘極堆疊層側f 105 ±之部分，以作為間隙壁頂部 經濟部智慧財產局員工消費合作社印製 1 1 4a。之後再以間隙壁頂部1 1 4a為罩幕，蝕刻底下的介電 層1 1 2的暴露部分，僅剩下在側壁丨〇5上的部分，形成間 隙壁底部112a，由間隙壁底部112a與間隙壁頂部114a組 成内部間隙壁。由於閘極頂蓋層i 〇8以及間隙壁頂部1 1耗 所選用之材質對於介電層n 2具有良好的蝕刻選擇比 (selectivity)，因此間隙壁頂部丨14a在蝕刻介電層1 12時損 耗甚少’且不會對閘極堆疊層形成破壞。而且，若事先有 形成氮化矽襯層1 1 〇，則可作為蝕刻中止層，使介電層工U 的蝕刻自動在襯層1 1 〇停止。 10 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐） 526592 A72. Description of the invention (The electrical layer is formed by thermal oxidation, for example, including multiple crystals ... 04 and ... two layers 10 _ conductive layer via Rema and tungsten layer 106, and the gate cap layer is a follow-up layer such as nitrogen cutting Layer 108, oxynitride layer or other is better., Ask! Good ㈣ choose the material [and the method of making nitridation dream layer is more oxygen Γ stack layer, for example, first on the base & ⑽ Sequentially 108, the two layers 102, the polycrystalline silicon layer 104, the tungsten layer 106, and the silicon nitride layer gate stack Γ define the required pattern using traditional lithography and gadolinium technology, forming layer 4 to form a gate stack After the layer ', a conformal and thin silicon nitride layer 110 can be selectively formed on the substrate too, and the thickness is about 3-30 "(nm)' So silicon nitride '! 10 will cover the gate stack layer The side wall is used as a liner layer. ......... 1: (Please read the notes on the back before filling this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Figure B, then on the substrate! 〇〇 and formed between the gate stack layer-layer dielectric layer 112, and the dielectric layer " 2 is slightly higher than the gate conductivity Layer (ie, the polycrystalline silicon layer 104 and the tungsten layer 106), the dielectric layer 112 is made of a low dielectric constant material, and its dielectric constant ⑷ ...... 丨 μ 丨 must be smaller than that of the gate cap layer. The dielectric constant. If the gate cap layer is made of silicon nitride, the dielectric constant must be less than 7. The material used for the dielectric layer 丨 12 is silicon oxide, for example, and its dielectric constant is about 4. Use other materials with lower dielectric constant, such as spin-on glass (sog), spin-on polymer (SOP), etc., as far as the formation methods are not limited. The method for making the dielectric layer 112 is first Cover the substrate 100 with a dielectric layer, and then control the etching rate by uniform etching to remove the order on the gate cap layer. # This paper size applies to China National Standard (CNS) A4 (210X297). ) 526592 V. Description of the invention () The knife P only leaves the required part between the gate electrode stack Nieping μ and the appropriate layer. Then come to Meiguang (Please read the precautions on the back before filling this page} 、 A dielectric layer 114 is formed on the soil 100, and the dielectric layer 1 1 4 must be workable. Its thickness is good for controlling the width of the spacers formed later. The median thunder is 彳, θ, θ 9 1 14. The selected material is silicon nitride, oxynitride ^, or 疋, etc. It is easy to control the thickness and has a good etching selection ratio. The material is preferably silicon nitride. The dielectric layer 1 1 4 can be formed using a chemical vapor deposition (CVD) nitride nitride layer, and its thickness control is much better than that of an oxide layer or other dielectric materials. Layer, can transport 5-60 nanometers (nrn), or even lower. Please refer to the figure ^ rm "," and "L" and then etch back to form the top of the gap wall on the side wall 105 of the gate stack layer 1 14a, for example, by removing reactive gate etching (με) on the gate capping layer 108 and the substrate 100, only the part on the gate stack layer side f 105 ± is left as the top of the gap wall economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau 1 1 4a. After that, using the top of the gap wall 1 1 4a as a mask, the exposed portion of the underlying dielectric layer 1 12 is etched, leaving only the part on the side wall 05 to form the gap wall bottom 112a. The gap wall bottom 112a and The partition wall top 114a constitutes an internal partition wall. Since the gate cap layer i 〇8 and the top of the gap wall 1 1 consume a selected material for the dielectric layer n 2 with a good etching selectivity, the top of the gap wall 14a is lost when the dielectric layer 12 is etched Very little 'and will not cause damage to the gate stack. In addition, if a silicon nitride liner layer 1 10 is formed in advance, it can be used as an etching stop layer to automatically stop the etching of the dielectric layer process U at the liner layer 1 10. 10 This paper size applies to China National Standard (CNS) A4 (210X297 mm) 526592 A7
睛翏照第1D圖，接著在 土（包括間隙壁頂邻 (請先閱讀背面之注意事項再填寫本頁) U4a與間隙壁底部U2a)之側壁上形成外部間隙壁116。'° 外部間M "6使用對後續沉積的介電層(比如：化矽： 具有較佳蚀刻選擇比的材質，比如是氮化石夕。外部間隙曰壁 "“勺形成方法，比如先在基底100上形成一層氮化矽層了 覆蓋内部間隙*，然後再進行回蝕刻，去除閘極堆心以 及基底1 00上之部分，僅留下在内部間隙壁側壁上之部分 作為外部間隙壁i i 6。 刀 然後再於閑極堆疊層之間的基底100中形成源極/汲極 區118 ’其形成方法例如可使用離子植入技術，進行換雜 而形成。然後再去除源極/汲極區丨丨8上的介電層，並在源 極/汲極區1 1 8上形成導電層丨2〇，比如是導線或是接觸窗 插塞。 經濟部智慧財產局員工消費合作社印製 請再參照第1 D圖，經由上述之製程即形成本發明之一 較佳實施例之堆疊間隙壁結構。本發明之堆疊間隙壁結構 係形成於閘極堆疊層之側壁上，如前所述，此閘極堆疊層 之結構至少包括閘極介電層、閘極導電層與閘極頂蓋層， 其中閘極頂盖層為第一介電層。本發明之堆疊間隙壁於 構，如圖所示，至少包括第二、第三與第四介電層。其中， 第一介電層其為一低介電底部，即前述之間隙壁底部 11 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 526592 五 經濟部智慧財產局員工消費合作社印製 、發明説明（） 係形成於半導體基底1 0 0上，且位於 側壁上，此彻八+ 立於間極堆疊層之 此低）丨電底部1 12a之高度等於戍古妖 之高度，且較# 3 μ > 次巧於間極導電層 層 低 化 四 化 較彳土疋略向於閘極導電層之高度。 ::鼠化石夕頂部’即前述之間隙壁頂部％，係：= "電底部1 12a上，且位於閘極堆疊層之側由、 八^ 14a與低介電底部112a組成-内部間隙壁。第 ^層為氮化石夕外部116,形成於低介電底部U2a鱼氮 頂部114a之側壁上，亦即覆蓋整個内部間隙 外部間隙壁。 化成 常 電 度 ： a 由於低介電底部11 2a之介電常數低於氮化矽之介電 數，因此在閘極導電層與接觸窗插塞12〇之間的等效介 常數比單純使用氮切更低，因此對應的等效間隙壁^ 比氮化矽更厚。如此，在閘極導電層與接觸窗插塞12〇 間在閘極側壁所造成電容搞合可大幅地降低，而且問極^ 線層之間的電容耦合亦可大幅地降低。在低介電底部}a 上形成氮化矽頂部114a可以防止在形成低介電底部ιΐ2 時受到破壞。 本發明之堆疊間隙壁結構除了可應用在閘極堆疊層之 外，亦可應用於位元線，減少位元線之間的電容耦合效應。 第2A-2D圖係繪示本發明之另一較佳實施例之製程剖面示 意圖。 12 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公复） 526592 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 請參照第2A圖，首先提供一半導體基底200，比如是 具有< 1 00>晶格結構之單晶矽基底，其上製作若干的半導體 元件，如金氧半（MOS)電晶體。在基底200中具有導電區 域202，例如是源極/汲極區，導電墊層，導電性導線或是 類型的導電區域。在基底200上形成有一層介電層210， 比如是氧化石夕層或是其他的低介電材質層。 接著在介電層2 1 0上進行位元線之製作，形成導電層 與頂蓋層之堆疊層，其製作方法比如在介電層210上依序 形成一導電層212與一頂蓋層214，導電層212之材質比 如是複晶石夕、铭、鹤、銅或是其合金。頂蓋層214之材質 比如是氮化矽、氮氧化矽層或是其他對後續蝕刻具有良好 蝕刻選擇比之材質層，且以氮化矽層較佳。接著以傳統的 微影及蝕刻技術定義出所需的導線圖案，形成位元線堆疊 層。在形成位元線堆疊層之後，可選擇性地在表面形成一 層共形且薄的氮化石夕層2 1 6，厚度約為3 - 3 0 n m，因此氮化 石夕層2 1 6將覆蓋位元線堆疊層的側壁2 1 5，作為襯層（1 i n e r layer) ° 經濟部智慧財產局員工消費合作社印製 請參照第2B圖，接著在介電層2 1 0上且在位元線堆疊 層之間形成一層介電層218，而且介電層218約略高於導 電層2 1 2之高度。介電層2 1 8係由低介電常數材質所構成， 13 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) 經濟部智慧財產局員工消費合作社印製 526592 五、發明説明（） 且其介電常數（dielectric constant)必 介電常數，若閘極Tg甚s Λ P 、]、於閘極頂蓋層之 右閑極頂盍層由氮化矽所槿 需小於7。介電声218所.$田 構成’則其介電常數 "电層2 1 8所選用之材質例 電常數約為4左右，亦可選用其他= :其介 介電材質’例如旋塗式玻璃(s〇 人：〶數之低 至於豆报士、十， 疋孟式聚合物（SOP)等， 至於其形成方法均不在此限。介電層2 ): 復盖㉟介電層，然後再以均勾性餘刻的 、： 控制餘刻速率，去降你太百望 式 亚 疋半★除位在頂i層214上之部& 位元線堆疊層之間所需的部分。 邊下在 然後再於基底20。上形成一層介電層22〇，此介電層 :須控制其厚度，以利於控制後續形成之間 介電層22°所選用之材質比如是氮化砍、氮氧切： 疋/、他易於控制厚度且具有良好儀刻選擇比之材質，且以 氮化石夕較佳。介電層220比如可使用化學氣相沉積法(CVD) 所形成之氛化石夕層，其厚度控制遠優於氧化石夕或其他介電 層，因此可獲得較小寬度之間隙壁，若使用氮化石夕層，: 厚度控制可達5-3 Onm，甚至更低。 请參照第2C圖，然後進行回蝕刻，在位元線堆疊層之 側土 2 1 5上形成間隙壁頂部22〇a，例如可使用反應性離子 蝕刻（RIE)去除頂蓋層214以及介電層21〇上之部分，僅剩 下在位兀線堆疊層側壁2 1 5上之部分，用以作為間隙壁。 14 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公 ::'.........ΜΨ.........、玎.........嫌， (請先閲讀背面之注意事項再填寫本頁) 526592 A7 B7 五、發明説明（） 隨後再以間隙壁頂部220為罩幕，蝕刻底下的介電層21 8 的暴露部 僅剩下在側i 215上的部分，形成間隙壁底 邛218a，由間隙壁底部218a與間隙壁頂部22〇a共同組成 内邛間隙壁。然後再繼續蝕刻底下的介電層21 0，直到暴 露出導電區域202，以形成接觸窗開口 222。由於頂蓋層 2 14與間隙壁頂部22〇a所選用之材質對於介電層218具有 良好的蝕刻選擇比（selectivity)，因此間隙壁頂部22〇a在蝕 刻介電層2 1 8與2 1 0時損耗甚好，且不會對位元線導電層 2 1 2造成破壞。 明麥照第2D圖，接著在内部間隙壁（包括間隙壁頂部 22 0a與間隙壁底部21 8a)之側壁上形成外部間隙壁224，並 且延伸覆蓋接觸窗開口 222之側壁221。此外部間隙壁224 選擇對後續沉積的介電層（比如是氧化矽層）具有較佳的蝕 刻選擇比的材質，例如是氮化矽。外部間隙壁224的形成 方法，比如先在基底200上形成一層氮化矽層，覆蓋内部 間隙壁以及接觸窗開口 222之側壁221與底部，然後進^ 回姓刻，去除頂蓋層214上以及開口 222底部之部分，订 形成所需的外部間隙壁224，覆蓋内部間隙壁以及開口 a。 之側壁221。隨後在開口 222之中填入導電材料，以形成2 接觸窗插塞2 2 6，電性連接至導電區域2 〇 2。 請再參照第2D圖，經由上述之製程即形成本發明之另 15 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁} -訂· 經濟部智慧財產局員工消費合作社印製 五 經濟部智慈財產局員工消費合作社印製Focus on Figure 1D, and then form an external partition 116 on the side walls of the soil (including the top adjacent to the partition (please read the precautions on the back before filling in this page) U4a and the bottom of the partition U2a). '° The outer space M " 6 uses a dielectric layer for subsequent deposition (such as siliconized silicon: a material with a better etching selection ratio, such as nitride nitride. The outer gap is called a wall, such as first A silicon nitride layer was formed on the substrate 100 to cover the internal gap *, and then etched back to remove the gate core and the part on the substrate 100, leaving only the part on the side wall of the internal gap as the external gap ii 6. The knife then forms a source / drain region 118 'in the substrate 100 between the stacks of idler electrodes. The formation method can be formed by ion implantation using ion implantation. Then the source / drain is removed. A dielectric layer on the pole area 丨 8 and a conductive layer on the source / drain area 1 18, such as a wire or a contact window plug. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Please refer to FIG. 1D again, through the above process, a stacked spacer structure of a preferred embodiment of the present invention is formed. The stacked spacer structure of the present invention is formed on the side wall of the gate stack layer, as described above , This gate stack layer The structure includes at least a gate dielectric layer, a gate conductive layer, and a gate cap layer, wherein the gate cap layer is a first dielectric layer. As shown in the figure, the stacking spacer of the present invention includes at least a second, The third and fourth dielectric layers. Among them, the first dielectric layer is a low-dielectric bottom, that is, the aforementioned bottom of the spacer wall. 11 This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) 526592 5 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and the description of the invention () is formed on the semiconductor substrate 100 and is located on the side wall. This is completely + stands at the low level of the interlayer stacking layer. The height is equal to the height of the ancient ancient demon, and it is lower than # 3 μ > It is slightly lower than the conductive layer of the electrode, which is slightly higher than the height of the conductive layer of the gate. The top of the gap wall is: = " Electric bottom 1 12a, and is located on the side of the gate stack layer is composed of, ^ 14a, and low dielectric bottom 112a-the internal partition wall. The first layer is the outside of nitride nitride 116, formed on the side wall of the low-dielectric bottom U2a fish nitrogen top 114a, also Covers the entire internal gap and external gap wall. Formed constant electrical degree: a. Because the dielectric constant of the low dielectric bottom 11 2a is lower than the dielectric number of silicon nitride, it is between the gate conductive layer and the contact window plug 12o. The equivalent permittivity is lower than using only nitrogen cut, so the corresponding equivalent spacer ^ is thicker than silicon nitride. In this way, the capacitance between the gate conductive layer and the contact window plug 120 is caused by the gate sidewall. The coupling can be greatly reduced, and the capacitive coupling between the interlayers can also be greatly reduced. The formation of the silicon nitride top 114a on the low dielectric bottom} a can prevent damage when the low dielectric bottom is formed. . In addition to being applicable to the gate stack layer, the stacked spacer structure of the present invention can also be applied to bit lines to reduce the capacitive coupling effect between the bit lines. Figures 2A-2D are schematic cross-sectional views of another preferred embodiment of the present invention. 12 This paper size applies to China National Standard (CNS) A4 specification (210X297 public copy) 526592 A7 B7 V. Description of invention () (Please read the precautions on the back before filling this page) Please refer to Figure 2A, first provide a semiconductor The substrate 200 is, for example, a single crystal silicon substrate having a < 100 > lattice structure, and a plurality of semiconductor elements, such as a metal-oxide-semiconductor (MOS) transistor, are fabricated thereon. The substrate 200 has a conductive region 202, such as a source / drain region, a conductive pad layer, a conductive wire, or a conductive region of the type. A dielectric layer 210 is formed on the substrate 200, such as a stone oxide layer or other low-dielectric material layers. Next, a bit line is fabricated on the dielectric layer 210 to form a stacked layer of the conductive layer and the cap layer. The manufacturing method is, for example, sequentially forming a conductive layer 212 and a cap layer 214 on the dielectric layer 210. The material of the conductive layer 212 is, for example, polycrystalline stone, Ming, crane, copper, or an alloy thereof. The material of the cap layer 214 is, for example, a silicon nitride layer, a silicon oxynitride layer, or another material layer having a good etching selection ratio for subsequent etching, and a silicon nitride layer is preferred. Then, the required wiring pattern is defined by conventional lithography and etching techniques, and a bit line stacking layer is formed. After the bit line stack layer is formed, a conformal and thin nitride nitride layer 2 1 6 can be selectively formed on the surface, and the thickness is about 3-3 0 nm, so the nitride nitride layer 2 1 6 will cover the bit. The side wall 2 1 5 of the stacking layer of the element line is used as a lining (1 iner layer) ° Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy Please refer to Figure 2B, and then stack on the dielectric layer 2 1 0 and on the bit line A dielectric layer 218 is formed between the layers, and the dielectric layer 218 is slightly higher than the conductive layer 2 1 2. The dielectric layer 2 1 8 is made of a low dielectric constant material. 13 This paper size is applicable to China National Standard (CNS) A4 (210X 297 mm). Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. 526592 5. Description of the invention () And its dielectric constant must be a dielectric constant. If the gate electrode Tg is even s Λ P,], the right top electrode layer of the gate cap layer must be less than 7 by silicon nitride. Dielectric Acoustics 218. $ 田 结构 'then its dielectric constant " electrical layer 2 1 8 The material used for this example is about 4 or other, can also choose other =: its dielectric dielectric material' such as spin coating Glass (s0 person: the number is as low as Dou Bao Shi, Shi, Meng-type polymer (SOP), etc., as for the formation method is not limited to this. Dielectric layer 2): cover the dielectric layer, and then Then, with the average hook rate: Control the rate of the ring rate to reduce your half-best-looking sub-half. ★ Remove the part between the top layer 214 and the bit line stacking layer. Underneath and then on the substrate 20. A dielectric layer 22 is formed on the dielectric layer. The thickness of the dielectric layer must be controlled in order to facilitate the control of the subsequent formation of the dielectric layer 22 °. The selected materials such as nitride cutting and nitrogen oxygen cutting are: The thickness is controlled and the material has a good selection ratio, and it is better to use nitride. The dielectric layer 220 can be, for example, an atmospheric fossilized layer formed by chemical vapor deposition (CVD). Its thickness control is much better than that of oxidized stone or other dielectric layers. Therefore, a spacer with a smaller width can be obtained. Nitrile layer: thickness control up to 5-3 Onm, or even lower. Please refer to FIG. 2C, and then etch back to form the top of the spacer 22a on the side soil 2 1 5 of the bit line stack layer. For example, the top cap layer 214 and the dielectric can be removed using reactive ion etching (RIE). The part on the layer 210 is only the part on the side wall 2 15 of the bit line stacking layer, which is used as a gap wall. 14 This paper size applies to China National Standard (CNS) A4 specifications (210X297 male :: '......... ΜΨ ........., 玎 ......... (Please read the precautions on the back before filling this page) 526592 A7 B7 V. Description of the invention () Then use the top 220 of the partition wall as the cover, and the exposed part of the dielectric layer 21 8 under the etching is only on the side The part on i 215 forms the bottom wall 218a of the gap wall, which is composed of the bottom wall 218a of the gap wall and the top wall 22a of the inner wall. Then, the dielectric layer 21 0 underneath is etched until the conductive area 202 is exposed. To form a contact window opening 222. Since the material selected for the cap layer 21 and the top of the spacer 22a has a good selectivity for the dielectric layer 218, the top 22a of the spacer is in the etching medium. The electrical layers 2 1 8 and 2 10 have very good losses, and do not cause damage to the bit line conductive layer 2 1 2. Mingmai according to Figure 2D, and then the internal gap wall (including the top 22 0a of the gap wall and the gap) An outer gap wall 224 is formed on the side wall of the wall bottom 21 8a), and extends to cover the side wall 221 of the contact window opening 222. This outer space The wall 224 selects a material that has a better etching selection ratio for the subsequently deposited dielectric layer (such as a silicon oxide layer), for example, silicon nitride. The method for forming the external spacer 224, for example, first forms a layer of nitrogen on the substrate 200 The silicon layer covers the internal gap wall and the side wall 221 and bottom of the contact window opening 222, and is then engraved to remove the parts on the top cover layer 214 and the bottom of the opening 222 to form the required external gap wall 224, covering The internal gap wall and the side wall 221 of the opening a. The conductive material is then filled in the opening 222 to form 2 contact window plugs 2 2 6 and electrically connected to the conductive area 2 02. Please refer to FIG. 2D again, After the above process, another 15 papers of the present invention will be formed. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling out this page}-Staff Printed by Consumer Cooperatives. 5 Printed by Consumers' Cooperatives, Intellectual Property Office, Ministry of Economic Affairs.
526592 、發明説明（） 一較佳實施例之堆疊間隙壁結構。在此 ® B〇 1土只施例中，土奋 f間隙壁結構係形成於位元線堆疊層之側壁上，y1堆 述，位元線堆疊層包括導電層2丨2與頂蓋屏 々别所 蓋層214為第-介電層。如圖所示，本發；…二中頂 結構至少包括第二、第三與第四介電層。其中，二壁 層為-低介電底部’即前述之間隙壁底部;、18a:係：2 介電層21〇上，且位於位元線堆疊層 ^成於 _x.. 上'’此低介雷 底邛21 8a之高度等於或高於導電層212 .心回度，且較佳县 略尚於閘極導電層之高度。第三介電# _ 示，丨电層為虱化矽頂部，即 刖述之間隙壁頂部220a，係形成於低電底部21。上，且位 於位元線堆疊層之侧壁上，由此氮化石夕頂部22〇a與二 底部218a組成内部間隙壁。第四介電層為氮化矽外部 224 ’係形成於氮化矽頂部22〇a與低介電底部η。之側壁 上，而且延伸至位在低介電底部218a邊緣底下之接觸窗： 口 222之側壁221，形成一外部間隙壁。 由於低介電底部218a之介電常數低於氮化矽之介電常 數’因此在導電層2 1 2與接觸窗插塞2 2 6之間的等效介電 常數比單純使用氮化矽更低，因此對應的等效間隙壁厚度 比氮化石夕更厚。如此，在導電層2丨2與接觸窗插塞226之 間所造成的電容耦核可大幅地降低，而且亦可降低位元線 之間的電容搞合。此外，在接觸窗開口 2 2 2的側壁2 2 1上 形成氮化矽間隙壁224可避免接觸窗開口 222受到蝕刻液 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐） '.........餐.........#.........蠢· (請先閲讀背面之注意事項再填寫本頁} 526592 A7 B7 五、發明説明（） 的侵I虫而擴大。 綜上所述，本發明提供一種堆疊間隙壁結構及製程， 在間隙壁結構中埋入低介電材質，可降低間隙壁兩側之間 的耦合電容，而且在製作過程中仍具有良好的保護效果， 避免導電層受到破壞，而影響整體電性。 如熟悉此技術之人員所暸解的，以上所述僅為本發明 之較佳實施例而已，並非用以限定本發明之申請專利範 圍；凡其它未脫離本發明所揭示之精神下所完成之等效改 變或修飾，均應包含在下述之申請專利範圍内。 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐)526592, description of the invention () a stacked spacer structure of a preferred embodiment. In this ® B〇1 soil example, the soil wall structure is formed on the side wall of the bit line stacking layer, and y1 is stacked. The bit line stacking layer includes a conductive layer 2 and a cover screen. The capping layer 214 is a first dielectric layer. As shown in the figure, the present invention; ... the second top structure includes at least second, third and fourth dielectric layers. Among them, the second wall layer is-a low dielectric bottom, that is, the bottom of the aforementioned spacer; 18a: Department: 2 on the dielectric layer 21, and is located on the bit line stack layer ^ 成 上 _x .. The height of the low-medium lightning base 邛 21 8a is equal to or higher than the conductive layer 212. The cardiac resilience is better than the height of the gate conductive layer. The third dielectric # _ shows that the electric layer is the top of the siliconized silicon, that is, the top 220a of the spacer wall described below, which is formed on the low-electric bottom 21. And is located on the side wall of the bit line stacking layer, so that the top 22a of the nitride nitride and the bottom 218a form an internal partition wall. The fourth dielectric layer is a silicon nitride outer layer 224 'which is formed on the silicon nitride top 22a and the low dielectric bottom η. On the side wall and extending to the contact window located below the edge of the low-dielectric bottom 218a: the side wall 221 of the opening 222 forms an external gap wall. Since the dielectric constant of the low dielectric bottom 218a is lower than that of silicon nitride, the equivalent dielectric constant between the conductive layer 2 1 2 and the contact window plug 2 2 6 is more than that of using silicon nitride alone. It is low, so the corresponding equivalent wall thickness is thicker than nitride nitride. In this way, the capacitive coupling core caused between the conductive layer 2 and the contact window plug 226 can be greatly reduced, and the capacitance between the bit lines can be reduced. In addition, a silicon nitride spacer 224 is formed on the side wall 2 2 1 of the contact window opening 2 2 2 to prevent the contact window opening 222 from being subjected to the etching solution. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm). ........ Meal ......... # ......... Stupid (Please read the notes on the back before filling out this page} 526592 A7 B7 V. Description of the invention In summary, the present invention provides a stacked bulkhead structure and manufacturing process, and embedding a low dielectric material in the bulkhead structure can reduce the coupling capacitance between the two sides of the bulkhead, and During the manufacturing process, it still has a good protection effect to avoid the conductive layer from being damaged, which affects the overall electrical properties. As will be understood by those skilled in the art, the above is only a preferred embodiment of the present invention and is not intended to Limit the scope of patent application for this invention; all other equivalent changes or modifications made without departing from the spirit disclosed by this invention should be included in the scope of patent application below. (Please read the precautions on the back before filling in this Page) Employee Consumer Cooperatives, Bureau of Intellectual Property, Ministry of Economic Affairs This paper applies system-scale Chinese National Standard (CNS) A4 size (210X 297 mm)