CN113540025A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113540025A
CN113540025A CN202010291431.3A CN202010291431A CN113540025A CN 113540025 A CN113540025 A CN 113540025A CN 202010291431 A CN202010291431 A CN 202010291431A CN 113540025 A CN113540025 A CN 113540025A
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layer
conductive
gap
forming
semiconductor structure
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成国良
张�浩
郭雯
段超
许增升
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: providing a first conductive layer; forming a dielectric layer on the first conductive layer, wherein the dielectric layer is internally provided with an opening, and the opening is exposed out of the surface of the first conductive layer; forming a second conducting layer in the opening, wherein the top surface of the second conducting layer is flush with or lower than the top surface of the dielectric layer; and forming a gap layer on the surface of the side wall of the opening, wherein the gap layer is positioned between the dielectric layer and the second conductive layer. The semiconductor structure formed by the method has better performance.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in the integrated circuit is continuously reduced, so that the operation speed of the whole integrated circuit can be effectively increased. As the size requirements of the components become smaller, the size of the conductive structures formed accordingly becomes smaller.
The forming method of the conductive structure comprises the following steps: providing a semiconductor substrate; forming a first dielectric layer on a semiconductor substrate, wherein the first dielectric layer is internally provided with a first opening; forming a first plug within the first opening; after the first plug is formed, forming a second dielectric layer on the surface of the first plug and the surface of the first dielectric layer; forming a second opening in the second dielectric layer; after forming the second opening, a second plug is formed within the second opening. The first and second plugs form a conductive structure. To reduce the resistance of conductive structures of increasingly smaller dimensions, materials of lower resistivity are used to form the conductive structures.
However, the performance of the semiconductor devices formed by the prior art needs to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of the formed semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: a semiconductor structure, comprising: a first conductive layer; a dielectric layer on the first conductive layer, wherein the dielectric layer has an opening therein, and the opening exposes the surface of the first conductive layer; the second conducting layer is positioned in the opening, and the top surface of the second conducting layer is flush with or lower than the top surface of the dielectric layer; and the gap layer is positioned on the surface of the side wall of the opening and is positioned between the dielectric layer and the second conductive layer.
Optionally, the material of the gap layer is a conductive material.
Optionally, the material of the gap layer includes: tungsten.
Optionally, the top surface of the second conductive layer is lower than the top surface of the dielectric layer.
Optionally, the method further includes: and the third conducting layer is positioned on the surface of the second conducting layer, and the opening is filled with the second conducting layer and the third conducting layer.
Optionally, the material of the gap layer is the same as the material of the third conductive layer.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a first conductive layer; forming a dielectric layer on the first conductive layer, wherein the dielectric layer is internally provided with an opening, and the opening is exposed out of the surface of the first conductive layer; forming a second conducting layer in the opening, wherein the top surface of the second conducting layer is flush with or lower than the top surface of the dielectric layer; and forming a gap layer on the surface of the side wall of the opening, wherein the gap layer is positioned between the dielectric layer and the second conductive layer.
Optionally, the material of the gap layer is a conductive material.
Optionally, the material of the gap layer includes: tungsten.
Optionally, the method for forming the gap layer includes: forming a gap material layer on the surface of the side wall of the opening and the surface of the top of the dielectric layer, wherein the gap material layer is positioned between the second conductive layer and the dielectric layer; and flattening the gap material layer until the surface of the dielectric layer is exposed, and forming a gap layer on the surface of the side wall of the opening.
Optionally, the top surface of the second conductive layer is lower than the top surface of the dielectric layer.
Optionally, the method further includes: after forming the gap material layer and before flattening the gap material layer, forming a third conductive material layer on the surface of the gap material layer; and flattening the gap material layer and the third conductive material layer until the top surface of the dielectric layer is exposed, so that the third conductive material layer forms a third conductive layer, the gap material layer forms a gap layer, and the second conductive layer and the third conductive layer fill the opening.
Optionally, the forming method of the gap material layer includes: forming an initial gap material layer on the surface of the side wall of the opening and the surface of the top of the dielectric layer; and modifying the initial gap material layer to form the gap material layer.
Optionally, in the process of performing modification treatment on the initial gap material layer, the third conductive material layer is further formed.
Optionally, the material of the initial gap material layer includes: a semiconductor material or a conductive material.
Optionally, the semiconductor material includes: silicon.
Optionally, the process for forming the initial gap material layer includes: a chemical vapor deposition process; the parameters of the chemical vapor deposition process include: the introduced gas comprises SiH4The gas flow rate ranges from 0 to 1000 ml/min and the temperature ranges from 300 to 500 ℃.
Optionally, the modification treatment comprises a displacement reaction.
Optionally, the process parameters for performing modification treatment on the initial gap material layer include: the gas introduced comprises WF6The gas flow rate ranges from 0 to 1000 ml/min and the temperature ranges from 300 to 500 ℃.
Optionally, a portion of the initial gap material layer is oxidized to form an oxide layer.
Optionally, the method further includes: and after the initial gap material layer and before the third conductive material layer is formed, removing the oxide layer.
Optionally, the process for removing the oxide layer includes: an ion etching process; the parameters of the ion etching process comprise: the gas introduced comprises argon, the flow rate of the gas ranges from 0 standard ml/min to 1000 standard ml/min, the radio frequency power ranges from 0 watt to 2000 watts, and the bias power ranges from 0 watt to 1000 watts.
Optionally, the process for planarizing the gap material layer includes: and (5) carrying out a chemical mechanical polishing process.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, after the second conductive layer is formed in the opening, the gap layer is formed on the surface of the side wall of the opening and is positioned between the second conductive layer and the dielectric layer. The gap layer is filled in the space between the second conducting layer and the dielectric layer, so that the gap between the second conducting layer and the dielectric layer is effectively reduced, and therefore in the subsequent planarization process, the etching solution adopted by planarization can be reduced to pass through the gap between the second conducting layer and the side wall of the dielectric layer, so that the first conducting layer at the bottom of the opening is subjected to etching damage, the protection of the first conducting layer material is realized, the contact resistance between the first conducting layer and the second conducting layer is improved, and the performance of the formed semiconductor structure is better.
Further, the initial gap material layer is subjected to modification treatment to form a gap material layer. The modification treatment is a chemical reaction process, which is beneficial to improving the adhesion of the formed gap material layer to the second conducting layer and the dielectric layer, further reducing the gaps between the second conducting layer and the dielectric layer and between the third conducting material layer and the dielectric layer, further protecting the first conducting material layer, improving the contact resistance between the first conducting layer and the second conducting layer and ensuring that the formed semiconductor structure has better performance.
Furthermore, by removing the partially oxidized gap material layer, the oxidized gap material layer is prevented from influencing the size of the top of the opening, so that the key sizes of the gap layer and the third conductive layer in the opening are not influenced, and the stability of the performance of the formed semiconductor structure is improved.
In the semiconductor structure provided by the technical scheme of the invention, the surface of the side wall of the opening is provided with the gap layer, and the gap layer is positioned between the dielectric layer and the second conductive layer. The gap layer is filled in the space between the second conducting layer and the dielectric layer, so that the gap between the second conducting layer and the dielectric layer is effectively reduced, and therefore in the subsequent planarization process, the etching solution adopted by planarization can be reduced to pass through the gap between the second conducting layer and the side wall of the dielectric layer, so that the first conducting layer at the bottom of the opening is subjected to etching damage, the protection of the first conducting layer material is realized, the contact resistance between the first conducting layer and the second conducting layer is improved, and the performance of the formed semiconductor structure is better.
Drawings
FIGS. 1-5 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 6 to 11 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Fig. 12 to 15 are schematic structural views of steps of a method for forming a semiconductor structure according to another embodiment of the present invention.
Detailed Description
As described in the background, semiconductor structures have poor performance.
The reason for the poor performance of the semiconductor structure will be described in detail below with reference to the accompanying drawings, and fig. 1 to 5 are schematic structural views of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 has a first conductive layer 110 therein, the substrate 100 exposes a surface of the first conductive layer 110, the substrate 100 has a dielectric layer 120 on a surface thereof, the dielectric layer 120 has an opening 130 therein, and the opening 130 exposes a surface of the first conductive layer 110.
Referring to fig. 2, a second conductive layer 140 is formed in the opening 130, and a top surface of the second conductive layer 140 is lower than a top surface of the dielectric layer 120.
Referring to fig. 3, the second conductive layer 140 is subjected to an ion etching process to form a third conductive layer 150 on the exposed sidewall surface of the opening 130.
Referring to fig. 4, after the second conductive layer 140 and the third conductive layer 150 are formed, a fourth conductive material film 160 is formed on the surfaces of the second conductive layer 140 and the third conductive layer 150 and the surface of the dielectric layer 120 in the opening 130, and the opening 130 is filled with the fourth conductive material film 160.
Referring to fig. 5, the fourth conductive material film 160 is planarized until reaching the surface of the dielectric layer 110, and a fourth conductive layer 161 is formed in the opening 130.
In the above method, the third conductive layer 150 is formed by performing ion bombardment on the second conductive layer 140, so that a part of the material of the second conductive layer 140 is deposited on the exposed sidewall of the opening 130, and the third conductive layer 150 is favorable for increasing the adhesion between the subsequent fourth conductive layer 161 and the sidewall of the dielectric layer 120, thereby reducing the loss of the etching solution used in the subsequent planarization process to the first conductive layer 110 in the substrate 100 through the gap a (shown in fig. 5) between the sidewalls of the second conductive layer 140 and the dielectric layer 120 and between the fourth conductive material film 160 and the dielectric layer 120.
However, the third conductive layer 150 still cannot effectively prevent the first conductive layer 110 in the substrate 100 from being damaged by the etching solution passing through the gaps between the sidewalls of the second conductive layer 140 and the dielectric layer 120 and between the fourth conductive material film 160 and the dielectric layer 120 during the planarization process, so that the contact resistance between the second conductive layer 140 and the first conductive layer 110 is still large, and the performance of the formed semiconductor structure is poor. Meanwhile, the ion bombardment process not only bombards the second conductive layer 140, but also bombards the dielectric layer 120, which results in a reduction in the sidewall material of the dielectric layer 120, and thus a reduction in the critical dimension of the fourth conductive layer 161 located in the opening 130, resulting in a poor stability of the formed semiconductor structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 6, a first conductive layer 210 is provided.
Specifically, in the present embodiment, the first conductive layer 210 is located in the substrate 200, and the substrate 200 exposes the surface of the first conductive layer 210.
In the present embodiment, the substrate 200 is a single-layer substrate.
In other embodiments, the substrate may also be an SOI substrate, which may be a double layer of an insulating substrate plus a top single crystal silicon layer, or a sandwich structure with an insulating thin layer as an intermediate layer.
The materials of the substrate 200 include: silicon, germanium, silicon on insulator or germanium on insulator. Accordingly, the material of the substrate comprises: germanium, silicon on insulator or germanium on insulator.
Referring to fig. 7, a dielectric layer 220 is formed on the first conductive layer 210, wherein the dielectric layer 220 has an opening 221 therein, and the opening 221 exposes the surface of the first conductive layer 210.
The dielectric layer 220 provides support for the subsequent formation of the conductive structure, and plays an electrical isolation role for different devices.
The forming method of the dielectric layer 220 and the opening 221 includes: forming a dielectric material film (not shown) on the surface of the substrate 200; forming a mask layer (not shown in the figure) on the surface of the medium material film, wherein the mask layer exposes part of the surface of the medium material film; and etching the dielectric material film by taking the mask layer as a mask until the surface of the first conductive layer 210 is exposed, so as to form the dielectric layer 220 and an opening 221 positioned in the dielectric layer 220.
The dielectric layer 220 is made of an insulating material, and includes: one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon nitride boride, silicon oxycarbonitride or silicon oxynitride.
In this embodiment, the dielectric layer 220 is made of silicon oxide.
Referring to fig. 8, a second conductive layer 230 is formed in the opening 221, wherein a top surface of the second conductive layer 230 is lower than a top surface of the dielectric layer 220.
The material of the second conductive layer 230 includes: a metal, the metal comprising: copper, tungsten, aluminum, titanium nitride, or tantalum.
In this embodiment, the material of the second conductive layer 230 is tungsten.
The forming process of the second conductive layer 230 includes: selective chemical vapor deposition process.
Because the first conductive layer 210 and the dielectric layer 220 are made of different materials and have different surface characteristics, a selective chemical deposition process is adopted to form the second conductive layer 230 on the surface of the first conductive layer 210 at the bottom of the opening 221, and simultaneously, no material is deposited on the surface of the dielectric layer 220, so that the deposited material can be prevented from closing at the top of the opening 221 in advance, and a cavity is prevented from being generated in the formed second conductive layer 230, and the performance of the formed semiconductor structure is better.
In other embodiments, the top surface of the second conductive layer is flush with the top surface of the dielectric layer.
Next, an aperture material layer is formed on the sidewall surface of the opening 221 and the top surface of the dielectric layer 220, and the aperture material layer is located between the second conductive layer 230 and the dielectric layer 220, and please refer to fig. 9 to fig. 10 in the process of forming the aperture material layer.
Referring to fig. 9, an initial gap material layer 240 is formed on the sidewall surface of the opening 221 and the top surface of the dielectric layer 220.
Specifically, in this embodiment, the initial gap material layer 240 is also located on the top surface of the second conductive layer 230.
The material of the initial slot material layer 240 includes: a semiconductor material or a conductive material.
In this embodiment, the material of the initial gap material layer 240 is a semiconductor material, silicon.
In this embodiment, the process of forming the initial gap material layer 240 includes: a chemical vapor deposition process; the parameters of the chemical vapor deposition process include: the introduced gas comprises SiH4The gas flow rate ranges from 0 to 1000 ml/min and the temperature ranges from 300 to 500 ℃.
Referring to fig. 10, a modification process is performed on the initial gap material layer 240, so that the gap material layer 241 is formed on the initial gap material layer 240.
In this embodiment, during the modification process of the initial gap material layer 240, a third conductive material layer 250 is further formed.
With continued reference to fig. 10, a third conductive material layer 250 is formed on the surface of the gap material layer 241.
The material of the gap material layer 241 is a conductive material.
The material of the third conductive material layer 250 is a conductive material.
In this embodiment, the gap material layer 241 and the third conductive material layer 250 are made of the same material and are both tungsten.
The third conductive material layer 250 and the gap material layer 241 are made of the same material and are both tungsten.
The modification treatment comprises a displacement reaction.
In this embodiment, the process parameters for performing the modification treatment on the initial gap material layer 240 include: the gas introduced comprises WF6The gas flow rate ranges from 0 to 1000 ml/min and the temperature ranges from 300 to 500 ℃.
It should be noted that the modification process selectively deposits and forms the third conductive material layer 250 by stacking the gap material layer 241 on the surface layer by layer.
In this embodiment, the material of the initial gap material layer 240 is Si, and the gas introduced by the modification treatment is WF6Introduced gas WF6Can react with Si capable of converting W element from WF6Middle displacement to generate W and SiF4。
By performing a modification process on the initial gap material layer 240, a gap material layer 241 is formed. The modification treatment is a chemical reaction process, which is beneficial to improving the adhesion of the formed gap material layer 241 to the second conductive layer 230 and the dielectric layer 220, further reducing the gaps between the second conductive layer 230 and the dielectric layer 220 and between the third conductive material layer 250 and the dielectric layer 220, and further protecting the material of the first conductive layer 210, so that the contact resistance between the first conductive layer 210 and the second conductive layer 230 is improved, and the performance of the formed semiconductor structure is better.
In this embodiment, after forming the third conductive material layer 250, before subsequently planarizing the gap material layer 241 and the third conductive material layer 250, the method further includes: and forming a buffer layer 260 on the surface of the third conductive material layer 250, and in the process of planarizing the gap material layer 241 and the third conductive material layer 250, also planarizing the buffer layer 260.
The buffer layer 260 has the function of forming a thicker film layer on the surface of the dielectric layer 220, so as to play a buffer role in the subsequent planarization process and improve the stability of the process.
The buffer layer 260 has a single-layer structure or a multi-layer structure.
In this embodiment, the buffer layer 260 has a single-layer structure.
The formation process of the buffer layer 260 includes: chemical vapor deposition process.
In other embodiments, the buffer layer is a multi-layer structure, and the material of the buffer layer is titanium nitride and tungsten.
Referring to fig. 11, the gap material layer 241 and the third conductive material layer 250 are planarized until the top surface of the dielectric layer 220 is exposed, so that the third conductive material layer 250 forms a third conductive layer 251, the gap material layer 241 forms a gap layer 242, and the second conductive layer 230 and the third conductive layer 251 fill the opening 221.
In this embodiment, since the third conductive material layer 250 further has a buffer layer 260 on the surface, before the gap material layer 241 and the third conductive material layer 250 are planarized, the planarization process further removes the buffer layer 260 to expose the surface of the third conductive material layer 250.
The process of planarizing the gap material layer 241 and the third conductive material layer 250 includes: and (5) carrying out a chemical mechanical polishing process.
The chemical mechanical polishing process adopts polishing solution.
After forming the second conductive layer 230 and the third conductive layer 251 in the opening 221, a gap layer 242 is formed on the sidewall surface of the opening 221, and the gap layer 242 is located between the second conductive layer 230, the third conductive layer 251 and the dielectric layer 220. The gap layer 242 is filled in the space between the second conductive layer 230, the third conductive layer 251 and the dielectric layer 220, so that the gap between the second conductive layer 230, the third conductive layer 251 and the dielectric layer 220 is effectively reduced, and therefore, in the subsequent planarization process, the etching solution adopted by planarization can be reduced to pass through the gap between the second conductive layer 230, the third conductive layer 251 and the side wall of the dielectric layer 220, so that the first conductive layer 210 at the bottom of the opening 221 is damaged by etching, the material of the first conductive layer 210 is protected, the contact resistance between the first conductive layer 210 and the second conductive layer 230 and the third conductive layer 251 is improved, and the performance of the formed semiconductor structure is better.
Accordingly, the present invention further provides a semiconductor structure formed by the above method, with continued reference to fig. 11, including: a first conductive layer 210; a dielectric layer 220 located on the first conductive layer 210, wherein an opening 221 is formed in the dielectric layer 220, and the opening 221 exposes the surface of the first conductive layer 210; a second conductive layer 230 located in the opening 221, wherein a top surface of the second conductive layer 230 is flush with or lower than a top surface of the dielectric layer 220; and a gap layer 242 disposed on the sidewall surface of the opening 221, wherein the gap layer 242 is disposed between the dielectric layer 220 and the second conductive layer 230.
The material of the gap layer 242 is a conductive material.
The material of the slit layer 242 includes: tungsten.
In this embodiment, the top surface of the second conductive layer 230 is lower than the top surface of the dielectric layer 220.
The semiconductor structure further includes: and a third conductive layer 251 located on the surface of the second conductive layer 230, wherein the second conductive layer and the third conductive layer fill the opening.
The material of the second conductive layer 230 includes: a metal, the metal comprising: copper, tungsten, aluminum, titanium nitride, or tantalum. In this embodiment, the material of the second conductive layer 230 is tungsten.
The material of the third conductive layer 251 includes: a metal, the metal comprising: copper, tungsten, aluminum, titanium nitride, or tantalum.
In this embodiment, the material of the third conductive layer 251 is tungsten.
The material of the slit layer 241 is the same as the material of the third conductive layer 251.
In this embodiment, the materials of the gap layer 241 and the third conductive layer 251 are both tungsten.
Fig. 12 to 15 are schematic structural views of steps of a method for forming a semiconductor structure according to another embodiment of the present invention. The difference between the present embodiment and the foregoing embodiment is that after the initial gap material layer 240 is formed and before the initial gap material layer 240 is modified, the initial gap material layer 240 may be exposed to an external environment, which may cause a portion of the initial gap material layer 240 to be oxidized to form an oxide layer, and thus, the oxide layer needs to be removed. This embodiment continues the description of the method for forming a semiconductor structure on the basis of the above-described embodiments.
With reference to fig. 12, with reference to fig. 9, after the initial gap material layer 240 is formed, a portion of the initial gap material layer 240 is oxidized to form an oxide layer 341.
When the initial gap material layer 240 needs to be switched in different machines, it is inevitably exposed to the external atmospheric environment, so that a portion of the initial gap material layer 240 is oxidized, thereby forming an oxide layer 341, and the oxide layer 341 may cause electrical isolation and affect the conductivity of the formed semiconductor structure.
Referring to fig. 13, the oxide layer 341 is removed.
The process of removing the oxide layer 341 includes: an ion etching process; the parameters of the ion etching process comprise: the gas introduced comprises argon, the flow rate of the gas ranges from 0 standard ml/min to 1000 standard ml/min, the radio frequency power ranges from 0 watt to 2000 watts, and the bias power ranges from 0 watt to 1000 watts.
It should be noted that after removing a portion of the oxide layer 341, the unoxidized portion of the surface of the initial gap material layer 240 is exposed, and is then modified.
The ion etching process has a large etching selection ratio for the oxide layer 341 and the initial gap material layer 240, so that the oxide layer 341 is removed while the initial gap material layer 240 is not damaged by etching, and therefore, the unoxidized initial gap material layer 240 can protect the dielectric layer 220, the dielectric layer 220 is prevented from being damaged by etching, and the side wall of the dielectric layer 220 is not damaged by etching, that is, the size of the opening 221 in the dielectric layer 220 is kept unchanged, so that the key size of a conductive structure formed in the opening 221 subsequently is kept unchanged, and the stability of the performance of the semiconductor structure is improved.
The dimension refers to a distance in a direction in which the opening 221 is perpendicular to a sidewall surface of the opening 221.
Referring to fig. 14, after removing the oxide layer 341, a modification process is performed on the initial gap material layer 240, so that the gap material layer 342 is formed on the initial gap material layer 240.
The modification processing method is the same as that in the above embodiment, and is not described herein again.
In this embodiment, during the modification process of the initial gap material layer 240, a third conductive material layer 350 is further formed.
With continued reference to fig. 14, a third conductive material layer 350 is formed on the surface of the gap material layer 342.
The material of the gap material layer 342 is the same as the material of the gap material layer 241 in the above embodiments, and is not described herein again.
The third conductive material layer 350 is the same as the third conductive material layer 250 in the above embodiments, and is not described herein again.
It should be noted that the modification process selectively deposits and forms the third conductive material layer 350 by stacking the gap material layer 342 layer by layer.
After removing the oxide layer 341, the initial gap material layer 240 is exposed, and a modification process is performed on the initial gap material layer 240 to form a gap material layer 342. The modification treatment is a chemical reaction process, which is beneficial to improving the adhesion between the formed gap material layer 342 and the dielectric layer 220, further reducing the gap between the second conductive layer 230 and the dielectric layer 220 and the gap between the formed third conductive material layer 350 and the dielectric layer 220, and further protecting the material of the first conductive layer 210, thereby improving the contact resistance between the first conductive layer 210 and the second conductive layer 230, and enabling the performance of the formed semiconductor structure to be better.
In this embodiment, after forming the third conductive material layer 350, before subsequently planarizing the gap material layer 342 and the third conductive material layer 350, the method further includes: a buffer layer 360 is formed on the surface of the third conductive material layer 350, and in the process of planarizing the gap material layer 342 and the third conductive material layer 350, the buffer layer 360 is also planarized.
The buffer layer 360 is the same as the buffer layer 260 in the above embodiments in terms of material and function, and will not be described again.
Referring to fig. 15, the gap material layer 342 and the third conductive material layer 350 are planarized until the top surface of the dielectric layer 220 is exposed, so that the third conductive material layer 350 forms a third conductive layer 351, the gap material layer 342 forms a gap layer 343, and the second conductive layer 230 and the third conductive layer 351 fill the opening 221.
In this embodiment, since the surface of the third conductive material layer 350 further has a buffer layer 360, before the gap material layer 342 and the third conductive material layer 350 are planarized, the planarization process further removes the buffer layer 360 to expose the surface of the third conductive material layer 350.
The process of the planarization process is the same as that in the above embodiment, and is not described herein again.
Accordingly, another embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 15, including: a first conductive layer 210; a dielectric layer 220 located on the first conductive layer 210, wherein an opening 221 is formed in the dielectric layer 220, and the opening 221 exposes the surface of the first conductive layer 210; a second conductive layer 230 located in the opening 221, wherein a top surface of the second conductive layer 230 is flush with or lower than a top surface of the dielectric layer 220; a gap layer 343 is disposed on the sidewall surface of the opening 221, and the gap layer 343 is disposed between the dielectric layer 220 and the second conductive layer 230.
The material of the gap layer 343 is a conductive material.
In this embodiment, the material of the gap layer 343 is tungsten.
In this embodiment, the top surface of the second conductive layer 230 is lower than the top surface of the dielectric layer 220.
The semiconductor structure further includes: a third conductive layer 351 on the surface of the second conductive layer 230, wherein the second conductive layer 230 and the third conductive layer 351 fill the opening.
The material of the second conductive layer 230 includes: a metal, the metal comprising: copper, tungsten, aluminum, titanium nitride, or tantalum.
In this embodiment, the material of the second conductive layer 230 is tungsten.
The material of the third conductive layer 351 includes: a metal, the metal comprising: copper, tungsten, aluminum, titanium nitride, or tantalum.
In this embodiment, the material of the third conductive layer 351 is tungsten.
The material of the gap layer 343 and the material of the third conductive layer 351 are the same.
In this embodiment, the materials of the gap layer 343 and the third conductive layer 351 are both tungsten.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (23)

1. A semiconductor structure, comprising:
a first conductive layer;
a dielectric layer on the first conductive layer, wherein the dielectric layer has an opening therein, and the opening exposes the surface of the first conductive layer;
the second conducting layer is positioned in the opening, and the top surface of the second conducting layer is flush with or lower than the top surface of the dielectric layer;
and the gap layer is positioned on the surface of the side wall of the opening and is positioned between the dielectric layer and the second conductive layer.
2. The semiconductor structure of claim 1, in which a material of the gap layer is a conductive material.
3. The semiconductor structure of claim 2, wherein a material of the gap layer comprises: tungsten.
4. The semiconductor structure of claim 1, wherein a top surface of the second conductive layer is lower than a top surface of the dielectric layer.
5. The semiconductor structure of claim 4, further comprising: and the third conducting layer is positioned on the surface of the second conducting layer, and the opening is filled with the second conducting layer and the third conducting layer.
6. The semiconductor structure of claim 5, in which a material of the gap layer and a material of the third conductive layer are the same.
7. A method of forming a semiconductor structure, comprising:
providing a first conductive layer;
forming a dielectric layer on the first conductive layer, wherein the dielectric layer is internally provided with an opening, and the opening is exposed out of the surface of the first conductive layer;
forming a second conducting layer in the opening, wherein the top surface of the second conducting layer is flush with or lower than the top surface of the dielectric layer;
and forming a gap layer on the surface of the side wall of the opening, wherein the gap layer is positioned between the dielectric layer and the second conductive layer.
8. The method of forming a semiconductor structure of claim 7, wherein a material of the gap layer is a conductive material.
9. The method of forming a semiconductor structure of claim 8, wherein the material of the gap layer comprises: tungsten.
10. The method of forming a semiconductor structure of claim 7, wherein the method of forming the gap layer comprises: forming a gap material layer on the surface of the side wall of the opening and the surface of the top of the dielectric layer, wherein the gap material layer is positioned between the second conductive layer and the dielectric layer; and flattening the gap material layer until the surface of the dielectric layer is exposed, and forming a gap layer on the surface of the side wall of the opening.
11. The method of forming a semiconductor structure of claim 10, wherein a top surface of the second conductive layer is lower than a top surface of the dielectric layer.
12. The method of forming a semiconductor structure of claim 11, further comprising: after forming the gap material layer and before flattening the gap material layer, forming a third conductive material layer on the surface of the gap material layer; and flattening the gap material layer and the third conductive material layer until the top surface of the dielectric layer is exposed, so that the third conductive material layer forms a third conductive layer, the gap material layer forms a gap layer, and the second conductive layer and the third conductive layer fill the opening.
13. The method of forming a semiconductor structure of claim 10, wherein the method of forming the gap material layer comprises: forming an initial gap material layer on the surface of the side wall of the opening and the surface of the top of the dielectric layer; and modifying the initial gap material layer to form the gap material layer.
14. The method of claim 13, wherein said third conductive material layer is further formed during said modifying of said initial gap material layer.
15. The method of forming a semiconductor structure of claim 10, wherein the material of the initial gap material layer comprises: a semiconductor material or a conductive material.
16. The method of forming a semiconductor structure of claim 15, wherein the semiconductor material comprises: silicon.
17. The method of forming a semiconductor structure of claim 16, wherein the process of forming the initial slot material layer comprises: a chemical vapor deposition process; the parameters of the chemical vapor deposition process include: the introduced gas comprises SiH4The gas flow rate ranges from 0 to 1000 ml/min and the temperature ranges from 300 to 500 ℃.
18. The method of forming a semiconductor structure of claim 13, wherein the modification treatment comprises a displacement reaction.
19. The method of claim 18, wherein the process parameters for modifying the initial gap material layer comprise: the gas introduced comprises WF6The gas flow rate ranges from 0 to 1000 ml/min and the temperature ranges from 300 to 500 ℃.
20. The method of forming a semiconductor structure of claim 13, wherein a portion of said initial gap material layer is oxidized to form an oxide layer.
21. The half of claim 20Guide tubeThe method for forming a bulk structure is characterized by further comprising: and after the initial gap material layer and before the third conductive material layer is formed, removing the oxide layer.
22. The method of claim 15, wherein the removing the oxide layer comprises: an ion etching process; the parameters of the ion etching process comprise: the gas introduced comprises argon, the flow rate of the gas ranges from 0 standard ml/min to 1000 standard ml/min, the radio frequency power ranges from 0 watt to 2000 watts, and the bias power ranges from 0 watt to 1000 watts.
23. The method of forming a semiconductor structure of claim 10, wherein planarizing the layer of gap material comprises: and (5) carrying out a chemical mechanical polishing process.
CN202010291431.3A 2020-04-14 2020-04-14 Semiconductor structure and forming method thereof Pending CN113540025A (en)

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JPH0817921A (en) * 1994-06-30 1996-01-19 Hitachi Ltd Manufacture of semiconductor device
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