CN103094192A - Forming method of semiconductor device - Google Patents
Forming method of semiconductor device Download PDFInfo
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- CN103094192A CN103094192A CN2011103406193A CN201110340619A CN103094192A CN 103094192 A CN103094192 A CN 103094192A CN 2011103406193 A CN2011103406193 A CN 2011103406193A CN 201110340619 A CN201110340619 A CN 201110340619A CN 103094192 A CN103094192 A CN 103094192A
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Abstract
An embodiment of the invention provides a forming method of a semiconductor device. The forming method of the semiconductor device comprises that a semiconductor substrate is provided, wherein an inter-lamination dielectric layer is formed on the surface of the semiconductor substrate and is provided with a groove; partial inter-lamination of the lateral wall of the groove is oxidized to form an oxidation layer; an oxidation layer with partial thickness is close to the lateral wall of the groove and is nitrided to form a protective layer of the lateral wall of the groove and a sacrificial layer between the inter-lamination dielectric layer and the protective layer; after the protective layer is formed, the groove is filled up to form electric leads on the same level with the surface of the inter-lamination dielectric layer; and the sacrificial layer is removed to form an air gap. The forming method of the semiconductor device can form the air gap with good uniformity, effectively reduces an effective K value of the interconnecting layer, can not damage the electric leads, and improves performance of the semiconductor device in a semiconductor circuit.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of formation method of semiconductor device.
Background technology
Along with semiconductor industry enters high-performance and multi-functional integrated circuit New Times, in integrated circuit, the density of element can increase thereupon, and the spacing between component size and part or element can be dwindled thereupon.Will reach above-mentioned purpose in the past, only be subject to the ability of photoetching technique definition structure, in prior art, the geometric properties with element of reduced size has produced new limiting factor.For example, when the distance between conductive pattern was dwindled, the electric capacity that any two adjacent conductive patterns produce (for the function in order to the dielectric constant K of the insulating material that separates the distance between conductive pattern) can increase.The electric capacity of this increase can cause the capacitive coupling between conductor to rise, and consumes and improves resistance-capacitance (RC) time constant thereby increase electric power.Therefore, whether semiconductor integrated circuit performance and function can constantly improve and depend on the material with low-k of developing.
Because the material with lowest dielectric constant is air (k=1.0), usually can forms the air gap and further reduce the interior effective K value of interconnection layer.The formation method of semiconductor device of the prior art comprises:
Please refer to Fig. 1, Semiconductor substrate 100 is provided; Form the etching stop layer 101 that covers described Semiconductor substrate 100; Form the interlayer dielectric layer 103 that covers described etching stop layer 101; Formation is positioned at the patterned photoresist layer 105 on described interlayer dielectric layer 103 surfaces;
Please refer to Fig. 2, take described patterned photoresist layer 105 as mask, the described interlayer dielectric layer 103 of etching and etching stop layer 101 form groove 107;
Please refer to Fig. 3, remove described patterned photoresist layer, expose described interlayer dielectric layer 103 surfaces; After removing described patterned photoresist layer, adopt depositing operation to form the sacrifice layer 109 that covers described groove 107 sidewalls;
Please refer to Fig. 4, filled conductive metal in the described groove forms metal wire 111;
Please refer to Fig. 5, remove described sacrifice layer, form air gap 113.
Yet, the poor-performing of semiconductor device in semiconductor integrated circuit that adopts prior art to form.
Manyly please refer to about the formation method at semiconductor device the United States Patent (USP) that publication number is US20110018091.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor device of semiconductor integrated circuit better performances.
For addressing the above problem, the invention provides a kind of formation method of semiconductor device, comprising:
Semiconductor substrate is provided; Formation is positioned at the interlayer dielectric layer of described semiconductor substrate surface, and described interlayer dielectric layer has groove;
The part interlayer dielectric layer of the described trenched side-wall of oxidation forms oxide layer;
Described oxide layer near the segment thickness of trenched side-wall is carried out nitrogen treatment, form at the protective layer of described trenched side-wall, sacrifice layer between described interlayer dielectric layer and protective layer;
After described protective layer to be formed, fill the conductor wire of described groove formation and described interlayer dielectric layer flush;
Remove described sacrifice layer, form the air gap.
Alternatively, the material of described oxide layer is SiO
2
Alternatively, the gas of the part interlayer dielectric layer of the described trenched side-wall of oxidation employing is O
2, O
3Or CO
2
Alternatively, the temperature conditions of the part interlayer dielectric layer of the described trenched side-wall of oxidation is: more than or equal to 150 ℃.
Alternatively, the technique of the part interlayer dielectric layer of the described trenched side-wall of oxidation employing is plasma oxidation process.
Alternatively, the formation technique of described protective layer is plasma nitridation process.
Alternatively, the gas of described nitrogen treatment employing is NH
3, N
2, NO or NO
2In a kind of.
Alternatively, the material of described protective layer is SiN.
Alternatively, the width of described protective layer is less than 1/2 of the width of described oxide layer.
Alternatively, the width of described sacrifice layer is greater than 1/10 of minimum range between adjacent two grooves, and less than 3/7 of minimum range between adjacent two grooves.
Alternatively, the technique of removing described sacrifice layer is wet-etching technology, and the chemical reagent that described wet-etching technology adopts comprises hydrofluoric acid.
Alternatively, described groove forms by the Damascus technics of free hand drawing shape or dual damascene figure.
Alternatively, the material of described interlayer dielectric layer is the K value less than 3.0 low-K dielectric material.
Alternatively, described low-K dielectric material comprises C, Si, O and H element.
Alternatively, also comprise: form across described air gap, and cover the insulating barrier of described interlayer dielectric layer and protective layer.
Compared with prior art, embodiments of the invention have the following advantages:
In embodiments of the invention, the described oxide layer near the segment thickness of trenched side-wall is carried out nitrogen treatment, form at the protective layer of described trenched side-wall, sacrifice layer between described interlayer dielectric layer and protective layer.Described sacrifice layer is for follow-up formation air gap; described protective layer can be without prejudice in the process that forms the air gap for the protection of conductor wire; and the quality of the air gap that forms is good; reduced to a greater extent the effective K value in the interconnection layer; reduce the RC effect, improved the semiconductor integrated circuit performance.
Description of drawings
Fig. 1-Fig. 5 is the cross-sectional view of the forming process of prior art semiconductor device;
Fig. 6 is the structural profile structural representation of the semiconductor device of one embodiment of the invention formation;
Fig. 7 is the schematic flow sheet of formation method of the semiconductor device of the embodiment of the present invention;
Fig. 8-Figure 13 is the cross-sectional view of forming process of the semiconductor device of another embodiment of the present invention.
Embodiment
Just as stated in the Background Art, the poor-performing of semiconductor device in semiconductor integrated circuit of prior art formation.
Please continue with reference to figure 5, after research, the inventor finds that the reason of prior art semiconductor integrated circuit poor-performing is because the interlayer dielectric layer 103 between adjacent two grooves is more, causes the effective K value in interconnection layer higher caused.
The inventor finds: adopt the sidewall formation sacrifice layer of oxidation groove 107 can reduce processing step if do not adopt depositing operation, please refer to Fig. 2, when adopting cineration technics to remove described patterned photoresist layer 105 (please refer to Fig. 2), the interlayer dielectric layer 103 of oxidation groove 107 sidewalls forms sacrifice layer, afterwards, at the interior filled conductive metal of described groove 107 and remove sacrifice layer and form the air gap, can effectively reduce the effective K value in interconnection layer.
yet, the inventor finds, please refer to Fig. 6, if in oxidation removal photoresist (not indicating), the described interlayer dielectric layer 103 of oxidation forms sacrifice layer, remove again described sacrifice layer and form air gap 115, photoresist is oxidized can form the sidewall that a kind of polymer (polyma) 110 is attached to groove, described have the width of the sacrifice layer that polymer 110 adheres to the place less than not having polymer 110 to adhere to the width of the sacrifice layer at place, it is the homogeneity of the width of the existence of described polymer 110 sacrifice layer that affected follow-up formation, cause the homogeneity of width of the air gap 115 of follow-up formation to be affected, thereby affected the semiconductor integrated circuit performance.
After further research, the inventor provides a kind of formation method of semiconductor device, and the air gap of formation not only homogeneity is good, and the effective K value in interconnection layer reduces, and the RC effect is little, and can be to the conductor wire injury, and the performance of semiconductor integrated circuit is good.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention, so the present invention is not subjected to the restriction of following public specific embodiment.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the present invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three-dimensional space that should comprise in addition, length, width and the degree of depth in actual fabrication.
Please refer to Fig. 7, the formation method of the semiconductor device of the embodiment of the present invention comprises:
Step S201 provides Semiconductor substrate; Described semiconductor substrate surface is formed with interlayer dielectric layer, and described interlayer dielectric layer has groove;
Step S203, the part interlayer dielectric layer of the described trenched side-wall of oxidation forms oxide layer;
Step S205 carries out nitrogen treatment to the described oxide layer near the segment thickness of trenched side-wall, forms at the protective layer of described trenched side-wall, sacrifice layer between described interlayer dielectric layer and protective layer;
Step S207 after described protective layer to be formed, fills the conductor wire of described groove formation and described interlayer dielectric layer flush;
Step S209 removes described sacrifice layer, forms the air gap.
Concrete, please refer to Fig. 8-Figure 13, Fig. 8-Figure 13 shows the cross-sectional view of forming process of the semiconductor device of the embodiment of the present invention.
Please refer to Fig. 8, Semiconductor substrate 300 is provided; Described Semiconductor substrate 300 surfaces are formed with etching barrier layer 301; Described etching barrier layer 301 surfaces are formed with interlayer dielectric layer 303; Described interlayer dielectric layer 303 surfaces are formed with resilient coating 305; Groove 307, described groove 307 runs through described interlayer dielectric layer 303, resilient coating 305, etching barrier layer 101.
Wherein, described Semiconductor substrate 300 is for subsequent technique provides workbench, and the material of described Semiconductor substrate 300 is insulating material.
It is not damaged when forming groove that described etching stop layer 301 is used for follow-up protection Semiconductor substrate 300, and the material of described etching stop layer 301 is SiN or TiN, and the formation technique of described etching stop layer 301 is depositing operation, for example physics or chemical vapour deposition (CVD).
Described interlayer dielectric layer 303 is used to subsequent etching to form groove platform is provided, and is used for isolating adjacent conductor wire, prevents short circuit.The formation technique of described interlayer dielectric layer 303 is depositing operation, for example physics or chemical vapour deposition (CVD).The material of described interlayer dielectric layer 303 is the K value less than 3.0 low-K dielectric material.In an embodiment of the present invention, described low-K dielectric material comprises C, Si, O and H element.
Described resilient coating 305 is used for providing a buffering, protection interlayer dielectric layer 303 when subsequent etching forms groove.The material of described resilient coating 305 is SiO
2, a kind of in SiN, SiC, SiON or BN.In an embodiment of the present invention, the formation technique of described resilient coating 305 is TEOS technique or low temperature oxidation technology (LTO).
Described groove 307 is used for the filled conductive material and forms conductor wire.In an embodiment of the present invention, the formation technique of described groove 307 is dry etch process.Because dry etch process is well known to those skilled in the art, do not repeat them here.
Need to prove, in other embodiments of the invention, described groove 307 can also form by the Damascus technics of free hand drawing shape or dual damascene figure, and it is simple that it forms technique, and the quality of the groove of formation is good.
Need to prove, in other embodiments of the invention, can also directly form interlayer dielectric layer 303 on described Semiconductor substrate 300, described interlayer dielectric layer 303 has groove 307.
Please refer to Fig. 9, the part interlayer dielectric layer 303 of described groove 307 sidewalls of oxidation forms oxide layer 309.
The inventor finds, forms the air gap at groove 307 sidewalls, helps to reduce the effective K value in interconnection layer.Further, the inventor finds, part interlayer dielectric layer 303 that can described groove 307 sidewalls of direct oxidation, and the interlayer dielectric layer 303 after oxidation easily is removed.Therefore, in embodiments of the invention, the part interlayer dielectric layer 303 of described groove 307 sidewalls is carried out oxidation, formed oxide layer 309.
Described oxide layer 309 is used for follow-up formation sacrifice layer and protective layer.The material of described oxide layer 309 is SiO
2The gas that the part interlayer dielectric layer 303 of described groove 307 sidewalls of oxidation adopts is O
2, O
3Or CO
2Further, better for the quality that makes the oxide layer 309 that oxidation forms, during the part interlayer dielectric layer of the described trenched side-wall of oxidation, adopt O
2, O
3Or CO
2In a kind of gas, and the temperature conditions during oxidation is: more than or equal to 150 ℃.In an embodiment of the present invention, the technique of part interlayer dielectric layer 303 employings of described groove 307 sidewalls of oxidation is plasma oxidation process.
Please refer to Figure 10, the described oxide layer near the segment thickness of groove 307 sidewalls is carried out nitrogen treatment, form at the protective layer 311 of described trenched side-wall, sacrifice layer 310 between described interlayer dielectric layer 303 and protective layer 311.
The inventor finds, if follow-uply directly remove described oxide layer 309 and form the air gap, might to existing conductor wire injury, affect the transmission of signal in follow-up integrated circuit.Further, the inventor finds, is pre-formed 311 pairs of conductor wires of a protective layer and protects, and can avoid the generation of problems.Further, inventor's discovery is carried out nitrogen treatment to described oxide layer, and the protective layer 311 of formation can protect conductor wire not impaired in subsequent technique.
In an embodiment of the present invention, the formation step of described protective layer 311 comprises: the described oxide layer near the segment thickness of groove 307 sidewalls is carried out nitrogen treatment, for example plasma nitridation process.The gas that described nitrogen treatment adopts is NH
3, N
2, NO or NO
2In a kind of.The material of the protective layer 311 that forms is SiN.Considered the protection of protective layer 311, follow-up conductor wire is difficult for impaired, can form the air gap of larger width.After research, the inventor finds, the width of described protective layer 311 is less than 1/2 of the width of described oxide layer.
Described sacrifice layer 310 is not namely by the oxide layer of nitrogenize, for follow-up formation air gap.The width of described sacrifice layer 310 is relevant with the width of the air gap of follow-up formation, in order to reduce to greatest extent the effective K value in interconnection layer, reduce the RC effect, do not destroy again the insulation effect of interlayer dielectric layer 301 and the transmission performance of conductor wire, in an embodiment of the present invention, the width of described sacrifice layer 310 is greater than 1/10 of minimum range between adjacent two grooves, and less than 3/7 of minimum range between adjacent two grooves.
Need to prove, the width of embodiment of the present invention indication and distance are the size that is parallel to Semiconductor substrate 300 surface direction.
Please refer to Figure 11, after described protective layer 311 to be formed, fill the conductor wire 313 of described groove formation and described interlayer dielectric layer 303 flush.
Described conductor wire 313 is used for transmission of signal, and the material of described conductor wire 313 is electric conducting material, such as copper, titanium, tantalum, tungsten etc.The forming process of described conductor wire 313 is: for example physics or chemical vapor deposition method deposition cover the conductive film of described Semiconductor substrate 300, protective layer 311 and interlayer dielectric layer 303 (namely filling full described groove) to adopt depositing operation; Then adopt CMP (Chemical Mechanical Polishing) process (CMP) to carry out chemico-mechanical polishing to described conductive film, expose described interlayer dielectric layer 303 and protective layer 311, form conductor wire 313.
Please refer to Figure 12, remove described sacrifice layer, form air gap 315.
The technique of removing the employing of described sacrifice layer is wet-etching technology.In an embodiment of the present invention, the chemical reagent of described wet-etching technology employing comprises hydrofluoric acid.
Described air gap 315 reduces power consumption and reduces the RC effect for reducing the effective K value in interconnection layer.The width of described air gap 315 equals the width of described sacrifice layer, and namely the width of described air gap 315 is greater than 1/10 of minimum range between adjacent two grooves, and less than 3/7 of minimum range between adjacent two grooves.
Need to prove, when removing described sacrifice layer, due to the protection that described protective layer 311 is arranged, can not cause damage to conductor wire 313.
Please refer to Figure 13, form across described air gap 315, and cover the insulating barrier 317 of described interlayer dielectric layer 303 and protective layer 311.
In an embodiment of the present invention, after forming air gap 315, also comprise: form described insulating barrier 317, be used for the conductor wire 313 between the isolation adjacent layer.The material of described insulating barrier 317 is the common insulating material such as silicon dioxide, does not repeat them here.
To sum up, in embodiments of the invention, the described oxide layer near the segment thickness of trenched side-wall is carried out nitrogen treatment, form at the protective layer of described trenched side-wall, sacrifice layer between described interlayer dielectric layer and protective layer.Described sacrifice layer is for follow-up formation air gap; described protective layer can be without prejudice in the process that forms the air gap for the protection of conductor wire; and can form the air gap of better quality; reduced to a greater extent the effective K value in the interconnection layer; reduce the RC effect, improved the semiconductor integrated circuit performance.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (15)
1. the formation method of a semiconductor device comprises:
Semiconductor substrate is provided; Described semiconductor substrate surface is formed with interlayer dielectric layer, and described interlayer dielectric layer has groove;
It is characterized in that, also comprise:
The part interlayer dielectric layer of the described trenched side-wall of oxidation forms oxide layer;
Described oxide layer near the segment thickness of trenched side-wall is carried out nitrogen treatment, form at the protective layer of described trenched side-wall, sacrifice layer between described interlayer dielectric layer and protective layer;
After described protective layer to be formed, fill the conductor wire of described groove formation and described interlayer dielectric layer flush;
Remove described sacrifice layer, form the air gap.
2. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the material of described oxide layer is SiO
2
3. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the gas that the part interlayer dielectric layer of the described trenched side-wall of oxidation adopts is O
2, O
3Or CO
2
4. the formation method of semiconductor device as claimed in claim 3, is characterized in that, the temperature conditions of the part interlayer dielectric layer of the described trenched side-wall of oxidation is: more than or equal to 150 ℃.
5. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the technique that the part interlayer dielectric layer of the described trenched side-wall of oxidation adopts is plasma oxidation process.
6. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the gas that described nitrogen treatment adopts is NH
3, N
2, NO or NO
2In a kind of.
7. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the formation technique of described protective layer is plasma nitridation process.
8. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the material of described protective layer is SiN.
9. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the width of described protective layer is less than 1/2 of the width of described oxide layer.
10. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the width of described sacrifice layer is greater than 1/10 of minimum range between adjacent two grooves, and less than 3/7 of minimum range between adjacent two grooves.
11. the formation method of semiconductor device as claimed in claim 1 is characterized in that, the technique of removing described sacrifice layer is wet-etching technology, and the chemical reagent that described wet-etching technology adopts comprises hydrofluoric acid.
12. the formation method of semiconductor device as claimed in claim 1 is characterized in that, described groove forms by the Damascus technics of free hand drawing shape or dual damascene figure.
13. the formation method of semiconductor device as claimed in claim 1 is characterized in that, the material of described interlayer dielectric layer is the K value less than 3.0 low-K dielectric material.
14. the formation method of semiconductor device as claimed in claim 13 is characterized in that, described low-K dielectric material comprises C, Si, O and H element.
15. the formation method of semiconductor device as claimed in claim 1 is characterized in that, also comprises: form across described air gap, and cover the insulating barrier of described interlayer dielectric layer and protective layer.
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|---|---|---|---|
| CN201110340619.3A CN103094192B (en) | 2011-11-01 | 2011-11-01 | Forming method of semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109962014A (en) * | 2017-12-26 | 2019-07-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113540025A (en) * | 2020-04-14 | 2021-10-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101599455A (en) * | 2008-06-03 | 2009-12-09 | 台湾积体电路制造股份有限公司 | Integrated circuit formation method |
| US20110183516A1 (en) * | 2009-03-26 | 2011-07-28 | Samsung Electronics Co., Ltd. | Methods of forming wiring structures |
-
2011
- 2011-11-01 CN CN201110340619.3A patent/CN103094192B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101599455A (en) * | 2008-06-03 | 2009-12-09 | 台湾积体电路制造股份有限公司 | Integrated circuit formation method |
| US20110183516A1 (en) * | 2009-03-26 | 2011-07-28 | Samsung Electronics Co., Ltd. | Methods of forming wiring structures |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109962014A (en) * | 2017-12-26 | 2019-07-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109962014B (en) * | 2017-12-26 | 2022-10-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113540025A (en) * | 2020-04-14 | 2021-10-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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