CN109962014A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

Info

Publication number
CN109962014A
CN109962014A CN201711427817.7A CN201711427817A CN109962014A CN 109962014 A CN109962014 A CN 109962014A CN 201711427817 A CN201711427817 A CN 201711427817A CN 109962014 A CN109962014 A CN 109962014A
Authority
CN
China
Prior art keywords
side wall
layer
gate structure
barrier layer
forming method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201711427817.7A
Other languages
Chinese (zh)
Other versions
CN109962014B (en
Inventor
纪世良
张海洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201711427817.7A priority Critical patent/CN109962014B/en
Publication of CN109962014A publication Critical patent/CN109962014A/en
Application granted granted Critical
Publication of CN109962014B publication Critical patent/CN109962014B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A kind of semiconductor structure and forming method thereof, forming method includes: offer substrate, and gate structure is formed in substrate, is formed with side wall on the side wall of gate structure；Barrier layer is formed on the side wall of side wall；The side wall at least removing Partial Height, forms groove between barrier layer and gate structure；First medium layer is formed in the partial depth of groove top, first medium layer, barrier layer and gate structure surround air side wall.After the present invention forms barrier layer on side wall side wall, at least remove the side wall of Partial Height, groove is formed between barrier layer and the gate structure, the first medium layer, barrier layer and the gate structure that are formed in groove top partial depth is set to surround air side wall, compared with spacer material, the dielectric constant of air is smaller, so the setting of air side wall can reduce the parasitic capacitance of semiconductor devices, it to accelerating the reaction speed of semiconductor devices, reducing power consumption and increasing driving current, and then can be promoted the electrical property of semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
In semiconductor fabrication, with the development trend of super large-scale integration, integrated circuit feature size persistently subtracts It is small.For the reduction of meeting market's demand size, MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) channel length also corresponding constantly shorten.However, with the shortening of device channel length, device source Pole between drain electrode at a distance from also shorten therewith, therefore grid is deteriorated therewith to the control ability of channel, grid voltage pinch off The difficulty of (pinch off) channel is also increasing, so that sub-threshold leakage (subthreshold leakage) phenomenon, i.e. institute The short-channel effect (SCE:short-channel effects) of meaning is easier to occur.
Therefore, for the reduction of better meeting market's demand size, semiconductor technology gradually starts from planar MOSFET to tool There is the transistor transient of the three-dimensional of more high effect, such as fin formula field effect transistor (FinFET).In FinFET, grid knot Structure can at least control ultra-thin body (fin) from two sides, compared with planar MOSFET, control of the gate structure to channel Ability is stronger, can be good at inhibiting short-channel effect；And FinFET has relative to other devices with existing IC manufacturing There is better compatibility.
But the electric property of the semiconductor structure of prior art formation is still to be improved.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, improves the electricity of semiconductor structure Performance.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, comprising: substrate is provided, it is described It is formed with gate structure in substrate, is formed with side wall on the side wall of the gate structure；Resistance is formed on the side wall of the side wall Barrier；The side wall at least removing Partial Height, forms groove between the barrier layer and the gate structure；In the groove First medium layer is formed in the partial depth at top, the first medium layer, barrier layer and gate structure surround air side wall.
Correspondingly, the present invention also provides a kind of semiconductor structures, comprising: substrate；Gate structure is located in the substrate； Barrier layer, on the side wall of the gate structure；Groove, it is described recessed between the gate structure and the barrier layer Slot at least exposes the partial sidewall of the gate structure；First medium layer, it is described in the partial depth of the groove top First medium layer, barrier layer and gate structure surround air side wall.
Compared with prior art, technical solution of the present invention has the advantage that
After the present invention forms barrier layer on the side wall of side wall, the side wall of Partial Height is at least removed, on the barrier layer Form groove between the gate structure, it is subsequent form first medium layer in the partial depth of the groove top after, institute It states first medium layer, barrier layer and gate structure and surrounds air side wall (Air-gap Spacer), correspondingly, subsequent in the base After forming interlayer dielectric layer on bottom, it can make to realize electrical isolation between at least partly gate structure and interlayer dielectric layer with air； Compared with spacer material, the smaller (K of the dielectric constant of airvacuum=1), so the setting of air side wall can reduce semiconductor The parasitic capacitance of device, such as outer edge capacitor (Outer fringing capacitance, Cof) and grid can be reduced With the capacitor between contact hole plug (Contact-plug), thus be conducive to accelerate semiconductor devices reaction speed, reduce Power consumption and increase driving current, and then can be promoted the electrical property of semiconductor structure.
In optinal plan, after forming side wall on the side wall of gate structure, barrier layer is formed on the side wall of the side wall Before, using H2Or He plasma, at least the side wall described in Partial Height carries out corona treatment, and passes through wet etching Mode remove the spacer material through the corona treatment；Corona treatment can weaken through the corona treatment Spacer material bond energy, thus make the wet-etching technology to the spacer material through the corona treatment have it is higher Etch rate and etching selection ratio (etch rate) reduce the wet process and carve thus while effectively removing the side wall Influence of the etching technique to other structures in the substrate, and then be conducive to improve the electric property of formed semiconductor structure and good Rate.
In optinal plan, in the step of forming the groove, the side wall is removed, the groove is made to expose the barrier layer Substrate between the gate structure, that is to say, that air side wall is completely instead of the side wall, to be conducive to further The parasitic capacitance for reducing semiconductor devices, can at least reduce 40% for power consumption, driving current is at least increased 40%.
In optinal plan, the gate structure is pseudo- grid structure, removes the grid knot after forming the air side wall Structure forms metal gate structure at the gate structure position, so as to avoid the formation of the technique step of the air side wall Suddenly adverse effect is caused to the metal gate structure, and then is conducive to further to be promoted the electric property of semiconductor structure and good Rate.
Detailed description of the invention
Fig. 1 to Figure 10 is the corresponding structural representation of each step in the forming method first embodiment of semiconductor structure of the present invention Figure；
Figure 11 to Figure 19 is that the corresponding structure of each step is shown in the forming method second embodiment of semiconductor structure of the present invention It is intended to；
Figure 20 is the structural schematic diagram of one embodiment of semiconductor structure of the present invention.
Specific embodiment
It can be seen from background technology that even if the electric property of semiconductor structure still needs to be mentioned at present after introducing FinFET structure It is high.Its electric property reason still to be improved is analyzed to be:
Parasitic capacitance has biggish negative effect on the electric property of fin formula field effect transistor, wherein influencing most serious Parasitic capacitance mainly include capacitor between outer edge capacitor and grid and contact hole plug, if fin field effect crystal Parasitic capacitance in pipe is excessive, then the reaction speed of semiconductor devices can be caused to slow down, power consumption increases and driving current increases The problems such as, and with the reduction of integrated circuit feature size, shadow of the parasitic capacitance to the electric property of fin formula field effect transistor Sound also increases with it, the even more than influence of device natural capacity (Intrinsic Capacitance, Cox).
In the formation process of current fin formula field effect transistor, side wall (Spacer) is generallyd use to control ion note The region entered, the material of side wall are generally one or both of silicon nitride and silica, and in self-aligned contacts (Self- Aligned Contact, SAC) side wall of silicon nitride material is generally used in technology.Since the dielectric constant of silicon nitride is larger, So that the parasitic capacitance of fin formula field effect transistor is larger, and become the obstruction for reducing parasitic capacitance.Particularly with NMOS device, when using the side wall of high dielectric constant material, it is difficult to meet its actual demand to electric property.
Therefore, it is urgent to provide a kind of forming methods of semiconductor structure, to reduce the parasitism electricity of fin formula field effect transistor Hold.
In order to solve the technical problem, after the present invention forms barrier layer on the side wall of side wall, at least removal part is high The side wall of degree forms groove, the subsequent partial depth in the groove top between the barrier layer and the gate structure After interior formation first medium layer, the first medium layer, barrier layer and gate structure surround air side wall, correspondingly, it is subsequent After forming interlayer dielectric layer in the substrate, it can make to realize electricity between at least partly gate structure and interlayer dielectric layer with air Insulation；Compared with spacer material, the dielectric constant of air is smaller, so the setting of air side wall can reduce semiconductor devices Parasitic capacitance, such as the capacitor between outer edge capacitor and grid and contact hole plug can be reduced, to be conducive to accelerate The reaction speed of semiconductor devices reduces power consumption and increases driving current, and then the electric property of semiconductor structure is enable to mention It rises.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention Specific embodiment be described in detail.
Fig. 1 to Figure 10 is the corresponding structural representation of each step in the forming method first embodiment of semiconductor structure of the present invention Figure.
In conjunction with referring to figs. 1 to Fig. 3, Fig. 1 is perspective view (only illustrating a gate structure), and Fig. 2 is Fig. 1 along the direction AA1 The schematic diagram of the section structure of secant provides substrate (not indicating), and gate structure 120, the grid knot are formed in the substrate Side wall 200 (as shown in Figure 3) is formed on the side wall of structure 120.
In the present embodiment, the substrate is used to form fin formula field effect transistor, thus the substrate include substrate 100 with And the discrete fin 110 on the substrate 100.In other embodiments, the substrate can be also used for forming plane crystalline substance Body pipe, the substrate mutually should be planar substrates.
The substrate 100 provides technique platform to be subsequently formed fin formula field effect transistor, and the fin 110 is for providing The channel of formed fin formula field effect transistor.
In the present embodiment, the substrate 100 is silicon substrate.In other embodiments, the material of the substrate can also be The other materials such as germanium, SiGe, silicon carbide, GaAs or gallium indium, the substrate can also on insulator silicon substrate or The other kinds of substrate such as the germanium substrate on person's insulator.The material of the substrate, which can be, to be suitable for process requirement or is easy to collect At material.
The material of the fin 110 is identical as the material of the substrate 100.In the present embodiment, the material of the fin 110 For silicon.In other embodiments, the material of the fin can also be germanium, SiGe, silicon carbide, GaAs or gallium indium.
In the present embodiment, for being formed by fin formula field effect transistor and be cmos device, the substrate 100 includes PMOS area I (as shown in Figure 2) and NMOS area II (as shown in Figure 2), the substrate of the PMOS area I and NMOS area II 100 are respectively formed on discrete fin 110.In other embodiments, being formed by fin formula field effect transistor can moreover be only NMOS, the substrate accordingly only include NMOS area；Alternatively, being formed by fin field effect pipe is only PMOS, the substrate phase It should only include PMOS area.
In the present embodiment, the PMOS area I and NMOS area II are adjacent area.In other embodiments, described PMOS area and NMOS area can also be isolated.
Correspondingly, the gate structure 120 is across the fin 110, and cover atop part and the portion of the fin 110 Divide side wall.In the present embodiment, gate electrode layer (High K Last Metal gate is formed after forming high-k gate dielectric layer after Last technique), i.e., the described gate structure 120 are pseudo- grid structure (Dummy Gate), and the gate structure 120 is to be subsequently formed Take up space the metal gate structure (Metal Gate) of the fin formula field effect transistor position.In other embodiments, institute State gate structure can also by formation fin formula field effect transistor metal gate structure.
In the present embodiment, dummy gate structure is laminated construction, the pseudo- oxide layer including being located in the substrate and position Pseudo- grid layer in the pseudo- oxide layer.The material of the puppet grid layer is polysilicon, and the material of the puppet oxide layer can be oxygen SiClx or silicon oxynitride.In another embodiment, the material of the pseudo- grid layer can also for silica, silicon nitride, silicon oxynitride, The other materials such as silicon carbide, carbonitride of silicium, carbon silicon oxynitride or amorphous carbon.
In other embodiments, dummy gate structure can also be single layer structure, and the material of dummy gate structure can select From other materials such as polysilicon, silica, silicon nitride, silicon oxynitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride and amorphous carbons One or more of.
Specifically, the step of forming gate structure 120 includes: that pseudo- grid film, the puppet are formed on the substrate 100 Grid film is across the top and side wall of the fin 110 and the covering fin 110；The first buffering is formed in the pseudo- grid film surface Film；Hardmask material is formed on first buffer film；The second buffer film is formed on the hardmask material；Successively Second buffer film and hardmask material are etched, the second buffer film of residue after etching is as second buffer layer 150, etching Remaining hardmask material afterwards is defined as hard mask layer 140, the second buffer layer 150 and hard mask layer 140 to shape At gate structure 120 figure；It is exposure mask with the second buffer layer 150 and hard mask layer 140, is sequentially etched described first Buffer film and pseudo- grid film, first buffer film of residue after etching are used as first buffer layer 130, the remaining puppet grid film conduct after etching Gate structure 120.
In the present embodiment, the material of the hard mask layer 140 is silicon nitride, and the hard mask layer 140 is used for as etching The etch mask of the puppet grid film is also used to during subsequent technique to playing a protective role at the top of the gate structure 120. In other embodiments, the material of the hard mask layer can also be silicon oxynitride, silicon carbide or boron nitride.
Since the stress of the hardmask material (the i.e. described hard mask layer 140) is larger, formed on the pseudo- grid film When the hardmask material, it is easy to cause dislocation, the first buffer film (i.e. described first buffering in the pseudo- grid film surface 130) layer for providing buffer function when forming the hardmask material, avoids the problem that generating dislocation；In addition, successively carving When losing second buffer film and hardmask material, the first buffering film surface can also define the position of etching stopping, To avoid the problem that etching deficiency or over etching (Over Etch) occurs in each region, and then avoid to formed gate structure 120 quality and pattern generates adverse effect.In the present embodiment, the material of first buffer film is silica, i.e., described the The material of one buffer layer 130 is silica.
The second buffer layer 150 and the hard mask layer 140 collectively as the etch mask for etching the pseudo- grid film, from And it can guarantee that the effect of etch mask is unaffected in the case where suitably reducing 140 thickness of hard mask layer.This implementation In example, the material of second buffer film is silica, i.e., the material of the described second buffer layer 150 is silica.Due to subsequent It is formed by interlayer dielectric layer and exposes 120 top of gate structure, and the material of the interlayer dielectric layer is generally also oxidation Silicon, therefore by forming the second buffer layer 150 at the top of the hard mask layer 140, it is being subsequently formed interlayer dielectric layer In technical process, the technology difficulty of flatening process can also be accordingly reduced.
The side wall 200 is used to protect the side wall of the gate structure 120, is also used to define subsequent ion injection technology The regional location of (such as source and drain injection technology).The side wall 200 can be single layer structure or laminated construction, the side wall 200 Material can for silica, silicon nitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride, boron nitride and carbon nitridation One of boron is a variety of.In the present embodiment, the side wall 200 is single layer structure, and the material of the side wall 200 is silicon nitride. Wherein, according to actual process demand, the side wall 200 with a thickness of 3nm to 15nm.
In conjunction with reference Fig. 3 and Fig. 4, barrier layer 250 (as shown in Figure 4) is formed on the side wall of the side wall 200.
Subsequent step includes the side wall 200 of at least etched portions height, so that the side wall 200 is replaced with air side wall, The barrier layer 250 is used to limit the boundary of formed air side wall, i.e., the described barrier layer 250 is used for and the gate structure 120 surround the air side wall.
It should be noted that subsequent step further includes forming etching stop layer and interlayer dielectric layer, therefore in the present embodiment, Choosing has with the substrate, side wall 200, etching stop layer and interlayer dielectric layer compared with high technology compatibility and the common material of technique Expect the material as the barrier layer 250.So the material on the barrier layer 250 can be silica, silicon nitride, nitrogen oxidation One of silicon, silicon carbide, carbonitride of silicium, carbon silicon oxynitride, boron nitride and boron carbonitrides are a variety of.
In the present embodiment, the material on the barrier layer 250 is silica.Cost is relatively low for silica material, and subsequent shape In technical process at the interlayer dielectric layer, further include the steps that planarization process, therefore pass through selective oxidation silicon materials The barrier layer 250, so as to preferably be compatible with the planarization process, the technique for advantageously reducing the planarization process Difficulty.
In the present embodiment, the material on the barrier layer 250 is different from the material of the side wall 200, therefore subsequent etching Technique to form the side wall 200 and the barrier layer 250 etching selection ratio with higher so as to preferably control The pattern of air side wall.
It should be noted that the thickness on the barrier layer 250 is unsuitable too small, also should not be too large.If the barrier layer 250 Thickness it is too small, then in subsequent etching technics, the barrier layer 250 is higher by the probability being lost, to be unfavorable for pair The pattern of formed air side wall controls；If the thickness on the barrier layer 250 is excessive, it is unfavorable for the reduction of characteristic size, And it also will cause the unnecessary waste of process costs.For this purpose, in the present embodiment, the barrier layer 250 with a thickness of 2nm to 5nm. Wherein, the thickness on the barrier layer 250 refers to: the barrier layer 250 is along the ruler perpendicular to 200 sidewall direction of side wall It is very little.
In the present embodiment, the barrier layer is formed using atomic layer deposition (Atomic Layer Deposition) technique 250, to improve the caliper uniformity on the barrier layer 250 and the covering power in 200 side wall of side wall.Accordingly , after forming the barrier layer 250, the barrier layer 250 also covers the substrate 100 top (as shown in Figure 1), fin 110 150 top of side wall and top, 200 top of side wall and second buffer layer.
It should be noted that after forming the barrier layer 250, reservation is covered in order to reduce processing step, reduce technology difficulty Cover the resistance at 150 top of 100 top of substrate, 110 side wall of fin and top, 200 top of side wall and second buffer layer Barrier 250.In other embodiments, it can also etch by etching technics and remove the substrate top, fin side wall and top Barrier layer at the top of portion, side wall and at the top of second buffer layer, only retains the barrier layer of the side wall side wall.
It should also be noted that, in the present embodiment, in order to described in subsequent etching during side wall 200, described in reduction The mode that influence of the etching technics to other structures in the substrate, using plasma processing and wet etching combine is to go Except the side wall 200.
Fig. 3 is referred to correspondingly, combining, is formed on the side wall of the side wall 200 before the barrier layer 250, the shape At method further include: use H2Or He plasma, corona treatment at least is carried out to the side wall 200 of Partial Height 220。
By the corona treatment 220, to weaken the key of 200 material of side wall through the corona treatment 220 Can, to provide Process ba- sis to the side wall 200 progress wet-etching technology to be subsequent.
Specifically, compared with 200 material of side wall without the corona treatment 220, although through the plasma 200 material of side wall of processing 220 is still silicon nitride, but the material structure of the side wall 200 is changed, subsequent wet etching Technique to 200 material of side wall etch rate with higher and etching selection ratio through the corona treatment 220, thus While effectively removing side wall 200, influence of the wet-etching technology to other structures in the substrate is reduced, in turn Be conducive to improve the electric property and yield of formed semiconductor structure.
In the present embodiment, the technique of the corona treatment 220 is plasma implantation process.Plasma injects work Skill has preferably injection direction, so as to carry out plasma to the side wall 200 along the short transverse of the side wall 200 Body processing 220, and then be conducive to control 200 height of side wall through the corona treatment 220.Wherein, the side wall 200 Short transverse is the substrate surface normal direction.
In other embodiments, the technique of the corona treatment can also be plasma doping process.
Specifically, the step of carrying out corona treatment 220 to the side wall 200 includes: to capacitance coupling plasma H is passed through in (Capacitive Coupled Plasma, CCP) chamber2Or He, along the short transverse of the side wall 200, H atom Or He atom is injected into the side wall 200.
It should be noted that the Implantation Energy of the corona treatment 220 is bigger, the injection of H atom or He atom is deep Degree is bigger, and 200 height of side wall influenced by the corona treatment 220 is corresponding also bigger, and the corona treatment 220 Implantation Energy by bias power set, i.e., bias power is bigger, and the Implantation Energy of the corona treatment 220 is accordingly got over Greatly.So the bias power of the corona treatment 220 is unsuitable too small, also should not be too large.If bias power is too small, It is easy to cause the effect for carrying out corona treatment 220 to the side wall 200 poor, to reduce subsequent wet etching technics edge The etch amount of the short transverse of the side wall 200；If bias power is excessive, process risk also will increase, be easy to exposing Substrate cause adverse effect.For this purpose, in the present embodiment, the bias power of the corona treatment 220 be 200W extremely 2000W.Wherein, according to the removal amount of the subsequent side wall 200 and the height of the side wall 200, reasonable biasing function is set Rate.
Also it should be noted that, under fixed bias power, the process time of the corona treatment 220 is longer, then Implantation dosage is bigger, and the effect for carrying out the corona treatment 220 to the side wall 200 is accordingly better, subsequent wet etching Technique is also bigger to the removal rate of the side wall 200.So the process time of the corona treatment 220 is unsuitable too short, Also unsuitable too long.If the process time of the corona treatment 220 is too short, it is easy to cause and the side wall 200 is carried out The effect of corona treatment 220 is poor, to reduce the etch rate of subsequent wet etching technics；If the plasma The process time of processing 220 is too long, also will increase process risk, is easy to cause adverse effect to the substrate exposed.For this purpose, this In embodiment, the process time of the corona treatment 220 is 5 seconds to 12 seconds.Wherein, according to the subsequent side wall 200 The height of removal amount and the side wall 200 sets the reasonable process time.
In addition, H2Or the gas flow of He is unsuitable too small, also should not be too large.If the gas flow is too small, to institute State side wall 200 carry out the corona treatment 220 effect it is poor, correspondingly, be unfavorable for subsequent wet etching technics into Row；If the gas flow is excessive, it is easy to generate adverse effect to other film layers or structure, to be easy to cause to form half The electric property and reliability performance of conductor structure decline.For this purpose, in the present embodiment, H2Or the gas flow of He is 100sccm To 1000sccm.Wherein, according to the removal amount of the subsequent side wall 200 and the height of the side wall 200, reasonable gas is set Body flow.
It is subsequent to use wet-etching technology in the present embodiment, remove 200 material of side wall through the corona treatment 220 Material, to replace the side wall 200 using air side wall.Compared with the material of the side wall 200, the dielectric constant of air is smaller (Kvacuum=1), so the setting of air side wall can reduce the parasitic capacitance of semiconductor devices, such as outer edge can be reduced Capacitor between capacitor and grid and contact hole plug, to be conducive to accelerate the reaction speed of semiconductor devices, reduce function Consumption and increase driving current, and then can be promoted the electrical property of semiconductor structure.
That is, in subsequent wet-etching technology, it is bigger to the etch amount of the side wall 200, it is formed and is partly led The parasitic capacitance of body device is smaller.For this purpose, carrying out corona treatment to the side wall 200 of whole height in the present embodiment 220, so that subsequent wet etching technics be enable to completely remove the side wall 200.
It should be noted that at present for NMOS device, when using the side wall 200 of high dielectric constant material, it is difficult to Meet its actual demand to electric property.Therefore, in the present embodiment, according to actual process demand, only to the NMOS area The side wall 200 of II carries out the corona treatment 220.
Specifically, photoresist layer 210 is formed in the substrate of the PMOS area I, the photoresist layer 210 covers described 150 top of 200 top of side wall and second buffer layer of PMOS area I；It is exposure mask with the photoresist layer 210, to the NMOS The side wall 200 of region II carries out the corona treatment 220；After the corona treatment 220, the photoresist is removed Layer 210.
In other embodiments, only the corona treatment can also be carried out by the side wall to the area PMOS；Alternatively, right The side wall in the NMOS area and the area PMOS carries out the corona treatment, can also be according to actual process demand, to described The side wall in NMOS area and the area PMOS carries out the corona treatment respectively, subsequent to the NMOS area and PMOS to control respectively The side wall removal amount in area, so that NMOS device and PMOS device be made to meet the actual demand to electric property respectively.
It should also be noted that, after the corona treatment 220, the forming method further include: with the side wall 200 be exposure mask, and p-type source and drain doping area is formed in the substrate (not indicating) of 120 two sides of gate structure of the PMOS area I (not shown) forms N-type source and drain doping area (not shown) in the substrate of 120 two sides of gate structure of the NMOS area II.
P-type source and drain doping area is for the source region (Source) or drain region (Drain) as formed PMOS device, institute ShuNXing source and drain doping area is used for source region or drain region as formed NMOS device.
It, can be to avoid right by carrying out the corona treatment 220 after forming the side wall 200 in the present embodiment It is subsequent to be formed by structure or doped region causes adverse effect, to be conducive to the electrical property for further promoting semiconductor structure Energy.
It with continued reference to Fig. 4, and combines and refers to Fig. 5 to Fig. 7, at least remove the side wall 200 (as shown in Figure 6) of Partial Height, Groove 220 (as shown in Figure 7) is formed between the barrier layer 250 and the gate structure 120.
The groove 220 is used to provide Process ba- sis to be subsequently formed air side wall.Wherein, with the material of the side wall 200 Material is compared, and the dielectric constant of air is smaller, so the setting of air side wall can reduce the parasitic capacitance of semiconductor devices, such as The capacitor between outer edge capacitor and grid and contact hole plug can be reduced, to be conducive to accelerate semiconductor devices Reaction speed reduces power consumption and increases driving current, and then can be promoted the electrical property of semiconductor structure.
In the present embodiment, at least partly the side wall 200 of height is in H2Or lived through under He condition of plasma etc. from Daughter handles 220 (as shown in Figure 3), therefore the step of at least removing side wall 200 of Partial Height includes: using wet etching work Skill removes 200 material of side wall through the corona treatment 220, and etching solution used by the wet-etching technology is Hydrofluoric acid solution.
By the corona treatment 220, make the wet-etching technology to the side through the corona treatment 220 200 material of wall etching selection ratio with higher, so as to effectively remove the side wall 200 through the corona treatment 220 Material, and influence of the wet-etching technology to other structures in the substrate is effectively reduced, and then be conducive to improve institute's shape At the electric property and yield of semiconductor structure.
It should be noted that pressing percent by volume, the concentration of the hydrofluoric acid solution is unsuitable too small, also should not be too large.Such as Fruit concentration is too small, then is difficult to remove 200 material of side wall through the corona treatment 220；If concentration is excessive, although can have Side wall 200 material of the effect removal through the corona treatment 220, but since the material on the barrier layer 250 is silica, It is accordingly also easy to cause the etching loss to the barrier layer 250.For this purpose, in the present embodiment, by percent by volume, the hydrogen fluorine The concentration of acid solution is in 1:1000 to 1:100.It should be noted that percent by volume therein refers to the volume of hydrofluoric acid and water Percentage.
In the present embodiment, in order to effectively reduce the parasitic capacitance of formed semiconductor devices, to the side of whole height Wall 200 carries out the corona treatment 220, correspondingly, the wet-etching technology completely removes the side wall 200, makes institute It states groove 220 and exposes substrate between the barrier layer 250 and the gate structure 120, i.e., air side wall is completely instead of institute Side wall 200 is stated, to be conducive to further decrease the parasitic capacitance of semiconductor devices, power consumption can at least be reduced to 40%, incited somebody to action Driving current at least increases 40%.
In conjunction with reference fig. 4 to fig. 6, in the present embodiment, after forming barrier layer 250 on the side wall of the side wall 200, formed Before the groove 220 (as shown in Figure 7), the forming method further include: form etch-stop on the substrate (not indicating) Only layer 300 (as shown in Figure 4), the etching stop layer 300 also cover 250 side wall of barrier layer and top, the side wall 200 120 top of top and the gate structure；First medium film 301 is formed on the etching stop layer 300 (such as Fig. 5 institute Show), the first medium film 301 covers the etching stop layer 300 at 120 top of gate structure；Using flatening process, go Except the first medium film 301 and etching stop layer 300 for being higher than 120 top of gate structure, expose the gate structure 120 Top, the remaining first medium film 301 after the flatening process are used as second dielectric layer 310 (as shown in Figure 6).
In the present embodiment, the etching stop layer 300 is contact etch stop layer (Contact Etch Stop Layer, CESL), the surface of the etching stop layer 300 is used to define etching stopping in the etching technics for forming contact hole Position, to reduce the probability that the problem of insufficient etching or over etching occurs in each region.
In the present embodiment, the material of the etching stop layer 300 is silicon nitride.
In the present embodiment, the technique for forming the etching stop layer 300 is chemical vapor deposition (Chemical Vapor Deposition) technique, the barrier layer 250 cover the substrate 100 top, 110 side wall of fin and top (as shown in Figure 1) Portion, 200 side wall of side wall and top and 150 top of second buffer layer；Correspondingly, the step of forming etching stop layer 300 In, the etching stop layer 300 is formed on the barrier layer 250.
The second dielectric layer 310 is filled between the adjacent gate structure 120, for realizing adjacent semiconductor constructs Between, the electric isolution between adjacent metal, be also used to provide technique platform for the formation process of contact hole plug；Moreover, institute The top that second dielectric layer 310 exposes the gate structure 120 is stated, to provide technique base to be subsequently formed metal gate structure Plinth.
The material of the second dielectric layer 310 is insulating materials.The material of the second dielectric layer 310 can be oxidation Silicon, silicon nitride, silicon oxynitride or carbon silicon oxynitride.In the present embodiment, the material of the second dielectric layer 310 is silica.
In the present embodiment, after the flatening process, 310 top of second dielectric layer and the gate structure 120 Top flushes, so that the formation for follow-up function layer provides good Process ba- sis.Correspondingly, in the mistake of the flatening process Cheng Zhong also removes second buffer layer 150, hard mask layer 140 and the first buffer layer 130 at 120 top of gate structure, and also Removal is higher than the barrier layer 250 at 420 top of gate structure.
In the present embodiment, after forming the second dielectric layer 310, the side wall 200 is removed using wet-etching technology, from And the groove 220 is formed between the barrier layer 200 and gate structure 120.
It should be noted that due to being formed with the barrier layer between the etching stop layer 300 and the side wall 200 250, the barrier layer 250 also helps the influence for reducing the wet-etching technology to the etching stop layer 300, to have Conducive to the integrality and pattern quality for guaranteeing the etching stop layer 300.
In conjunction with reference Fig. 8 and Fig. 9, first medium is formed in the partial depth at the top of the groove 220 (as shown in Figure 7) 320 (as shown in Figure 9) of layer, the first medium layer 320, barrier layer 250 and gate structure 120 surround air side wall.
By the first medium layer 320, to seal 220 top of groove, consequently facilitating subsequent be situated between described second Required function layer is formed on matter layer 310 and first medium layer 320, and subsequent technique is avoided to cause shadow to the air side wall It rings.
The material of the first medium layer 320 is insulating materials.The material of the first medium layer 320 can be oxidation Silicon, silicon nitride, silicon oxynitride or carbon silicon oxynitride.In the present embodiment, in order to improve processing compatibility, the first medium layer 320 material is identical as the material of the second dielectric layer 310, i.e., the material of the described first medium layer 320 is silica.
Specifically, the step of forming first medium layer 320 includes: to form second in the second dielectric layer 310 Deielectric-coating 302 (as shown in Figure 8), the second medium film 302 are also located in the partial depth at 220 top of groove；Using Flatening process, removal are located at the second medium film 302 at 310 top of the second dielectric layer, retain the in the groove 220 Second medium film 302 is used as first medium layer 320 (as shown in Figure 9)；Wherein, the first medium layer 320 and the second medium Layer 310 constitutes interlayer dielectric layer 350 (as shown in Figure 9).
In the present embodiment, institute is formed using chemical vapor deposition (Chemical Vapor Deposition, CVD) technique State second medium film 302.Since the side wall 200 is with a thickness of 3nm to 15nm, i.e., the opening size of the described groove 220 is 3nm To 15nm, the depth-to-width ratio of the groove 220 is larger, described when forming second medium film 302 in the second dielectric layer 310 Second medium film 302 is only capable of filling in the partial depth of 220 top side of groove, therefore the first medium layer 320 while playing sealing 220 top of groove, can be avoided the spatial position for occupying the groove 220 too much；This Outside, itself binding force for being formed by first medium layer 320 using chemical vapor deposition process is stronger, and the groove 220 Opening size very little, therefore under the clamping of the barrier layer 250 and gate structure 120, the first medium layer 320 will not It is fallen in the groove 220 due to gravity；To sum up, the air side wall reduces the parasitism of semiconductor devices still validly Capacitor.
In conjunction with reference Figure 10, in the present embodiment, the gate structure 120 is (as shown in Figure 9) for pseudo- grid structure, therefore is formed After the air side wall, the forming method further include: remove the gate structure 120；After removing the gate structure 120, Metal gate structure 160 is formed at 120 position of gate structure.
Specifically, the metal gate structure 160 includes: the gate dielectric layer (not shown) in the substrate, described Gate dielectric layer covers the atop part and partial sidewall of the fin 110 across the fin 110 (as shown in Figure 1)；Grid electricity Pole layer (not shown), is located on the gate dielectric layer.
The gate dielectric layer is for realizing the electric isolution between formed metal gate structure and the substrate interior raceway groove.Institute The material for stating gate dielectric layer is high K dielectric material.Wherein, it is opposite to refer to that relative dielectric constant is greater than silica for high K dielectric material The dielectric material of dielectric constant.
In the present embodiment, the material of the gate dielectric layer is HfO2.In other embodiments, the material of the gate dielectric layer It is also selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3Deng.
The gate electrode layer is used as electrode, and the formed metal gate structure of realization is electrically connected with external circuit.This reality It applies in example, the material of the gate electrode layer is W.In other embodiments, the material of the gate electrode layer can also for Al, Cu, Ag, Au, Pt, Ni or Ti etc..
It should be noted that in the forming process of semiconductor structure, after forming the gate structure 120, the grid Structure 120 surface in pole will form natural oxidizing layer (not shown), in general, the natural oxidizing layer with a thickness of 2nm to 3nm, because After removing the gate structure 120, the natural oxidizing layer can be used for limiting the formation position of the metal gate structure 160 for this It sets, the technique that can accordingly avoid the formation of the metal gate structure 160 has an impact the air side wall.
It should also be noted that, forming the metal gate structure 160 after forming the air side wall, should be able to mutually keep away The processing step for exempting to be formed the air side wall causes adverse effect to the metal gate structure 160, to be conducive into one Step promotes the electric property and yield of semiconductor structure.
Figure 11 to Figure 19 is that the corresponding structure of each step is shown in the forming method second embodiment of semiconductor structure of the present invention It is intended to.
The something in common of the present embodiment and previous embodiment, details are not described herein for the present embodiment.The present embodiment and aforementioned reality Apply example the difference is that: after forming the groove 510 (as shown in figure 13), form the etching stop layer 600 (such as figure Shown in 14).Correspondingly, the forming method includes:
In conjunction with reference to figures 11 to Figure 13, after at least carrying out corona treatment to the side wall of Partial Height 500, in the side Barrier layer 550 (as shown in figure 12) is formed on the side wall of wall 500；Using wet-etching technology, remove at through the plasma 500 material of side wall of reason forms groove 510 between the barrier layer 550 and the gate structure 420.
In the present embodiment, the material on the barrier layer 550 is silica.
Specifically, the step of forming barrier layer 550 includes: using atom layer deposition process, in the side wall 500 Form the barrier film 555 (as shown in figure 11) on side wall, the barrier film 555 also covers at the top of the substrate (not shown), 450 top of 410 side wall of fin and top, 500 top of side wall and second buffer layer；Using no mask etching technique, institute is removed The barrier film 555 for stating 450 top of substrate top, 410 side wall of fin and top, 500 top of side wall and second buffer layer, retains institute The barrier film 555 stated on 500 side wall of side wall is used as the barrier layer 550.
By making the barrier layer 550 expose 500 top of side wall, to be provided for side wall 500 described in subsequent etching Process ba- sis.
In the present embodiment, using H2Or He plasma carries out the corona treatment, the wet-etching technology institute The etching solution of use mutually should be hydrofluoric acid solution.
In the present embodiment, in order to effectively reduce the parasitic capacitance of formed semiconductor devices, remove through the plasma After 500 material of side wall of processing, the groove 510 is made to expose the base between the barrier layer 550 and the gate structure 420 Bottom.
Technique and the wet etching to technique, the formation barrier layer 550 before forming the barrier layer 550 The specific descriptions of technique please refer to the corresponding description in previous embodiment, and details are not described herein for the present embodiment.
In conjunction with referring to figs. 14 to 16, after forming the groove 510, the forming method further include: the substrate (not Mark) on formed etching stop layer 600 (as shown in figure 14), the etching stop layer 600 also covers 550 side wall of barrier layer With 420 top of top, 510 top of the groove and the gate structure；First is formed on the etching stop layer 600 Deielectric-coating 601 (as shown in figure 15), the first medium film 601 cover the etching stop layer at 420 top of gate structure 600；Using flatening process, removal is higher than the first medium film 601 and etching stop layer 600 at 420 top of gate structure, Expose the top of the gate structure 420, the remaining first medium film 601 after the flatening process is used as second dielectric layer 610 (as shown in figure 16).
The etching stop layer 600 is contact etch stop layer, and the surface of the etching stop layer 600 is for forming The position of etching stopping is defined in the etching technics of contact hole, so that reducing each region the problem of insufficient etching or over etching occurs Probability.
In the present embodiment, the material of the etching stop layer 600 is silicon nitride, forms the work of the etching stop layer 600 Skill is chemical vapor deposition process.
It should be noted that as shown in figure 13, since the side wall 500 also covers the first buffer layer 430, hard exposure mask The side wall of layer 440 and second buffer layer 450, therefore after the removal side wall 500, it is described along the substrate surface normal direction Groove 510 also extends at 450 top position of second buffer layer；And the side wall 500 with a thickness of 3nm to 15nm, institute The depth-to-width ratio for stating groove 510 is larger, therefore as shown in figure 14, described in the processing step for forming the etching stop layer 600 Etching stop layer 600 also fills up in the partial depth groove 610 of 610 top side of groove.
In the present embodiment, the material of the second dielectric layer 610 is silica, after the flatening process, described the The top of second medium layer 610 with flushed at the top of the gate structure 420.Correspondingly, also being gone during the flatening process Except second buffer layer 450, hard mask layer 440 and the first buffer layer 430 at 420 top of gate structure, and also removal is higher than The barrier layer 550 at 420 top of gate structure.Correspondingly, after the flatening process, along the substrate surface normal side To the groove 510 extends at 420 top position of gate structure.
To the specific descriptions of the second dielectric layer 610, the corresponding description in previous embodiment is please referred to, the present embodiment exists This is repeated no more.
In conjunction with reference Figure 17 and Figure 18, first is formed in the partial depth at the top of the groove 510 (as shown in figure 17) Dielectric layer 620 (as shown in figure 18), the first medium layer 620, barrier layer 550 and gate structure 420 surround air side wall.
In the present embodiment, in order to improve processing compatibility, the material of the first medium layer 620 and the second dielectric layer 610 material is identical, i.e., the material of the described first medium layer 620 is silica.
Specifically, the step of forming first medium layer 620 includes: to form second in the second dielectric layer 610 Deielectric-coating 602 (as shown in figure 17), the second medium film 602 are also located in the partial depth at 510 top of groove；Using Flatening process, removal are located at the second medium film 602 at 620 top of the second dielectric layer, retain the in the groove 510 Second medium film 602 is used as first medium layer 620 (as shown in figure 18)；Wherein, the first medium layer 620 and the second medium Layer 610 constitutes interlayer dielectric layer 650 (as shown in figure 18).
In the present embodiment, when forming second medium film 602 in the second dielectric layer 610, the second medium film 602 It is filled in the partial depth groove 510 of 510 top side of groove, therefore the first medium layer 620 is playing While sealing 510 top of groove, the spatial position for occupying the groove 510 too much can be avoided, to make described Air side wall reduces the parasitic capacitance of semiconductor devices still validly.
Specific descriptions to the processing step for forming the first medium layer 620, please refer to corresponding in previous embodiment Description, details are not described herein for the present embodiment.
In conjunction with reference Figure 19, in the present embodiment, the gate structure 420 is (as shown in figure 18) for pseudo- grid structure, therefore shape After the first medium layer 620, the forming method further include: remove the gate structure 420；Remove the gate structure After 420, metal gate structure 460 is formed at 420 position of gate structure.
To the specific descriptions of the metal gate structure 460, the corresponding description in previous embodiment, the present embodiment are please referred to Details are not described herein.
Correspondingly, the present invention also provides a kind of semiconductor structures.
With reference to Figure 20, the structural schematic diagram of one embodiment of semiconductor structure of the present invention is shown.
The semiconductor structure includes: substrate (not indicating)；Gate structure 760 is located in the substrate；Barrier layer 850, On the side wall of the gate structure 760；Groove 810, between the gate structure 760 and the barrier layer 850, institute State the partial sidewall that groove 810 at least exposes the gate structure 760；First medium layer 920 is located at 810 top of groove Partial depth in, the first medium layer 920, barrier layer 850 and gate structure 760 surround air side wall.
In the present embodiment, the semiconductor structure is fin formula field effect transistor, therefore the substrate includes that (figure is not for substrate Show) and discrete fin 710 on the substrate.In other embodiments, the semiconductor structure can also be plane Transistor, the substrate mutually should be planar substrates.
In the present embodiment, by taking the fin formula field effect transistor is cmos device as an example, the substrate includes PMOS area I Discrete fin 710 is all had on the substrate of NMOS area II, the PMOS area I and NMOS area II.In other implementations In example, the fin formula field effect transistor can moreover be only NMOS, and the substrate accordingly only includes NMOS area；Alternatively, described Fin field effect pipe is only PMOS, and the substrate accordingly only includes PMOS area.
Correspondingly, the gate structure 760 is across the fin 710, and cover atop part and the portion of the fin 710 Divide side wall.In the present embodiment, the gate structure 760 is the metal gate structure of the fin formula field effect transistor.Specifically, The gate structure 760 includes: the gate dielectric layer (not shown) in the substrate, and the gate dielectric layer is across the fin 710, and cover the atop part and partial sidewall of the fin 710；Gate electrode layer (not shown) is located at the gate dielectric layer On.
To the specific descriptions of the substrate, fin 710 and gate structure 760, accordingly retouching in previous embodiment is please referred to It states, details are not described herein for the present embodiment.
In the present embodiment, the first medium layer 920, barrier layer 850 and gate structure 760 surround air side wall, wherein The barrier layer 850 is used to limit the boundary of the air side wall.
Compared with the material for the side wall that fin formula field effect transistor generallys use, the dielectric constant of air is smaller, so empty The setting of gas side wall can reduce the parasitic capacitance of semiconductor devices, to accelerate the reaction speed of semiconductor devices, reduce power consumption With increase driving current, and then can be promoted the electrical property of semiconductor structure.
In the present embodiment, in order to effectively reduce the parasitic capacitance of formed semiconductor devices, the air side wall is also by institute The substrate stated between gate structure 760 and the barrier layer 850 surrounds, i.e. air side wall completely instead of the side wall, thus Power consumption can at least be reduced 40%, driving current is at least increased 40%.
In the present embodiment, according to actual process demand, along perpendicular on the direction of 810 side wall of groove, the groove 810 opening size is 3nm to 15nm.It in other embodiments, can be to the open-mouth ruler of the groove according to device performance requirements Very little and depth is adjusted.
It should be noted that the groove 810 is the side by removing 760 side wall of gate structure in the present embodiment Wall is to form.In other embodiments, the semiconductor structure can also include the side wall positioned at the bottom portion of groove, that is, It says, by way of removing Partial Height side wall, makes the barrier layer, gate structure and remaining side walled at the groove, and The depth of the groove is controlled according to the removal amount of the side wall, to adjust the parasitic capacitance of formed semiconductor devices.
In the present embodiment, the barrier layer 850 is located on the side wall of the gate structure 760, and is also located at the substrate On.In other embodiments, the barrier layer can also be only located on the side wall of the gate structure.
The material on the barrier layer 850 is silica, silicon nitride, silicon oxynitride, silicon carbide, carbonitride of silicium, carbon nitrogen oxidation One of silicon, boron nitride and boron carbonitrides are a variety of.In the present embodiment, the material on the barrier layer 850 is silica.
It should be noted that the thickness on the barrier layer 850 is unsuitable too small, also should not be too large.If the barrier layer 850 Thickness it is too small, then in forming 810 technique of groove, the barrier layer 850 is higher by the probability being lost, thus unfavorable In the pattern control to the air side wall；If the thickness on the barrier layer 850 is excessive, it is unfavorable for subtracting for characteristic size It is small, and also will cause the unnecessary waste of process costs.For this purpose, in the present embodiment, the barrier layer 250 with a thickness of 2nm extremely 5nm。
The first medium layer 920 is located in the partial depth at 810 top of groove, and the first medium layer 920 is used At the top of the sealing groove 810, consequently facilitating the formation of subsequent required function layer, and avoid subsequent technique to the air Side wall impacts；Moreover, the depth-to-width ratio of the groove 810 is larger, therefore in the forming process of the first medium layer 920 In, the first medium layer 920 is only capable of filling in the partial depth of 810 top side of groove, can be avoided excessive Ground occupies the spatial position of the groove 810, so that the parasitism for making the air side wall reduce semiconductor devices still validly is electric Hold.
The material of the first medium layer 920 is insulating materials.The material of the first medium layer 920 can be oxidation Silicon, silicon nitride, silicon oxynitride or carbon silicon oxynitride.In the present embodiment, the material of the first medium layer 920 is silica.
It should be noted the semiconductor structure further include: etching stop layer 900 covers the substrate and described The side wall on barrier layer 850；Second dielectric layer 910 is located on the etching stop layer 900, and the second dielectric layer 910 exposes institute State the top of gate structure 760, wherein the second dielectric layer 910 and the first medium layer 920 are for constituting inter-level dielectric Layer 950.
In the present embodiment, the etching stop layer 900 is contact etch stop layer, the table of the etching stop layer 900 Face is used to define the position of etching stopping in the etching technics for forming contact hole, thus reduce each region occur etching it is insufficient or The probability of the problem of over etching.Specifically, the material of the etching stop layer 300 is silicon nitride.
It should be noted that the barrier layer 850 also covers the substrate top and the fin in the present embodiment 710 side walls and top, correspondingly, the etching stop layer 900 is located on the barrier layer 850.
The second dielectric layer 910 between the adjacent gate structure 760, for realizing adjacent semiconductor constructs it Between, the electric isolution between adjacent metal, be also used to provide technique platform for the formation process of contact hole plug.The present embodiment In, 910 top of the second dielectric layer with flushed at the top of the gate structure 760.
The material of the second dielectric layer 910 is insulating materials.The material of the second dielectric layer 910 can be oxidation Silicon, silicon nitride, silicon oxynitride or carbon silicon oxynitride.In the present embodiment, in order to improve processing compatibility, the second dielectric layer 910 material is identical as the material of the first medium layer 920, i.e., the material of the described second dielectric layer 910 is silica.
The semiconductor structure can be formed using forming method described in aforementioned first embodiment, can also be used aforementioned Forming method described in second embodiment is formed, and can also be formed using other forming methods.To the semiconductor structure It specifically describes, can refer to the corresponding description in previous embodiment, details are not described herein for the present embodiment.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

Claims (18)

1. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided, gate structure is formed in the substrate, is formed with side wall on the side wall of the gate structure；
Barrier layer is formed on the side wall of the side wall；
The side wall at least removing Partial Height, forms groove between the barrier layer and the gate structure；
First medium layer, the first medium layer, barrier layer and gate structure are formed in the partial depth of the groove top Surround air side wall.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the side wall is oxidation One of silicon, silicon nitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride, boron nitride and boron carbonitrides are a variety of.
3. the forming method of semiconductor structure as described in claim 1, which is characterized in that described in the step of providing substrate The material of side wall is silicon nitride；
It is formed before barrier layer on the side wall of the side wall, the forming method further include: use H2Or He plasma, until Few side wall described in Partial Height carries out corona treatment.
4. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that the parameter of the corona treatment It include: H2Or the gas flow of He is 100sccm to 1000sccm, bias power is 200W to 2000W, and the process time is 5 seconds To 12 seconds.
5. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that at least remove the side wall of Partial Height The step of include: that the spacer material through the corona treatment, the wet-etching technology are removed using wet-etching technology Used etching solution is hydrofluoric acid solution.
6. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that the volume hundred of the hydrofluoric acid solution Dividing specific concentration is 1:1000 to 1:100.
7. the forming method of semiconductor structure as described in claim 1, which is characterized in that in the step of forming the groove, The side wall is removed, the groove is made to expose the substrate between the barrier layer and the gate structure.
8. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material on the barrier layer is oxidation One of silicon, silicon nitride, silicon oxynitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride, boron nitride and boron carbonitrides are a variety of.
9. the forming method of semiconductor structure as described in claim 1, which is characterized in that the barrier layer with a thickness of 2nm To 5nm.
10. the forming method of semiconductor structure as described in claim 1, which is characterized in that the shape on the side wall of the side wall It behind barrier layer, is formed before the groove, the forming method further include: form etching stop layer on the substrate, institute Etching stop layer is stated also to cover at the top of the barrier layer side wall and top, the side wall and at the top of the gate structure；
First medium film is formed on the etching stop layer, the first medium film covers the etching at the top of the gate structure Stop-layer；
Using flatening process, removal is higher than first medium film and etching stop layer at the top of the gate structure, described in exposing The top of gate structure, the remaining first medium film after the flatening process is as second dielectric layer.
11. the forming method of semiconductor structure as described in claim 1, which is characterized in that after forming the groove, form institute Before stating first medium layer, the forming method further include: form etching stop layer, the etching stop layer on the substrate It also covers at the top of the barrier layer side wall and top, the groove top and the gate structure；
First medium film is formed on the etching stop layer, the first medium film covers the etching at the top of the gate structure Stop-layer；
Using flatening process, removal is higher than first medium film and etching stop layer at the top of the gate structure, described in exposing The top of gate structure, the remaining first medium film after the flatening process is as second dielectric layer.
12. the forming method of semiconductor structure as described in claim 10 or 11, which is characterized in that form the first medium The step of layer includes: that second medium film is formed in the second dielectric layer, and the second medium film is also located at the groove top In the partial depth in portion；
Using flatening process, removal is located at the second medium film at the top of the second dielectric layer, retains the in the groove Second medium film is as the first medium layer.
13. the forming method of semiconductor structure as described in claim 1, which is characterized in that the gate structure is pseudo- grid knot Structure, after forming the air side wall, the forming method further include: remove the gate structure；
After removing the gate structure, metal gate structure is formed at the gate structure position.
14. a kind of semiconductor structure characterized by comprising
Substrate；
Gate structure is located in the substrate；
Barrier layer, on the side wall of the gate structure；
Groove, between the gate structure and the barrier layer, the groove at least exposes the part of the gate structure Side wall；
First medium layer, in the partial depth of the groove top, the first medium layer, barrier layer and gate structure enclose At air side wall.
15. semiconductor structure as claimed in claim 14, which is characterized in that the material on the barrier layer is silica, nitridation One of silicon, silicon oxynitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride, boron nitride and boron carbonitrides are a variety of.
16. semiconductor structure as claimed in claim 14, which is characterized in that the barrier layer with a thickness of 2nm to 5nm.
17. semiconductor structure as claimed in claim 14, which is characterized in that the air side wall also by the gate structure and Substrate between the barrier layer surrounds.
18. semiconductor structure as claimed in claim 14, which is characterized in that the semiconductor structure further include:
Etching stop layer covers the side wall of the substrate and the barrier layer；
Second dielectric layer is located on the etching stop layer, and the second dielectric layer exposes the top of the gate structure.
CN201711427817.7A 2017-12-26 2017-12-26 Semiconductor structure and forming method thereof Active CN109962014B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201711427817.7A CN109962014B (en) 2017-12-26 2017-12-26 Semiconductor structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201711427817.7A CN109962014B (en) 2017-12-26 2017-12-26 Semiconductor structure and forming method thereof

Publications (2)

Publication Number Publication Date
CN109962014A true CN109962014A (en) 2019-07-02
CN109962014B CN109962014B (en) 2022-10-04

Family

ID=67021703

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711427817.7A Active CN109962014B (en) 2017-12-26 2017-12-26 Semiconductor structure and forming method thereof

Country Status (1)

Country Link
CN (1) CN109962014B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112635324A (en) * 2019-09-24 2021-04-09 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN113053751A (en) * 2019-12-27 2021-06-29 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN113809007A (en) * 2020-06-11 2021-12-17 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1203445A (en) * 1997-06-23 1998-12-30 日本电气株式会社 Method of manufacturing semiconductor device of which parasitic capacitance is decreased
US6093612A (en) * 1997-05-24 2000-07-25 Lg Semicon Co., Ltd. Metal oxide silicon field effect transistor (MOSFET) and fabrication method of same
US20080040697A1 (en) * 2006-06-21 2008-02-14 International Business Machines Corporation Design Structure Incorporating Semiconductor Device Structures with Voids
US7994040B2 (en) * 2007-04-13 2011-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and fabrication thereof
CN103094192A (en) * 2011-11-01 2013-05-08 中芯国际集成电路制造(上海)有限公司 Forming method of semiconductor device
US20130248950A1 (en) * 2012-03-20 2013-09-26 Samsung Electronics Co., Ltd. Semiconductor devices and method of manufacturing the same
CN103390644A (en) * 2012-05-08 2013-11-13 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof
US20140024192A1 (en) * 2012-07-20 2014-01-23 Samsung Electronics Co., Ltd. Method for Fabricating Semiconductor Device
CN103578989A (en) * 2012-07-20 2014-02-12 中芯国际集成电路制造(上海)有限公司 MOS device, manufacturing method of MOS device and manufacturing method of CMOS devices
US20150187594A1 (en) * 2013-12-26 2015-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Composite Structure for Gate Level Inter-Layer Dielectric
US20150263122A1 (en) * 2014-03-12 2015-09-17 Taiwan Semiconductor Manufacturing Co., Ltd. Air-gap offset spacer in finfet structure
US9443956B2 (en) * 2014-12-08 2016-09-13 Globalfoundries Inc. Method for forming air gap structure using carbon-containing spacer
CN106104807A (en) * 2014-03-10 2016-11-09 高通股份有限公司 Wherein define the semiconductor device in gap
WO2017111770A1 (en) * 2015-12-23 2017-06-29 Intel Corporation Transistor with dual-gate spacer
CN107851659A (en) * 2015-07-17 2018-03-27 英特尔公司 Transistor with air gap separation body

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6093612A (en) * 1997-05-24 2000-07-25 Lg Semicon Co., Ltd. Metal oxide silicon field effect transistor (MOSFET) and fabrication method of same
CN1203445A (en) * 1997-06-23 1998-12-30 日本电气株式会社 Method of manufacturing semiconductor device of which parasitic capacitance is decreased
US20080040697A1 (en) * 2006-06-21 2008-02-14 International Business Machines Corporation Design Structure Incorporating Semiconductor Device Structures with Voids
US7994040B2 (en) * 2007-04-13 2011-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and fabrication thereof
CN103094192A (en) * 2011-11-01 2013-05-08 中芯国际集成电路制造(上海)有限公司 Forming method of semiconductor device
US20130248950A1 (en) * 2012-03-20 2013-09-26 Samsung Electronics Co., Ltd. Semiconductor devices and method of manufacturing the same
CN103390644A (en) * 2012-05-08 2013-11-13 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof
US20140024192A1 (en) * 2012-07-20 2014-01-23 Samsung Electronics Co., Ltd. Method for Fabricating Semiconductor Device
CN103578989A (en) * 2012-07-20 2014-02-12 中芯国际集成电路制造(上海)有限公司 MOS device, manufacturing method of MOS device and manufacturing method of CMOS devices
US20150187594A1 (en) * 2013-12-26 2015-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Composite Structure for Gate Level Inter-Layer Dielectric
CN106104807A (en) * 2014-03-10 2016-11-09 高通股份有限公司 Wherein define the semiconductor device in gap
US20150263122A1 (en) * 2014-03-12 2015-09-17 Taiwan Semiconductor Manufacturing Co., Ltd. Air-gap offset spacer in finfet structure
US9443956B2 (en) * 2014-12-08 2016-09-13 Globalfoundries Inc. Method for forming air gap structure using carbon-containing spacer
CN107851659A (en) * 2015-07-17 2018-03-27 英特尔公司 Transistor with air gap separation body
WO2017111770A1 (en) * 2015-12-23 2017-06-29 Intel Corporation Transistor with dual-gate spacer

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112635324A (en) * 2019-09-24 2021-04-09 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN113053751A (en) * 2019-12-27 2021-06-29 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN113053751B (en) * 2019-12-27 2023-05-05 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN113809007A (en) * 2020-06-11 2021-12-17 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN113809007B (en) * 2020-06-11 2024-03-01 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Also Published As

Publication number Publication date
CN109962014B (en) 2022-10-04

Similar Documents

Publication Publication Date Title
CN105470132B (en) The forming method of fin field effect pipe
CN106684144B (en) The manufacturing method of semiconductor structure
US7915167B2 (en) Fabrication of channel wraparound gate structure for field-effect transistor
CN110277316A (en) Semiconductor structure and forming method thereof
CN110265301B (en) Semiconductor structure and forming method thereof
CN109427664A (en) Semiconductor structure and forming method thereof
CN112309861A (en) Semiconductor structure, forming method thereof and transistor
CN105448730B (en) Semiconductor structure and forming method thereof
CN112017963A (en) Semiconductor structure and forming method thereof
CN106952908A (en) Semiconductor structure and its manufacture method
CN109962014A (en) Semiconductor structure and forming method thereof
CN108461544A (en) Semiconductor structure and forming method thereof
CN110957220B (en) Semiconductor structure and forming method thereof
CN106876335A (en) The manufacture method of semiconductor structure
CN112151377B (en) Semiconductor structure and forming method thereof
CN106876273B (en) The manufacturing method of semiconductor structure
CN111341661B (en) Transistor and forming method thereof
CN110858544A (en) Semiconductor device and method of forming the same
CN114068704B (en) Semiconductor structure and forming method thereof
CN111490092B (en) Semiconductor structure and forming method thereof
CN109309088A (en) Semiconductor structure and forming method thereof
CN109003899A (en) The forming method of semiconductor structure and forming method thereof, fin formula field effect transistor
CN111261517B (en) Semiconductor structure and forming method thereof
CN109285876B (en) Semiconductor structure and forming method thereof
CN109087892B (en) Semiconductor structure, forming method thereof and forming method of fin field effect transistor

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant