TW523917B - Nonvolatile semiconductor memory capable of random programming - Google Patents

Abstract

A nonvolatile semiconductor memory capable of random programming has a semiconductor substrate of first conductivity type having a memory region, a deep ion well of second conductivity type located in the semiconductor substrate within the memory region, a shallow ion well of first conductivity type isolated by a STI layer within the deep ion well, at least one NAND cell block located on the semiconductor substrate within the shallow ion well, and a bit line located over the semiconductor substrate to provide a first predetermined voltage for the shallow ion well during a data programming mode and to provide a second predetermined voltage for the shallow ion well during a data erase mode via a conductive plug which electrically connects the bit line and extends downwardly to the shallow ion well.

Description

523917 V. Description of the invention (1) Field of the invention The present invention provides a non-volatile semiconductor memory (n〇n-v〇utile semiconductor memory), especially a NAND-type non-volatile semiconductor that can be randomly coded (random programming). Memory. Background: Because flash (f 1 ash) electronic erasable programmable read-only memory (EEPROM) has the advantages of high density, etc., in today's electronic rewriteable non-volatile In terms of storage of sexual data, it has a wide range of applications. The main process structure of Flash C memory can be divided into two types: NOR and NAND. The products are mainly program conversion-based storage program code flash and data access storage. Flash memory (data flash). The former is used for program conversion and reading because it is fast, and it is mostly used for line and electricity. As for the latter, because of its high density, it is used for memory cards of digital cameras, information cameras, and other products. Among them, NAND-type flash memory has unlimited development potential due to increasing demand. As far as the current flash EEPROM is concerned, it can be divided into several different forms, one of which is the use of a bi-directional Fuluohan tunneling mechanism (Fowler-Nordheim tunneling mechanisin 'FN). ) To operate EE PROM. Please refer to the figure for a cross-sectional view of the conventional NAND-type EEPR0M 10

523917 V. Description of Invention (2) Intention. As shown in FIG. 1, the NAND-type EEPROM 10 includes a semiconductor substrate 12 ′ having a memory region; and a semiconductor well (semiconcjuctor we 1 1) 1 4 disposed in the semiconductor substrate in the memory region 2 A plurality of NAND cell block B is disposed on the semiconductor well 14 of the semiconductor substrate 12; and a bit line BL1 is disposed above the semiconductor substrate 12. In addition, the NAND memory string block b includes a plurality of rewritable memory cells (mem 0 ryce 1 1) M, and is connected in series with each other along the direction of the bit line BL1, and at the same time, in Adjacent memories _ under the same bit line BL1 share the doped regions under them as source (source) and; and (drai η) to form NAND-type memory cells. For example, the memory cell M 1 1 4 uses the doped region 丨 6 as the source and the doped region 18 as the drain '. However, the doped region 18 is also the source of the memory cell M 1 1 5 . In addition, Lu Jiyi's cell M has a stacked gate structure. For example, the upper layer of the memory cell 114 is a control gate ((: 01 ^ 1 «〇12 ^ 6) 2〇, and the lower layer is a storage charge The floating gate (f 1 〇atinggate) 2 2 is separated by an insulation film (insulator fi im) 24. Furthermore, one end of the series memory cell is electrically connected to the bit line BL1 through a plug 26, A selection transistor ST is provided at the other end of the tandem memory cell and is electrically connected to a source line (source ine) s L. At the same time, the control gate of the memory cell M is electrically connected. Connected to a word line (w 0 rd 1 ine) (not shown) perpendicular to the bit line bl 1. In this way, all tandem memory cells driven by the same word line are defined as a NAND memory string area For the conventional NAND-type EEPR0M 10, when a coding mode is performed,

523917 V. Description of the invention (3) In the formula, it is necessary to apply a round of voltage (such as 20 volts) to the selected character line to drive the operation of the memory. At the same time, for non-selected zigzag lines, a large voltage (such as 12 V) is required to turn on the channel (channe 1). In this case, it will consume a lot of power, and because each word line has to be applied with voltage, it will appear slow in speed. In addition, due to the existence of high voltage, problems may arise in terms of reliability, such as junction breakdown. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a non-volatile semiconductor memory that can be randomly coded to solve the above-mentioned conventional problems. In a preferred embodiment of the present invention, a non-volatile semiconductor memory capable of random programming includes: a first conductive semiconductor substrate having a memory region; and a second conductive deep ion well. Is located in the semiconductor substrate in the memory region; a first conductive shallow ion well is located in the deep ion well, and is covered by a shallow trench insulation layer (8 丁 11 & 761 ') Isolation; at least one NAND cell block is disposed on the semiconductor substrate in the shallow ion well; and a bit line is disposed above the semiconductor substrate for extending to the shallow ion by a Plug of well (p 1 ug), improved in a coding mode

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The electric non-volatile semiconductor memory is provided in a erase mode. The non-volatile semiconductor memory of the present invention forms a shallow ion well in a deep ion well, and extends the plug into the shallow ion well as a common electrode. electrode), which can avoid the need to apply voltage to each character line in the conventional method. That is to say, according to the structure of the present invention, when a non-volatile semiconductor memory is subjected to a coding mode, it is only necessary to apply a selected voltage to a selected word line. In this way, power can be saved greatly , And shorten the access time, thereby improving memory performance. Detailed description of the invention Please refer to FIG. 1 ′ FIG. 2 is an equivalent circuit diagram of the NAN D type non-volatile semiconductor memory device 30 of the present invention. As shown in FIG. 2, the NAND memory string block b includes a plurality of rewriteable memory cells (memory cel 1) M, and along the direction of the bit line (bit 1 i ne) BL1, Connected in series. In addition, one end of the tandem memory cell is electrically connected to the bit line BL1, and a selection transistor ST is provided at the other end of the tandem memory cell, and is connected to a source line SL Electrical connection 0 Please refer to FIG. 3 and FIG. 4. FIG. 3 is a NAND type nonvolatile semiconductor according to the present invention.

523917 V. Description of the invention (5) Layout drawing of body memory 30. FIG. 4 is a cross-sectional view of the NAND-type nonvolatile semiconductor memory 30 in FIG. 3 along the bit line BL1. As shown in FIGS. 3 and 4, the NAND-type non-volatile semiconductor memory 30 includes a first conductive semiconductor substrate 32 having a memory region; and a second conductive deep ion well 34 provided in the memory region. Inside the semiconductor substrate 32; a first conductivity type shallow well 36 is located in the deep ion well and is isolated by a shallow trench insulation layer (STI 1 ayer) 3 8; a plurality of NAND memories A NAND cell block B is disposed on the semiconductor substrate 32 in the shallow ion well 36; and a bit line BL is disposed above the semiconductor substrate 32 for extending to the shallow A plug (pi Ug) 40 of the ion well 36 provides the shallow ion well 36-a first predetermined voltage in an encoding plate type, and provides the shallow ion well 36-a second predetermined voltage in an erase mode. According to a preferred embodiment of the present invention, the semiconductor substrate 32 is a p-type semiconductor substrate, and the deep ion well 34 is an N-type conductivity type, and the shallow ion well 36 is a P-type conductivity type. Of course, the present invention is also applicable to the case where the n-type conductivity type is used as the semiconductor substrate 32. At this time, the deep ion well 34 is a P-type conductivity type and the shallow ion well 36 is an N-type conductivity type. In addition, the shallow ion well 36 has a well depth (we 1 1 depth) smaller than the thickness of the shallow trench insulation layer 38. In this embodiment, the thickness of the 'shallow trench insulation layer 38 is about 300 to 40 00A. Meanwhile, the doping dose of deep ion well 34 is about 1 £ 12 to iE13 at 0ms / m2, while the doping dose of shallow ion well is about 1E13 to 1E14 atoms / m2. In addition, the NAND memory string block B contains a plurality of rewritable

523917 V. Description of the invention (6) Memory cells M, which are connected in series with each other along the direction of bit line BL, and adjacent memory μ below the same bit line BL shares the same The doped region serves as a source (source) and a drain (drai η) to form a NAND-type memory cell. For example, the memory cell Ml 1 4 uses the doped region 42 as a source 'and the doped region 44 as a drain. However, the doped region 4 4 is also the source of the memory cell M 115. In addition, according to a preferred embodiment of the present invention, the memory cell M has a stacked gate structure. For example, the upper layer of the memory cell M1 1 4 is a control gate formed of polysilicon (p0iySiijcon). (control gate) 46. The lower layer is a floating gate 48 for storing electric charges, which is separated by an insulating film (insulat rn lm) 50. The insulating film 50 may be an oxygen nitrogen oxide film. (Oxide_nitride — oxide, ON). Of course, the gate structure of the present invention can also be a sonok gate structure, that is, a 10N layer is directly deposited on the shallow ion well 36, and then a layer of debris is deposited as the Control gate 4 6. At the same time, the control gates of the memory cells M perpendicular to the bit line b l are each electrically connected to the corresponding word line WL. In this way, all the serial memory cells driven by the same word line are defined as a NAND memory string block. In addition, one end of the tandem memory cell is electrically connected to the bit line BL through a plug 40. In order to extend the plug 40 into the shallow ion well 36, the contact hole needs to be etched to After the surface of the shallow ion well 36 is etched vertically downward through the drain doped region of the memory cell into the shallow ion well 36. In addition, as shown in Figure 5, the form of the source line SL may be in addition to the buried heavily doped region su shown in the nonvolatile semiconductor memory 30.

Page 10 523917 V. Description of the invention (7) A metal wire (m e t a 1 w i r i n g) S L 1 ′ is connected to the heavily doped region 54 through the plug 5 2. FIG. 6 shows the operating conditions of a non-volatile semiconductor memory with a stacked gate structure in the present invention. As shown in FIG. 6 and taking the non-volatile semiconductor memory 30 as an example, when the non-volatile semiconductor memory 30 performs a coding mode, a voltage of 5V needs to be applied to the bit line BL. Since the bit line BL is electrically connected to the shallow ion well 36 through the plug 40 extending to the shallow ion well 36, the bit line BL will also provide a voltage of 5 V in the shallow ion well, and this shallow ion can be seen The well 36 is a common electrode. In this way, when a memory cell M is selected for encoding, only a voltage of an appropriate magnitude is applied to the selected character line table, and no voltage is applied to all the character line companies, and Fulnohan can be used. Tunneling mechanism (Fowler-Nordheim tunneling mechanism, FN). In the preferred embodiment of the present invention, the voltage applied to the selected word το line WL is about -10V, and the source line SL For floating (floating), the gate voltage of the transistor sT is selected as 0V. In addition, when Tian Qianji and other body memories perform an erase mode, a voltage of -10V needs to be applied to the source line. Erase mode = memory = and erase, so all the word lines _ apply two electric ridges, the bit line BL at this time is floating (fi〇ati), select the transistor ST is 0V, It is also erased using the FN tunneling mechanism. Actually: Here: the operation of the volatile semiconductor memory 30 uses a bidirectional FN tunneling machine.

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V. Description of the invention (8) and 'When the non-volatile semiconductor memory 30 is in a read mode, a voltage of 0V is applied to the bit line BL, and a voltage of 5V is applied to the gate of the selected selection transistor ST2, As for the gate of the unselected selection transistor δTχ, it remains ον. At the same time, a voltage of ^ is also applied to the unselected word line WLx, and the selected word line WL is set to 0V for reading, and 5 to 5 are applied to the source line SL. As mentioned above, in addition to the stacked gate structure, the non-conductor memory of the present invention can also be constructed using a SONOS memory cell. As for the operating conditions of this non-volatile semiconductor memory with X-Son SONOS memory cells, it is shown in Figure VII. It can be seen from Figure VII that in the encoding and erasing modes, the voltage required to use the non-volatile semiconductor memory of the SONOS memory cell is equal to "T gigabit is low. That is, this use of s_ 二 隐The cellular conductor memory not only has a relatively rough manufacturing process, but also forms a shallow ion well compared to the conventional non-volatile semiconducting well, and uses this shallow ion well as each character line in a common electrical method. The high pulsating voltage required for the non-volatile semiconductor memory exposed by the applied voltage can be obtained. In other words, the volatile semiconductor memory performs a coded memory, and the invention extends to the pole of the plug connected to the bit line in deep ions. It can avoid the need of the knowing party. Moreover, with the structure of the present invention, the structure according to the present invention in the conventional technology can also be eliminated.

523917 V. Description of the invention (9) It is only necessary to apply a proper voltage to the line. In this way, it can greatly save power and shorten the access time (a c c s s t i m e), thereby improving the memory performance. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent.

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Brief Description of the Drawings Brief Description of the Drawings Figure 1 is a schematic cross-sectional view of a conventional NAND-type EEPROM. FIG. 2 is an equivalent circuit diagram of the NAND type non-volatile semiconductor memory of the present invention. FIG. 2 is a layout diagram of a NAND type non-volatile semiconductor memory according to the present invention. FIG. 4 is a cross-sectional view of the NAND type non-volatile semiconductor memory in FIG. 3. There are 1 疋 green Η Figure 5 shows another implementation of the NAND-type non-volatile semiconductor memory of the present invention. _Body = Ϊ f The non-volatile semiconductor of the present invention with a stacked gate structure UIS is a dull working condition. Emotional body == t The operating conditions of the non-volatile semiconductor body G of the present invention with a SONOS memory cell. Explanation of symbols in the figure 10! 2> 32 16, 18 22, 48 26, 40, 52 30, 50 34 NAND type EEPROM semiconductor substrate 14 Doped region of semiconductor well 2 0, 4 6 Control gate floating gate 24 Insulating film insertion Plug non-volatile semiconductor memory deep ion well 36 shallow ion well

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Claims (1)

523917 VI. Scope of patent application1. A non-volatile semiconductor memory, which can be random coded. The non-volatile semiconductor memory includes: a conductive semiconductor substrate with a memory area; a second conductive A deep ion well of the first type is provided in the semiconductor substrate in the memory region. A shallow conductive well of the first conductivity type is provided in the deep ion well and is formed by a shallow trench insulation layer (STI 1 ayer). Isolated; at least one NAND memory string block (NAND ce 1 1 b 1 ock) is provided on the semiconductor substrate in the shallow ion well; and a bit line is provided above the semiconductor substrate for use by a The plug (P 1 ug) extending to the shallow ion well provides a first predetermined voltage of the shallow ion well in a coding mode, and provides a second predetermined voltage of the shallow ion well in an erase mode. 2. The non-volatile semiconductor memory according to item 1 of the scope of patent application, wherein the shallow ion well has a well depth (we 1 1 depth) smaller than the thickness of the shallow trench insulation layer. 3. The non-volatile semiconductor memory according to item 1 of the scope of the patent application, wherein the first conductivity type is a P type and the second conductivity type is an N type. 4. The non-volatile semiconductor memory according to item 1 of the scope of the patent application, wherein the NAND memory string block includes a plurality of rewritable tandem memory cells and a selective transistor 523917 6. The scope of patent application (selecting transistor) is set at one end of the tandem memory cell, and the plug is set at the other end of the tandem memory cell. 5. The non-volatile semiconductor memory according to item 4 of the scope of the patent application, wherein the selective transistor system is electrically connected to a source line (s0 u r c e 1 丨 n e). 6 _ The non-volatile semiconductor memory according to item 4 of the scope of patent application, wherein the memory cell includes a stacked gate structure. 7. The non-volatile semiconductor memory according to item 4 of the scope of patent application, wherein the memory cell line is a SONOS memory cell. 8 · An erasable programmable read-only memory (EEPROM), which includes: a semiconductor substrate with a memory area; a shallow ion well located in the In the memory area, it is isolated by a shallow trench insulation layer; a deep ion well is located below the shallow ion well in the memory area; a plurality of NAND memory string blocks (NAND cel 1 block) are provided in the On the semiconductor substrate in the shallow ion well; and at least one bit line is provided above the semiconductor substrate, and the bit line is connected to the shallow ion well by a plug (p 1 ug) extending to the shallow ion well; connection. 523917 6. Scope of patent application 9. The erasable and codeable read-only memory described in item 8 of the scope of patent application, wherein each of the shallow ion wells has a well depth smaller than the thickness of the shallow trench insulation layer. 10. The erasable and codeable read-only memory as described in item 8 of the scope of patent application, wherein the bit line provides a first predetermined voltage of the shallow ion well in an encoding mode, and in an erasing mode A second predetermined voltage is provided for the shallow ion well. 1 1. The erasable and codeable read-only memory as described in item 10 of the scope of patent application, wherein the coding mode is performed using a Fowler-Nordheim tunneling mechani sm. 12. The erasable and codeable read-only memory according to item 10 of the scope of patent application, wherein the first predetermined voltage is 5 volts and the second predetermined voltage is -10 volts. 1 3. The erasable and codeable read-only memory as described in item 8 of the scope of the patent application, wherein each of the NAND memory string blocks includes a plurality of rewritable tandem memory cells and A selection transistor (se 1 ectingtransistor) is provided at one end of the tandem memory cell. 1 4. The erasable and codeable read-only memory as described in item 13 of the scope of patent application 523917 6. The scope of patent application, in which the selected transistor system is electrically connected to a source line (s0 u r c e 1 i n e). 15. The erasable and codeable read-only memory as described in item 13 of the scope of the patent application, wherein the memory cell includes a stacked gate structure. 16. The erasable and codeable read-only memory according to item 13 of the scope of patent application, wherein the memory cell is a SONOS memory cell. Page 19