TW523896B - Critical range method of using spin coating on glass to reduce double-layer embedding method - Google Patents

Abstract

A kind of method for forming wiring structure inside the integrated circuit device is disclosed in the invention. In the conducted example, a substrate is first provided and an inter dielectric layer is formed on the substrate. An etch stop layer is then formed, in which the etch stop layer is etched and patterned. A dielectric layer is formed to cover the etch stop layer; and the photoresist (PR) mask is also formed and defined. An opening position of the dielectric layer is formed on the second insulation layer of the first insulation layer such that the etch stop layer is inside the opening. The PR mask is stripped and the first conductive metal layer is deposited. The PR mask is again formed and defined. The extra conductive metal is removed and is followed by depositing the second conductive metal layer. Finally, the integrated circuit surface is flattened.

Description

j ^ 896 Amendment No. 88109873 ', Description of the invention (1) 5% 1 Field of the invention The present invention relates to a half of the guides, the living person, the small a, and the makeup of each piece contains an internal connection structure, including the bottom The electrical conductivity of the material begins with ~ Ώ ^ Shanshou Dianzhuang Wood Green, and an internal connection structure formed by using a more practical double-layer crater method. 2. Background of the Invention Generally, the conventional method of forming an interconnect structure will terminate the application of negative engraving and etching steps, the basic metal pattern etching technology, and develop a two-layer embedded process technology. The dielectric structure of the junction dielectric ik is formed in the junction body. The technical diagram of the elemental silicon layer is shown in the first A to the first j, and the inner layer of the first A = The electrical layer is an oxide layer 112, and the semiconductor layer is a single layer. In the first B diagram, a conductive contact / dielectric layer 113 is formed inside, and an inner dielectric layer 114 is deposited over the etching stop layer us and is turned into a stone. In the first figure C, the interconnect structure includes at least a conductor, a layer 113, and a conductive wire 114, and the photoresist mask 115 is |, and the layer 114 is above the wire etching pattern. Completed In Figure D, the overhead line engraving pattern is shaped using lithography technology. 11 —The photoresist layer 11 6 in the figure provides a overhead line engraving pattern.

Page 4 L: Same as in the first F chart, the line etching pattern formed. At 2: the photoresist mask is removed. Finally, the metal is not only deposited on the semiconducting surface, but the mouth is as shown in the first figure. In -1 ^^ 8109873 ^ V.% Explanatory Note (2) ^^^ In the first ~ I figure, too much of this genus eve ^ to genus is removed by chemical mechanical polishing process. Usually, 轫 ^ U # and photoresist layer are formed and used. It has one or one different resolution step-by-step alignment machine, and the thickness of the screen. However, in the use of high process, it will be difficult to form a deeper focal length, which will not only produce yield. It can reduce the production range and reduce the reliability of production. When a semiconductor integrated circuit is formed, the first layer Θ connection with the integrated circuit element substrate will be formed in the second circuit; ^ 处 'more inside ... or outside the integrated circuit element structure. Integrated Circuits has 3 objectives and summary of the invention: Method, practical and complete evaluation of the semiconductor components that are used to form integrated circuit components that are in violation of the estimates. In one embodiment, first, two layers are provided on the substrate, and then a second dielectric layer is formed on a χ stop layer. A pattern is formed on the etch stop layer and the first inner dielectric layer until the substrate is exposed. Then deposit a photomask to define the conductive metal on the conductive metal layer, and for the first engraving and then the substrate, stop, first form the electrical layer of the electrical pattern of the photomask and then set the metal layer, followed by the second Righteousness; the next step

523896 _ Case No. 88109873_ 年月 日 __ V. Description of the invention (3) until the etching stop layer is exposed. A second, conductive metal layer is then deposited and its surface is planarized. Obviously, since the present invention can use a longer focal length in the process, the method of the present invention can be applied to a thicker photoresist layer. This will not only produce a thinner critical range, but also increase production reliability. Figure 5-4 is a brief description: Figures A through I are cross-sectional structural diagrams of a conventional semiconductor device manufacturing process. Figures 2A to 2D are cross-sectional structural views showing an embodiment of the present invention. Description of drawing number: In the first picture 112 oxide layer 111 semiconductor layer 113 conductive contact / dielectric layer 114 internal dielectric layer 115 photoresist mask 116 photoresist layer, as in the second picture 111 semiconductor substrate

Page 6 V. Description of the invention (4) 1 1 2 Silicon oxide layer 1 1 3 Silicon nitride layer as shown in Figure 1B 21 Spin-coated glass layer 2 2 Photoresist mask 5-Detailed description of the invention Second A The diagrams to the second H diagrams show that in this embodiment, the substrate η is embedded by two layers: = This' The process of this substrate will be described in detail in the following section. In the second piece of Figure A, firstly, half of the substrate is formed using a PECVD method to deposit monoxide / thorium oxide, and then the mvD method 12 'is used above the fossil layer to form the oxygen stop layer. Once again, at this nitrogen / electron-oxygen cut layer 113, the hafnium patterning process has been completed. / As shown in FIG. 2B, the spin-on-glass method is used: glass layer 21 ”: FIG. 2c shows the semiconductor element J-face mask 22. Then, as shown in FIG. Pattern, and use reactive ion etching to remove the n :: broken glass layer 21 and excess oxygen-cut layer 如. Such as the second heart:; turn = 523896

F 'in the figure f-F figure shows' removing the spin-coated glass layer 21. Second, the coating glass layer 21 is removed by using a ten-to-tenth ratio of Sigma and two UiiJ: K〇Η solution, because the spin coating glass shows that the ratio is about forty to one. The second ㈣ full of the openings. The / W to the metal layer 23 is filled and removed from the surface of the semiconductor element. ^ Chemical mechanical polishing is the preferred embodiment of the present invention. The two types of insulating wires and the semiconductor bottom edge layer form an insulation to open the circuit. The momentary stop layer in the remaining layers, and then wired in the electrical material, after the dielectric is electrically connected into a pattern-integrated circuit element ^: ^: / using the original ^ substrate-interlayer method, at least Including the formation of a conductive material on the substrate and the formation of a ::::: "on the substrate-to provide an etching stop layer, then ^ g, and then the first insulation layer. = On the upper layer of Cheng Cheng's mouth, and the opening continues through the 『ί;:; the first position in the layer is engraved in the suspension layer. Then on the 6th edge layer, the sub-completely two positions form a trench, = tj take the second insulation and the first insulation layer of the line. At the mouth, reach the inside of the opening and the ditch;: cover = the conductive material layer completely fills the outlet and the mouth: A conductive material, that is, a conductive layer is formed at the etching stop layer and the second opening, and the conductive interlayer is conductive; : The trenches are formed - conductively connected; and the conductive substrate is a wood substrate and provide a layer between the definition of the final ^ = a conductive material on an overhead wire, where the needle-shaped surface planarization.

523896

Jj ^ _88109873 V. Description of the invention (6) d = The material of the edge layer and the second insulating layer are both oxidized stone layers, and the material of the stop layer is selected from the heterogeneous group consisting of nitrogen cut and polycrystalline silicon μ ^ oxynitride) Usurp #I. The step of forming the first pattern mask is to cover the second insulating layer to form the first pattern mask, "the first position of the upper edge of the euphemum layer is formed to open. Remove the first mask The second position-shaped stop layer of the first insulation layer and the first insulation layer layer are provided to form the opening; it can form a trench and at the same time in an interlayer. The first and second passes are completed. The part of the wire receiving the grinding And, at least the material can include, some materials can be covered by aluminum, tungsten, and the curtain into the second trench, and can be used. The first etching insulation layer can be used, and the trench can be used at the same time through the etching process. The etching process is stopped at least partly by a chemical machine or without an attached copper and a similar nicking process. The second and first insulating layers can be made of a reactive ionization insulating layer containing a mechanical abrasive / screen alloy group. It is formed by grinding. The metal of the barrier layer is formed. In the second and the engraving, the second insulating layer is formed in the shape of a sub-rhyme. The conductivity is conductive. The metal described above is only the present invention. Patent application · Λ L penetration embodiments only, not the lower limit for the completion of the weaving spirit equivalent change to all other disclosed without departing from the scope of the present invention patent &. Or repair potential "should be included in the application of the following

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Claims (1)

523896 _—Case No. 88109873 ___ ^ _ g_Amendment ____ VI. Scope of Patent Application 1 · A method for controlling the critical range of an integrated circuit element with a multi-layer conductive structure, including at least: providing a substrate; forming an intermediary An electrical layer is on the substrate; a stop layer is formed for a while and the etch stop layer is pattern-etched; a dielectric layer is formed on the stop layer for the etch; the dielectric layer defines a wiring line after the pattern is cut. Hne); depositing a first conductive metal layer; pattern etching the first conductive layer to define a wiring line above the inner dielectric layer in the etching stop chip, and removing the excess of the first conductive layer A conductive metal layer; a first conductive metal layer; and planarizing a surface of the integrated circuit element. The first method of forming a semiconductor device includes: forming a first layer, forming a first layer, forming a first layer, forming an open conductive wire and a via layer on the substrate in the remaining moment, and engraving the semiconductor element. The edge layer is above the substrate; the stop layer is above the first insulating layer; the edge layer is above the etching stop layer; the first insulation and the second insulation layer together form the opening of the Chu in the interlayer ; 1 ,; 1 ~ -〆2 insulation layer Page 10 ^ S_88109873 Sixth, within the scope of the patent application, go up in the area of the channel forming the shell, the area; in the sink area, the first area between the substrates in the interlayer area is flattened to the first position, and the opening to the etching stop layer The wiring area has been formed to penetrate the etching stop layer and the trench, and at the same time, the conductive area is not included in the wiring area. A conductive material is completely contained in the conductive material to provide an electrical conductivity in the wiring area. Connection; and a table of the conductive material Π runs through the second ', the opening is one, the second insulation layer, the wooden line area within the first insulation layer, that is, the trench portion, the line area and the ground fill the line area An interlayer is formed, and the conductive surface is formed. The insulating layer and completely wiring the area; the second position inside, so that the substrate is exposed to the trench, the wiring is ~ conductive dielectric layer, the conductive dielectric area and the conductive dielectric, and the conductive dielectric is in the conductive dielectric. The layer is a wire and the second insulation layer such as the scope of the patent application is an oxide layer. , /, /, The above first insulating layer and 5 · As in the method of applying for a patent jf] # π ^ w IL ^ ^ h ^ 3 methods, wherein the above-mentioned money is engraved with a stop layer. Λ, ^ \ 化石 夕, The material of the aerobic oxide oxide (oxynitride) and the polycrystalline silicon group, where f is the first and second insulating layers is silicon oxide. 6: 1 method of patent scope of $ 3, in which the above-mentioned formation-opening 11) is known for a first pattern cover to cover the second insulating layer, so as to cover the second insulating layer, Page 11 523896 _Case No. 88109873_Year_Month__ VI. Patent Application Scope 7. If the method of patent application No. 6 includes at least the steps of removing the first mask and providing a second mask, The second mask is provided at the second position of the second insulating layer to define the trench range. 8. For the method of claim 3, wherein the step of forming the opening at the second insulating layer is performed by a first etching process. 9. For the method of applying for the item No. 8 of the patent scope, wherein the step of forming a trench on the second insulating layer and forming a via layer on the etching stop layer and the first insulating layer at the same time, a second The etching process is completed. 10. The method according to item 9 of the scope of patent application, wherein the first etching process and the second etching process are both reactive ion etching processes. 11. The method according to item 9 of the patent application, wherein the first etching process is related to the etching stop layer and has higher selectivity than the second etching process. 12. The method according to item 3 of the scope of patent application, wherein the above-mentioned conductive material includes at least one metal with or without an adhesion / barrier layer, and the material of the metal may be composed of Ill, crane, copper, and similar alloys. 1 3. The method according to item 3 of the scope of patent application, wherein the conductive material is removed as described above. Page 12 523896 _Case No. 88109873_ Years and months Amendment_ VI. Patent application scope The material contains at least one solution, and it is selected from the ten to one ratio of HF buffer and diluted KOH solution. 14. The method according to item 3 of the scope of patent application, wherein the above-mentioned planarizing the surface of the conductive material includes at least a chemical mechanical polishing process. Page 13