JPH05504446A - Semiconductor interconnect structure using polyimide insulation - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Semiconductor interconnect structure using polyimide insulating material [Industrial application field] TECHNICAL FIELD This invention relates generally to semiconductor devices and manufacturing methods.

More specifically, we will discuss interconnect structures for semiconductor devices using polyimide insulators. do.

[Background of the invention] Semiconductor devices are typically semiconductor devices formed within a substrate such as silicon or gallium arsenide. Requires formation of electrical contacts and interconnections to the device area. Current large-scale integration cycle In LSI and very large scale integrated circuit (VLSI) technologies, these electrical Contacts and interconnects are formed in multiple stages, with adjacent interconnect stages being layers of insulating material. separated by Vias are provided to accommodate contacts to the device and contacts between stages. Or holes are formed through the insulating layer. In this technical field, such mutual ``Personalization'' or ``Backend Metallization'' of the connection structure It is called ``motion''.

Traditionally, the insulating materials used for these interconnect structures have been overwhelmingly silicon dioxide. They were inorganic insulators such as silicon, silicon nitride, and glass. For example, U.S. Pat. No. 822753 is connected to a silicided device by a tungsten stud. A device structure including aluminum wires is shown. This tungsten stud The board includes titanium nitride via liners and is made from oxide, nitride, or glass. It extends through the insulating layer that is constructed. This structure should be moved upwards (i.e. Multi-layer wiring (in the direction away from the surface of the vise) that can be extended to provide multi-stage wiring techniques are known in the art.

A class of materials called "polyimides" exhibit low dielectric constants, and therefore For a period of time, it is particularly desirable for use in the interconnect structure described above. I've been recognized.

For example, U.S. Pat. No. 4,560,436 describes tapered vias within a polyimide insulation layer. It shows how to form. However, polyimide also suffers from the brittle nature of the material itself. To begin with, it has some drawbacks. Polyimide is commonly used in semiconductor processing. The contamination caused by the materials and processes used and the subsequent destruction Especially easy to accept. For example, many etching solutions are very toxic to polyimide. Yes, and so do many of the metals used to make interconnects.

European Patent Application No. 0195977 uses polyimide to develop field effect transistors. A planar insulation stage is installed in the personalization structure for transistors (FET). It shows how to In the above-mentioned application, the polyester preferably covered with silicon dioxide Etch the imide insulation to provide vias. The bottom of these vias, e.g. For example, when polyimide is roughened, it attracts selectively deposited tungsten. Acts as a tightening activator (polyimide with selectively deposited tungsten) Repeating this process using edge material results in a multi-stage interconnect structure.

The method of the above application also has a tendency to damage polyimide exposed to tungsten metal. It has some notable drawbacks, including: selectively deposited tongues The use of tens is important because shallow vias are overfilled while deep vias are filled. It cannot be easily adapted to device surfaces whose surface shapes vary. selective attachment of metals If the via is not filled (i.e. unprotected polyimide) There is a tendency for voids to remain due to outgassing (referred to as “creep up” formation). be. Furthermore, this selective deposition is limited to the metals on which it can be performed. Than Specifically, it does not work well with desirable interconnect metals such as copper, aluminum, etc. . The above application does not realize gettering of any type of mobile ions. There is a flaw that there is no.

Another example of using polyimide as an insulating material in an interconnect structure is U.S. Pat. No. 02792 and No. 4386116. The latter patent is a multi-stage mutual The former patent discloses the use of polyimide as an insulating material in connection structures; Method for forming multi-tiered interconnected structures by chemical-mechanical polishing of imide insulators Disclosed.

To the best of the inventor's knowledge, it is possible to Using imides as back-end insulators to optimize their beneficial dielectric properties and further of the prior art, which can adapt to varying surface geometries and different types of interconnect metals. There's no way.

[Summary of the invention] It is an object of the present invention to develop a new and improved semiconductor utilizing polyimide as an insulating material. An object of the present invention is to provide a body interconnect structure and a method of manufacturing the same.

Another object of the present invention is to provide interconnection to device structures with microfeatures of various heights. The object of the present invention is to provide a method and apparatus as described above, which are easily applicable to forming a connection. Ru.

Yet another object of the invention is that different types of conductors are provided in different stages of the above structure. It is an object of the present invention to provide a method and a device as described above, which can be used.

According to the invention, a semiconductor device including a device region on the surface of the substrate where it is desired to provide a conductive contact is provided. exposing a substrate of body material, a polyimide layer on top of the substrate surface, and a device area; An opening in the polyimide layer and a metal lining above the opening surface to the device area. A refractory metal stud plugs the lined opening to form a conductive contact. A semiconductor structure is provided.

According to another aspect of the invention, the device on the surface of the substrate on which it is desired to provide conductive contacts providing a substrate of semiconductor material, including a region of polyimide on the surface of the substrate; forming the layer and forming an opening in the polyimide layer to expose the device area. forming a metal lining over the open surfaces in the polyimide layer; A layer of refractory metal is placed on top of the substrate to approximately fill the lined opening in the polyimide layer. The device includes the steps of conformally forming the layer and planarizing the refractory metal layer. A method of forming a conductive contact to a chair region is provided.

[Brief explanation of the drawing] These and other features, objects and advantages of the invention will be apparent from the following detailed description of the invention. It will become clear if you read it while referring to the drawings.

FIGS. 1-9 illustrate electrical connections including interconnect structures made in accordance with the present invention. A cross-section showing the successive steps in the manufacture of a field-effect transistor (FET). It is a front view.

Figures 10-12 are encountered when etching vias in polyimide. Certain features of the present invention are utilized to overcome undercut problems. FIG.

[Detailed description of the invention] Referring now to the drawings, FIG. A fabricated field effect (FET) transistor 20 is shown. FET20 is formed adjacent to major surface 22 by a channel region 30 of substrate 24 therebetween; It includes a highly doped P source region 26 and a drain region 28 that are spaced apart. Ru. overlying the surface of the channel 30 and separated from the surface by a thin layer of insulating material 34 A gate structure is provided that includes a conductive gate contact 32 that is connected to the gate. Contact point 32 is made of, for example, metal or doped polysilicon, and the insulating material 34 is made of, for example, metal or doped polysilicon. For example, it is made of thermally grown silicon dioxide (SiO2).

FET 20 further includes oxide sidewall spacers 36.3 covering the vertical edges of the gate structure. 8 and other devices surrounding the FET 20 and formed on the substrate 24 (Fig. (not shown) includes a field oxide region 4o electrically isolating FET 2o . FET 20, including its associated microstructure, is a conventional device in the art. Many methods of preparing and manufacturing them are known. FET2 including isolation region 40 The detailed method of creating 0 is not part of this invention and need not be described in detail here. stomach.

According to the invention, a thin layer of inorganic insulating material, preferably silicon nitride (Si3N4) 44 conformally over the above structure including FET 20 and field isolation region 40. Attach to. Layer 44 is formed to a thickness of, for example, about 2000 angest combs.

Layer 44 serves to prevent contamination of subsequently deposited materials by mobile ions. be.

A layer 46 of polyimide is applied over layer 44 to form a stop between the top surface of contact 32 and surface 22. Deposit to a thickness greater than height 48, for example approximately 2.5 microns thick. polyimide Do46 is a heat-stable polyimide that withstands high temperature operation in the range of approximately 450-500°C. For example, it is preferable to use PIQ L-100 commercially available from Hitachi. Delicious.

Next, referring to FIG. 2, as fi/J in the etchback planarization stage, A layer of niboxy or resin 49 is applied to provide a rayed top surface 46A. The top surface of the polyimide layer 46 is spin-kneaded using a conventional method. Next, in Figure 2 The device can be etched by reactive ion etching (RIE) using, for example, oxygen plasma. etc., by applying a blanket etching method to the layer 46 through the layer 49. The upper surface of the middle layer 46 is planarized.

Referring now to FIG. 3, a polygon having a top surface 46A planarized in the manner described above. An imide layer 46 is shown. Following planarization of layer 46, e.g. A layer 50 of an inorganic insulating material, such as carbon dioxide, silicon dioxide, or glass, is applied to the surface of layer 46. It is deposited on the surface to a thickness of approximately 3,500 angstroms.

As discussed in more detail below, layer 50 includes an etch stop, a polish stop, etc. as well as a galley that protects the underlying polyimide from damage from subsequent process steps. Contains important features of the inventive structure that function as cods in a variety of ways.

Next, referring to Figure 4, we can see that the anisotropic reactive ion etching method Using a lithographic mask (not shown), form vias 52, 54, 56. Ru. A via 54 extends from the surface of layer 50 downwardly through layer 50.46.44; A surface portion of gate contact 32 is exposed. Vias 52 and 56 are also on the same layer. 50, 46, and 44 extending downwardly through the source region 26 and drain region 26, respectively. A surface portion of area 28 is exposed. Vias 52, 54, 56 are for example CF, plastic. Etch through layer 50 using Zuma and through layer 46 using an oxygen plasma. After removing the photoresist mask, CF and plastic are etched again. It is formed by etching through the exposed portion of layer 44 using a Zuma.

According to another advantage of the present invention, polyimide layer 46 is etched using an oxygen plasma. Twitching will ensure complete integrity without causing damage to the underlying board 24 or FET 20. This enables flat overetching. The polyimide is considerably overetched. For feature structures with varying step heights or surface topography, Although it is often desirable to ensure good vias in the This can be accommodated with slight method changes as described with reference to FIGS.

Referring now to FIG. 5, a thin layer 58 of conductive material is conformally deposited over the structure. . Layer 58 forms a diffusion barrier between layer 48.50 and the later deposited refractory metal. from the first layer of titanium (T1) and the second layer of titanium nitride (TiN). It is preferable to include a two-layer structure. Layer 58 may be formed, for example, by first applying titanium to the device. sputtered conformally onto the top to a thickness of approximately 500 angstroms and then titanium nitride. by depositing conformally onto the titanium to a thickness of approximately 500 angstroms. It can be formed by

Referring now to FIG. 6, a refractory metal, preferably chemical vapor grown tungsten ( Deposit a layer of W) on top of the structure surface to fill vias 52, 54, 56 and leave gaps. forming a generally conformal layer 60 that does not According to an important feature of the invention, the tan The gsten layer 60 is formed by chemical vapor deposition (CVD) at a temperature in the range of approximately 300 to 420°C. at ambient temperatures and pressures in the range of about 5 to 50 torr. This CVD method is A ungsten source gas such as WF6+SiH4+H2 can be used. Ru. Within these temperature and pressure ranges, the via aspect ratio is approximately 1:4. Tungsten layer 60 uniformly fills vias 52, 54, 56, even if always large. And it can be filled without any gaps.

At this point, during the formation of layers 58 and 60, the inorganic layer 50 is exposed to the deteriorating effects of the metal forming process. and corrosion effects, especially the corrosion effects of the gas used in the CVD tungsten method. Note that it serves to protect the reimide layer 46. Layer 58 is tungs Improves the adhesion of the tensile layer 6o to the device and improves the adhesion of the tensile layer 6o to the underlying device area. It works to reduce the contact resistance of gsten.

Referring now to FIG. 7, layer 60 is removed using conventional chemical mechanical polishing techniques. Polish down to the edge layer 50 and remove the source region 26, gate contact 32, and drain region, respectively. Discrete metal stud contacts 60A, 60B, 60C to 28 remain.

FIG. 7A shows that layers 50 and 46 have been removed by etching and silicon dioxide ( An alternative embodiment of the present invention is shown in which the insulation material 63 (i.e. quartz) is replaced. layer 46 and 50 are reactive ion etchants using e.g. CF, 102 plasma. It can be removed by the RIE method. Layer 63 is formed by conventional chemical vapor phase oxide growth. (CVD) method and then printed using conventional chemical mechanical polishing methods. It can be layered to yield the structure shown in FIG. 7A. process saw Which embodiment of the invention (i.e., the embodiment of FIG. 7 or FIG. 7A) of the present invention is used at the stage of The remaining process steps below are to be performed in the same manner regardless of the I want to be recognized.

Referring now to FIG. 8, a thin layer 64 of conductive material is conformally deposited over the device. etch step of the later deposited thicker layer 66 of conformally deposited conductive material. Use as a top. Layers 64 and 66 may have different etching properties. is necessary. For example, layer 64 was sputter deposited to a thickness of approximately 0.1 microns. Layer 66 is made of copper and is made of sputter deposited aluminum to a thickness of approximately 0.5 microns. Spun to a thickness of approximately 0.5 microns, covered with a second layer of Umu copper alloy (AICu). The structure consists of a multi-stage structure including a first layer of titanium (T1) deposited on the substrate.

Continuing with the structure of FIG. 8 after the deposition of layers 64 and 66, conventional photolithography using an anisotropic etching agent to mask both layers (not shown). The surface of the buried bi 760B, which is generally above the FET gate contact 32 and An opening 68 is formed exposing an adjacent portion of layer 50. The opening 68 is made of, for example, BCl. 3. Etch down to the etch stop layer 64 using C1□, CC14 RIE plasma. layer 64 and removing the exposed portions of layer 64 using an HF dip. Wear. After forming openings 68 in layers 64, 66 in this manner, metal-filled vias are formed. Discrete metal lines/interconnects/wires to 60A, 60C, i.e. studs 60 Interconnect 64A/66A to A and Interconnect 64B/66B to Via 60C Form.

Instead of the process shown in FIG. 8 and described above, the metal wire 6 is 4A/66A, 64B/66B can also be formed.

Referring now to FIG. 9, the above steps for forming a planarized layer of polyimide. and polyimide insulation by repeating the above steps to form metal-filled vias. 72 and metal filled vias/studs 74, 76, 78. form 70. Via 76 extends through insulation 72 to connect interconnect 66A. thus contacting the FET gate contact 32) and extending vias 74 and 76 as well. interconnects 66, A (and thus FET source region 26) and 66B (and thus making contact with the FET drain region 28).

The above steps of the invention can be extended to provide further layers of metallization. It will be understood that it can be done. Using the advantage of non-invention, metallization up to at least 4 stages ization can be formed on a device such as FET 20 on substrate 22. and each stage supports metal-filled vias (i.e. vias 52, 54, 56); 1 of polyimide insulation covering the metal interconnects (i.e. interconnects 66A, 66B) It is theorized that one layer (ie, layer 46) is defined.

Referring now to Figures 10-12, the vias can be overetched and etched. It is necessary or desirable to undercut the tucking mask, Significant advantages of the invention are shown. 8 This kind of situation can be met, for example, in a different way. When it is necessary to etch a via with a certain aspect ratio.

FIG. 10 shows the overlying silicon nitride layer 82, polyimide layer 84, and silicon nitride layer. A silicon substrate 80 is shown supporting 86. (This is shown in Figure 3 above. It will be understood that the structure is almost the same as that of the insulator structure described above. ) In the figure, the opening 88 extends from the surface of layer 86 and contacts layer 82, and opening 88 includes a masking nitride layer. 02 plasma to form an undercut 90 under the silicon layer 86. - bar etched. Conventional photolithography mask over layer 86 is self-explanatory and not shown.

According to this aspect of the invention, using e.g. CF, RIE plasma etching agents, The silicon nitride layer 86 is then removed simultaneously with the exposed portion of layer 82 in the opening 88. . Referring to FIG. 11, the barrier metal layer 92 and Plunkett layer 92 are removed as described above. A tungsten adhesion layer 94 is formed.

Referring to FIG. 12, tungsten layer 94 is chemically mechanically deposited to the top surface of layer 84. Polishing results in filled vias 94A. Then the desired inorganic layer, e.g. Then, a layer of silicon nitride 96 is redeposited and further processing continues in accordance with the present invention.

In this way, the present invention does not require much change in the process and does not have much complexity in the process. Can deal with via overetching.

Thus, new and improved forming metal interconnects for semiconductor devices A method is provided. Lined with an inorganic protective coating and diffusion barrier and filled with refractory metal. Using polyimide insulation with calibrated vias or studs, the The interconnect structure provides the following significant advantages over prior art structures.

− Low dielectric insulation materials can be used - Can be etched without damaging the underlying structure - Various underlying step heights A reliable electrical connection can be made to a feature structure that varies from - Virtually eliminates contamination of device substrates by mobile ions - The present invention allows the use of different dielectric materials depending on the needs, such as bipolar, FET, Particularly applicable to the manufacture of semiconductor devices such as bipolar FET devices, with high density Very large scale integrated circuits (VLSI) require multiple stages of interconnection to connect multiple devices. ) is particularly useful for

Although the invention has been shown and described with respect to particular embodiments thereof, it is not intended to be so limited. It's not. Numerous modifications, changes, and improvements are contemplated that fall within the spirit and scope of the invention. It will come.

four FIC,3 FIG. 7A Semiconductor interconnect structure using polyimide insulators for substrates where conductive contacts are desired. A semiconductor structure is provided that includes a substrate of semiconductor material that includes a device region on a surface.

A planarized polyimide layer is placed on top of the surface of the substrate, and the polyimide layer is A layer of inorganic material is disposed on. The opening exposing the device area is located in the polyimide layer. gold is formed on top of the surface of the opening in the polyimide layer to provide a diffusion barrier. A lining is formed. The resistant A layer of fire metal fills the lined openings in the polyimide layer.

Inspection report

Claims (34)

[Claims] 1. A substrate of semiconductor material, including the device area on the surface of the substrate where you want to provide conductive contacts a stage of preparing forming a polyimide layer on the surface of the substrate; forming an exposed opening in the polyimide layer; forming a metal lining over the surface of the opening in the polyimide layer; on top of the substrate so as to approximately fill the lined opening in the polyimide layer above. conformally depositing a layer of refractory metal; and planarizing the refractory metal layer to the device region. How to form points. 2. Additionally, prior to the step of forming the openings, on the surface of the polyimide, 2. The method of claim 1, including the step of forming a layer of inorganic material. 3. Further, the polyimide layer is planarized prior to the step of forming the openings. 2. The method of claim 1, including the step of converting. 4. The step of planarizing the polyimide layer includes chemically planarizing the polyimide layer. 4. The method of claim 3, including the step of mechanically polishing. 5. The step of planarizing the polyimide layer comprises converting the polyimide layer into an organic polymer. coating with reamer and etching the organic polymer and polyimide layer the stage of 4. The method of claim 3, comprising: 6. The step of planarizing the refractory metal layer comprises chemically mechanically 2. The method of claim 1, including the step of polishing. 7. The metal lining includes a first layer of titanium (Ti) and a titanium nitride alloy (TiN). 2. The method of claim 1, comprising a second layer of ). 8. The method of claim 1, wherein the refractory metal comprises tungsten (W). 9. The above tungsten (W) is 9. The method of claim 8, wherein the method is deposited by chemical vapor deposition at a pressure in the range of 100 ml. 10. Additionally, multi-stage polyimide with metal-filled vias can be formed to 2. The method of claim 1, including the step of providing electrical interconnections of the stages. 11. Semiconductor material, including the device area on the surface of said substrate where it is desired to provide conductive contacts forming a polyimide layer on the surface of the substrate; and forming a polyimide layer on the surface of the substrate. a step of planarizing the surface of the polyimide layer; and a step of planarizing the surface of the polyimide layer. forming a layer of inorganic material thereon; and etching the inorganic material layer and the polyimide layer. etching the polyimide to form an opening exposing the device area; forming a metal lining over the surface of the opening in the midlayer; Place a resistive layer on top of the substrate so as to substantially fill the lined opening in the polyimide layer. conformally depositing a layer of refractory metal; planarizing the refractory metal layer; The refractory metal is removed from the surface of the polyimide layer, and the refractory metal is removed from the surface of the polyimide layer. The stage of leaving the genus A method of forming a conductive contact to the device region. 12. The inorganic material layer is made of silicon dioxide, silicon nitride, or glass. 12. The method of claim 11. 13. The step of planarizing the polyimide layer comprises converting the polyimide layer into an organic material. coating with a polymer and etching the organic polymer and the polyimide layer; the stages of 12. The method of claim 11, comprising: 14. The step of planarizing the polyimide layer includes chemically 12. The method of claim 11, including the step of mechanically polishing. 15. The metal lining above is a titanium (Ti) layer on the polyimide and a titanium nitride alloy on the titanium layer (TiN) layer. 16. 12. The method of claim 11, wherein the refractory metal comprises tungsten (W). 17. The step of forming the tungsten layer is performed at a temperature in the range of 300 to 420°C. The above tungsten is grown by chemical vapor deposition at a pressure in the range of 5 to 50 Torr. 17. The method of claim 16, including the step of depositing. 18. The step of planarizing the refractory metal layer comprises converting the refractory metal into a chemical mechanical 17. The method of claim 16, including the step of selectively polishing. 19. Furthermore, a conductive material layer is formed on the surface of the polyimide layer to 12. The aspect of claim 11, comprising the step of providing at least one electrically conductive wire to the tad. Law. 20. forming a metal lining on the surface of the via; conformally forming the metal layer on the surface of the polyimide; and removing the metal layer except in the via. 21. Additionally, multi-stage polyimide with metal-filled vias can be formed to 12. The method of claim 11, including the step of providing electrical interconnections of the stages. 22. Semiconductor material, including the device area on the surface of said substrate where it is desired to provide conductive contacts material substrate, a polyimide layer on the surface of the substrate and a top layer exposing the device area; an opening in the polyimide layer; Form a conductive contact to the device area with a metal lining over the surface of the opening above. a refractory metal stud filling an opening lined to Body structure. 23. Further, an inorganic material layer is provided on the surface of the polyimide outside the opening. 23. The structure of claim 22. 24. The metal lining above is a titanium layer on the polyimide; and a titanium nitride (TiN) layer over the titanium layer. 25. 23. The structure of claim 22, wherein the refractory metal comprises tungsten (W). 26. In addition, it includes metal-filled vias to provide multiple levels of electrical interconnection. 23. The structure of claim 22, comprising at least one additional stage of polyimide. 27. Further, providing at least one electrically conductive wire to the stud; 23. The structure of claim 22, including a region of electrically conductive material on a surface of the polyimide layer. 28. Semiconductor material, including the device area on the surface of said substrate where it is desired to provide conductive contacts material substrate, a planarized polyimide layer on the surface of the substrate; a layer of inorganic material on top of the polyimide layer and exposing the device area; an opening formed in the polyimide layer; provided on the surface of the opening in the polyimide layer to form a diffusion barrier. a refractory metal lining and a refractory metal lining filling the lined openings in the polyimide layer. layer of genus and forming a conductive contact to the device region by the refractory metal layer comprising: , semiconductor structures. 29. The inorganic material layer on the polyimide layer is made of silicon dioxide or silicon nitride. 29. The structure of claim 28, wherein the structure is selected from glass or glass. 30. The metal lining above is A layer of titanium (Ti) on the polyimide, and a layer of titanium (Ti) on the titanium layer. 29. The structure of claim 28, comprising a layer of TiN). 31. 29. The structure of claim 28, wherein the refractory metal comprises tungsten (W). 32. Further, providing at least one electrically conductive wire to the stud; 29. The structure of claim 28, including a region of electrically conductive material on a surface of the polyimide layer. 33. Furthermore, an inorganic material is provided between the polyimide and the surface of the semiconductor substrate. 27. The structure of claim 26, comprising a layer of material. 34. Additionally, the surface of the polyimide layer is at least one additional polyimide layer having metal-filled vias thereon; , the structure of claim 28.