TW521402B - Method for reducing random bit failures of flash memories - Google Patents

Abstract

A method for reducing random bit failures of flash memory fabrication processes with an ISSG film is disclosed. The random bit failures are caused by HF acid penetration. The ISSG film, which functions as a interface reinforcement layer, is formed on a sacrificial layer and a PL1 layer. With the aid of the ISSG film, the flash memory is free of acid-corroded seams.

Description

521402 V. Description of the invention (l)-Field of invention The present invention provides a flash memory with high gate coupling rati (GCR) and high reliability (re 1 iabi 1 ity). Method 'especially a method using an ISSG (in-situ steam growth) film to simultaneously reduce the random bit failure generated during the production of flash memory and improve the reliability of the flash memory.

Background note

In recent years, as the demand for portable electronic products has increased, the technology of flash memory (f 1 ash) and its market applications have also matured and expanded. These portable electronic products include digital camera negatives, mobile phones, video game apparatus, personal digital assistant (PDA) memory, telephone answering devices, and programmable ICs. Flash memory is a type of non-volatile memory (non_volatile memory). Its operating principle is to change the threshold voltage of the transistor or the memory unit to control the switching of the gate channel to achieve the purpose of storing data. The data stored in the memory will not be lost due to power interruption. Generally, the gate structure of flash memory is designed into two types, one is a stacked gate, and the other is a split gate.

Page 4 521402 V. Description of the invention (2) 'pole (spl i t-gate). The stacked gate flash memory mainly includes a floating gate for storing charge and a control gate (c ο ntr ο 1 gate) for controlling data access. It is isolated from the gate by a dielectric layer of a 0N0 (oxide-nitride-oxide) structure. Therefore, the memory can use the principle of a similar capacitor to store the low-quality charge in the stacked gate, so that the memory stores the signal " 1. " If " needs to replace the data in the memory, just provide a little extra Energy, erase the electrons stored in the floating gate, and then write the data again. 0 Please refer to Figures 1 to 4, Figures 1 to 4 make a double-bit (dua 1 bit) stacking method Schematic diagram of the method of gate flash memory. First, as shown in FIG. 1, the semiconductor wafer 10 includes a silicon substrate 12, and an active area 11 is isolated by a field oxide layer 14. The silicon substrate 12 and the two gate structures 21 are provided in the active region 11. The gate structure 21 has a gate oxide layer 16 on the surface of the silicon substrate 12 and a polycrystalline silicon layer or a PL 1 layer 18 is provided on the gate oxide layer 16 and a silicon nitride layer 20 is provided on the PL 1 layer 18. As shown in FIG. 2, an ion implantation process is performed outside the gate structure 21. The silicon substrate 12 is doped with ions on the surface, and then an oxidation process is performed to make the doping ion free. Activated and diffused to form an ion diffusion layer 22, which is used as a buried drain and source (BD / BS) for flash memory. At the same time, a heat is formed on the ion diffusion layer 22 Oxide layer

Page 5 521402 V. Description of the invention (3) ~ 'is the BD / BS oxide layer 24. As shown in FIG. 3, the silicon-nitrogen layer 20 is then completely removed, and a polycrystalline silicon layer 26 is formed on the silicon layer 18 on the surface of the semiconductor wafer 10. The PL1 layer 18 and the polycrystalline silicon layer 26 covering it form a floating gate 28. Subsequently, as shown in FIG. 4, a dielectric layer 30 consisting of an oxide-nitride-oxide structure is formed on the surface of each floating gate, and a f, a first oxide layer (not shown) (Shown), a nitride layer (not shown) is provided on the first oxide layer, and a second oxide layer (not shown) is provided on the nitride layer. : Then, a polycrystalline silicon layer 32 is formed on the surface of the semiconductor wafer 10 to cover the surfaces of the electrical layer 30 and the thermal oxidation layer 24. The polycrystalline silicon layer 32 is used as the control gate of the non-volatile memory. As the conventional manufacturing method uses a high-temperature thermal oxidation process to form a thermal oxidation layer 24 on the surface of the silicon substrate i2, the thickness of the thermal oxidation shoulder 24 becomes uneven, and the surface of the silicon substrate 12 is damaged. The crystal lattice structure is obviously ^ two-decided, and the reliability of the body has been improved. In addition, the oxidizing process used to form the thermal oxide layer 24 will excessively penetrate into the ions doped in the drain and source, thereby shortening the channel length of the floating gate 28 relatively, and even causing the drain and source. The inter-pole peak T # /, and the second king's abnormal electrical punch (punch thought), or lead to short, Tao: the effect is worsened. In addition, the memory junction formed by the conventional method 4 ». -J / r ju,. The problem of insufficient gate coupling ratio (GCR).

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SUMMARY OF THE INVENTION It is to provide a high GCR stacking method with an ISSG film, which can therefore have the main purpose of the present invention: the gate non-volatile memory manufacturing method improves the reliability of the memory. The other purpose of Fayue is to provide a flash memory manufacturing method that can not only avoid the problem of uneven bd / bs oxide layer thickness caused by the two-temperature heating process, but also accurately control each of the semiconductor wafers formed on the semiconductor wafer. The channel length of the stacked gate and the thickness of the BD / BS oxide layer effectively reduce the size of each component and increase the reliability of these components. In another aspect of the present invention, an ISSG film is used to effectively prevent the phenomenon of acid penetration during the process of making flash memory, which can reduce random bit failure caused by etching. The method of the present invention includes the following main steps according to a preferred embodiment of the method of the present invention: (1) providing a substrate including a channel region and a bit line region; (2) forming a channel region on the substrate A stacked layer, wherein the stacked layer includes a polycrystalline silicon layer and a sacrificial layer is formed directly on the polycrystalline silicon layer; and (3) oxidizes the plutonium layer and the substrate in the bit line region to simultaneously A polycrystalline silicon layer and an ISSW are formed on the surface of the sacrificial layer;

521402 V. Description of the invention (5) '(4) A dielectric layer is deposited on the ISSG film to cover the channel region and the bit line region, wherein the thickness of the dielectric layer on the bit line region is greater than that The thickness of the polycrystalline layer is smaller than the thickness of the stacked layer; (5) the dielectric layer and the I SSG film are partially removed to expose a part of the sacrificial layer; and (6) the sacrificial layer is completely removed. The method of the invention can obviously increase the capacitance area between the subsequently formed control gate and the floating gate, so that the GCR is increased by about 60 to 70%, thereby improving the electrical performance of the memory and reducing the flash memory. Energy dissipation of the body. The ISSG film can strengthen and protect the interface between the dielectric layer and the polycrystalline silicon layer, and avoid the interface between the dielectric layer and the polycrystalline silicon layer from being soaked and washed in the acid solution or during the wet etching of the dielectric layer. Acid-corroded seam phenomenon. In addition, the ISSG technology used to form the ISSG film does not cause a significant change in the doping profile of the BD / BS, so it can maintain the electrical stability of the memory element and a high degree of accumulation. Detailed description of the invention Please refer to FIG. 5 to FIG. 11, which are schematic cross-sectional views of manufacturing a high gate coupling rate (GCR) flash memory cell in a preferred embodiment of the method of the present invention. In order to facilitate the description of the present invention, Fig. 5 to Fig. 11 show only a part of the flash memory area related to the method of the present invention. Method of the invention

Page 8 521402 V. Description of the Invention (6) * In the preferred embodiment, a two-bit flash memory unit is taken as an example. First, as shown in FIG. 5, the semiconductor wafer 100 includes a silicon substrate 120, and an active area n0 isolated by a shallow trench isolation (STI) region 140 is provided on the Shixi substrate 12. And the two gate structures 210 are disposed in the active region 110. The gate structure 2 1 0 has a gate oxide layer or a tunneling oxide layer 1 60 provided on the surface of the silicon substrate i 2. A polycrystalline silicon layer or a PL 1 layer 1 80 is provided on the tunneling oxide layer 1 60 Above 'and a sacrificial layer 2000 are disposed above the PL1 layer 180. As shown in FIG. 5, the gate structure 2 10 further divides the active area 110 into a channel area i 3 and a bit line area Π 5. In a preferred embodiment of the present invention, the silicon substrate 12 is a p-type doped single crystal silicon substrate having a < 1 0 0> lattice arrangement direction. However, the present invention is not limited to this. The silicon substrate 12 may also be a silicon-on-insulator (SOI) substrate, an epitaxy silicon substrate, or a dream having different lattice arrangement directions. Substrate. In this preferred embodiment, the thickness of the 'tunneling oxide layer 160 is about 90 to 120 angstroms (angstrom, A), preferably 95 angstroms. The thickness of the PL1 layer 180 is about 100 Angstroms. The thickness of the sacrificial layer 2000 is about 1800-1950 angstroms, and preferably 1925 angstroms. The sacrificial layer 200 uses a chemical vapor deposition (^ 0) process, and uses two gas silanes (3) ^ 2 (: 12) and ammonia (1 ^ 3) as the reaction gases at 7 5 0 It is formed at ° C. The P L1 layer 1 80 is deposited at 620 ° C by using Shi Xiu (si si 4) as a reaction gas. The critical dimension of the PL 1 layer 1 80 after etching (after- etch-inspect critical dimension

Page 9 V. Description of the invention (7) AEICD) 'The length of the floating gate channel is about 0.3 dm. As shown in FIG. 6, an arsenic ion implantation process 212 is performed next to the surface of the silicon substrate 1 2 0 other than the gate structure 2 10, that is, the bit line region 丨 5, to be doped with a god ion to form a dopant. The miscellaneous region 2 2 0 is used as a burial of flash memory; and a buried drain and source (BD / BS) or bit line. In a preferred embodiment of the present invention, the arsenic ion implantation process 212 uses an energy of 501 ^ ¥ and a dose of about 1 £ 15 (; 111-depleted arsenic ions for ion implantation. Subsequently, a rapid heat treatment (rapid thermal processing (RTP) to activate the arsenic ions implanted on the surface of the silicon substrate 120. As shown in Figure 7, an oxidation process containing oxygen radicals and hydroxide radicals is performed to sacrifice the silicon nitride at the same time. The layer 200 surface, the pu layer 180 surface, and the silicon substrate 12 surface are oxidized to form an ISSG (in — situ

steam generation or in-situ steam growth) film 23 0. The thickness of the ISSG film 230 is between 80 and 300 angstroms, preferably between 100 and 150 angstroms. Subsequently, a high-density plasma chemical vapor deposition (HDPC VD) process is performed to deposit a jjDp oxide layer having a thickness of about 2000 to 3000 Angstroms 2 4 0, covering the Is G film 2 3 0. Among them, the DP oxide layer 2 4 0 covers the channel region 11 3 and the bit line region 115, and the thickness of the HDP vaporization layer 2 4 0 on the bit line region 1 5 is greater than that of the polycrystalline stone layer 1 § 〇, but less than the thickness of the stacked gate 210. 521402 V. Description of the invention (8) • The so-called ISSG film 230 is formed by a technique called in-situ steam growth (ISSG). In-situ steam growth (I SSG) technology is a low-pressure wet rapid thermal oxidation method with high reproducibility. In-situ steam growth (ISSG) technology can be performed in a single-wafer RTp reactor. For example, Applied Materials Co., Ltd.'s? £? 11818101: 1 ^ E type, which is configured with 15 to 25 tungsten tungsten halogen lamps arranged in parallel to quickly heat the wafer to the required high temperature. In a preferred embodiment of the present invention, ISSW 23 is formed in a XEplus Centura (R) type RTP reactor with a total gas f low rate (TGF) of about 10 SLM of hydrogen and oxygen. The hydrogen flow rate (% H2 of TGF) is 2%, and the pressure of the RTP reactor should be controlled below 20 Torr, preferably 10.5 T〇rr. During the reaction, the Shixi substrate 120 was rapidly heated to 100 0 C to 12 0 ° C, preferably 1 150 ° C by a tungsten tungsten halogen lamp, and maintained at this temperature of about 2 0 to 25 seconds. Because the reaction pressure is controlled at a low m pressure & below 20 Torr, this I SSG high temperature rapid oxidation reaction is performed under a mass transport controlled regime, and the change in pressure will directly affect the oxidation Mass transport rate during the process. Due to the short heating time of the ISSG technology, the profile of the concentration distribution of the doped region 220 will not be affected.

521402 V. Description of the invention (9) As shown in Figure 8, a wet lasting process is performed, using a diluted hydrofluoric acid (diluted HF, DHF) or a buffered oxygen silicon etchant (buffere (j oxide etcher, Β0Ε)). A part of the HDP oxide layer 240 and a part of the I SSG layer 2 3 0 are engraved to expose a part of the sacrificial layer 2 0. In the preferred embodiment of the present invention, the HDP oxide layer 2 is etched away. The thickness of 40 is about 650 to 900 angstroms, preferably about 700 angstroms. At this time, the η DP oxide layer 240 after the acid etching is divided into two parts that are not connected. One part 24 & is located directly above the sacrificial layer 2000, and the second part 24Ob is located on the side of the gate 210. The ISSG layer 2 3 0 strengthens the HDP oxide layer 240 and the PL1 layer 180. This can effectively prevent the penetration of the acid solution (ie, DHF) used to etch the HDp oxide layer 240, thereby avoiding the phenomenon of acid-corroded seam. Then, as shown in Figure 9, A hot phosphoric acid solution heated to about 16 was used to completely remove the sacrificial layer 200 above the PL1 layer 180. The same as removing the sacrificial layer 2, 00 The first part 2 j0a of the HDp oxide layer located directly above the sacrificial layer 200 is also removed. After the sacrificial layer 200 is removed, the second part 240b of the original oxide layer 240 is located at A protruding structure 2 52 is formed near the PL1 layer 180. This special protruding structure 252 can increase the gate coupling ratio (about 60 to 75 ° /.). As shown in Fig. 10, and then at? 11 A polysilicon layer 260 is formed on the layer 18o, and the polycrystalline silicon layer 26o is electrically contacted with the pl 1 layer 180 ′ to be used as a floating gate 28. Finally, as shown in FIG. Shaped on the surface of floating gate 28

Page 12 521402 V. Description of the invention (10)-Forming a dielectric layer 290. The dielectric layer 290 is an ONO structure composed of a bottom oxide layer (not shown), a nitride layer (not shown), and an upper oxide layer (not shown). Then, a polycrystalline silicon layer 300 is formed on the surface of the semiconductor wafer 1000 to serve as a control gate. The floating gate, the dielectric layer of the ON0 structure and the control gate form a stacked gate of a non-volatile memory. Since the fabrication of the ON0 dielectric layer 290 and the control gate is well known to those skilled in the art, detailed steps will not be repeated. The method for making a flash memory according to the present invention can be applied to a process of non-volatile memory (non-volatile memory), and can also be used to make an embedded flash memory (embedded f 1 ash) and dynamic random storage. Take the storage node of the capacitor element of the dynamic random access memory (DR AM). Compared with the conventional method for making flash memory, the method of the present invention is significantly improved. The technical features are: (1) The HDP oxide layer 240b deposited around the PL1 layer 180 is used as the BD / BS oxide layer, so there is no need to use Thermal oxidation process. Therefore, by using the thickness of the BD / BS made by the method of the present invention, an effective control can be obtained by the HDP CVD method, so that each of the stacked gates fabricated on the semiconductor wafer 1000 can flash rapidly. The electrical properties of the memory cells are approximately equal; (2) The present invention uses a wet etching method to etch the HDP oxide layer 240 'and then remove the sacrificial layer 200, so that a protruding structure 25 2 can be obtained, which can greatly increase the GCR; (3) The present invention uses the iSSG technology to form an ISSG film 230 ′. Therefore, the HDP oxide layer 240 can be directly wet-etched. This is caused by

Page 13 521402 V. Description of the invention (π)-The interface between HDP oxide layer 2 40 and pl 1 layer 180 is strengthened in ISSG layer 2 3 0, so it can effectively prevent the etching of HDP oxide layer 240. Acid (ie, DHF), thereby avoiding the phenomenon of acid-corroded seam. The above description is only a preferred embodiment of the present invention, and any equivalent changes and modifications made in accordance with the present invention application and patent scope should fall within the scope of the patent of the present invention. ^

Page 521 402 Simple illustrations Simple illustrations Figures 1 to 4 are schematic diagrams of a conventional method for making a stacked gate flash memory; and Figures 5 to 11 are the preferred embodiments of the method of the present invention A cross-sectional schematic diagram of a high-gate coupling rate flash memory cell is fabricated. Explanation of Symbols 10 Semiconductor wafer 11 Active area 12 Silicon substrate 14 Field oxide layer 16 Gate oxide layer 18 PL1 layer 20 Silicon nitride layer 21 Gate structure 22 Ion diffusion layer 24 BD / BS oxide layer 26 Polycrystalline silicon layer 28 Float Gate 30 Dielectric layer 32 Polycrystalline silicon layer 100 Semiconductor wafer 110 Active area 113 Channel area 115 Bit line area 120 Shi Xi substrate 160 Tunneling oxide layer 180 PL1 layer 200 Sacrificial layer 210 Gate structure 212 Arsenic ion implantation process 220 buried drain and source 230 ISSG film 240 HDP oxide layer 240a first part 240b second part 252 protrusion structure

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Claims (1)

521402 6. Scope of Patent Application 1. A method for reducing random bit failure of flash memory (randc) m blt f ai lure), the method includes the following steps: providing a substrate, and the surface of the substrate includes a channel area And a bit line region; forming a stacked layer on the channel region of the substrate; the stacked layer including a polycrystalline silicon layer and a sacrificial layer formed directly above the polycrystalline silicon layer; oxidizing the stacked layer and the bit on the polycrystalline silicon Layer and the sacrificial layer are deposited on the ISSG film-dielectric potential line region 'where the bit line region has the thickness of the polycrystalline fragment layer' but smaller than the portion except the dielectric layer and the carrier layer; and the line region The inner layer is formed on the same surface with an / ISSGm; layer covering the channel region and the thickness of the dielectric layer on the domain is greater than the thickness of the stack layer. The ISSG film is exposed to expose part of the sacrifice and completely remove the sacrifice. -The ISSG film can strengthen and protect the interface between the dielectric layer and the polycrystalline silicon layer, and avoid the interface between the dielectric layer and the polycrystalline silicon layer from being soaked in the acid solution. An acid-corroded seam phenomenon occurs during the washing process. 0 2 · As in the method of the first patent application, the I SSG film system uses an in-sitll steam growth (ISSG) technology. Form 0 Page 17 521402 VI. Application scope of patents_3. The method of applying for item 1 of the patent scope, wherein the dielectric layer is a high density plasma oxide (HDP oxide) layer. The method of item 1 of the patent, wherein the surface of the substrate further comprises a doped region in the substrate of the bit line region, and is used as a buried source / buried drain (BS / BD). ). 5. The method of claim 1, wherein the sacrificial layer is composed of silicon nitride. 6 · If the application layer and the DHF) or b0e). The method of claim 1 in the patent application for electric HF, in which the method for partially removing the ISSG film is to use a diluted hydrofluoric acid (buffered oxide etcher). Item, wherein the method of removing the sacrificial layer is a hot phosphoric acid solution. • The method of item 1 in the scope of the patent application, wherein the acid solution is immersed and cleaned, which includes a diluted HF (DHF). ) Solution 9 • The method according to item 1 of the scope of patent application, wherein the substrate is a Shixi substrate. 521402 Page 19