^1273 A7 ?? 經濟部智慧財產局員工消費合作社印製 -----— B7 _ 發明說明（产） (一） 發明技術領域： ▲本發明係為-種記憶體腳位切割之改良方法，特別是對 在兄憶體模財有若干個有部分微損壞之記憶體，在做電路 佈線設計時所實施之_、合併與_之方法。 (二） 發明技術背景·· 目月ίι使用於電腦上之動態隨機存取記憶體(DRAM)，依 其記憶體雕以及記龍触之設⑽可大致分為SDR DRAM' SGRAM、DDR DRAM 等數種。其中，SDR DRAM 是使用同步動態隨機存取記憶體(办加1^〇11〇此1)_)，所謂 同步（Synchronous)是指記憶體的時脈(d〇ck)能與cpu的時 脈能夠同時存取龍，因此可節省執行齡及倾傳輸的時 間。一般俗稱的PC-100、PC-133即是指CPU的外頻與記憶 體的存取頻率相同，且頻率可達1〇〇MHz或是i33MHz，而 由於該種記憶體模組之資料係可在每個時脈週期存取一次， 故稱為單倍速f料傳輸SDR(Single Data恤⑽記憶體模 組’這種使用SDR _己憶體模組通常設計有168_，且使 用3.3V之電壓，並透過一個168 pms的dmm⑽藏 In-Line Memory Module)插槽接至主機板。另外，ddr dram仍是使用動態隨機存取記憶體的顆粒，但對資料之存 取為使用一種雙倍速資料傳輸(D_e Data Rate ; 術。ddr的記憶體模組_使簡續機存取記憶體不過其 腳位通常設計為184 pins ’其特色是_職取的技術在_； 個時脈週期中可傳送兩次資料組，即是在該時脈之正緣與負 -----------— III— · 11 (請先閱讀-f面之it意事項再本頁) 訂. -丨線· 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公f ) 521273 五 ____ 經濟部智慧財產局員工消費合作社印製 A7 B7 發明說明（/) 緣各傳送一次，有別於SDR在一個時脈週期只能傳送一次， 故DDR的存取速度為SDR的兩倍，並且SDR之記憶模組通 常使用3.3V電壓，而DDR係通常使用3 3v或2.5乂的電壓。 而目珂常見記憶體顆粒之記憶容量種類非常繁多，例如有4^ 1273 A7 ?? Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ------- B7 _ Description of the Invention (Production) (I) Technical Field of the Invention: ▲ The present invention is an improved method for cutting the foot position of a memory In particular, the _, merge and _ methods implemented in the circuit wiring design of several memory devices that are partially damaged in the brother memory phantom. (II) Technical background of the invention ... The dynamic random access memory (DRAM) used in the computer can be roughly divided into SDR DRAM 'SGRAM, DDR DRAM, etc. according to its memory carving and the design of remembering the touch of the dragon. Several. Among them, the SDR DRAM uses synchronous dynamic random access memory (to add 1 ^ 〇11〇1) _), the so-called (Synchronous) means that the clock of the memory (doc) can be compared with the clock of the cpu The ability to access dragons at the same time saves execution time and transfer time. Generally known as PC-100, PC-133 means that the CPU's FSB and the memory access frequency are the same, and the frequency can reach 100MHz or i33MHz, and because the data of this memory module is available It is accessed once in each clock cycle, so it is called single-speed f-material transmission SDR (Single Data shirt memory module 'This type of SDR _ Ji Yi body module is usually designed with 168_, and uses a voltage of 3.3V , And connected to the motherboard through a 168 pm dmm hidden In-Line Memory Module) slot. In addition, ddr dram is still a particle that uses dynamic random access memory, but the data is accessed using a double-speed data transfer (D_e Data Rate; technology. Ddr memory module _ makes the simple machine access memory However, its foot position is usually designed as 184 pins. Its characteristic is _ professional technology in _; the data group can be transmitted twice in the clock cycle, that is, the positive edge and negative of the clock ----- ------— III— · 11 (Please read the notices on the -f side and then this page).-丨 Line · This paper size applies to China National Standard (CNS) A4 (210 X 297) f) 521273 Five____ Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 Invention description (/) The edge is transmitted once, which is different from SDR which can only be transmitted once in a clock cycle, so the DDR access speed is SDR The memory module of SDR usually uses 3.3V voltage, and DDR series usually uses voltage of 3 3v or 2.5 乂. And the memory capacity of Moike's common memory particles is very diverse, such as 4
Mbytes ’ 8Mbytes ’ 16Mbytes ’ 32Mbytes 等等，並配合不 同之圮憶體模組之設計而有不同設計規格與容量的記憶體顆 粒。 而不論是SDR或DDR或者是其他類型之記憶體顆粒， 在製造生產時都會面臨一些問題。即雖然製造記憶體顆粒之 過程係為製程繁複且各項條件均嚴格之半導體製程，其良率 之提升也是各半導體製造廠所努力的目標，不過在此情況下 §己憶體顆粒在製程上仍然會有不良品的出現，在這些有瑕疵 的記憶體顆粒中，除了少部分因損壞嚴重而完全不能使用 外，其他的則屬小區域之損壞，而在使用上仍然可對這些有 小區域損壞之記憶體顆粒予以利用與設計。 在實際之设計上，多半是對該記憶體顆粒做邏輯上之區 分或疋對該記憶體模組之腳位予以設計，以達到對該記憶體 顆粒之再利用以達成資源有效再利用之目的。在對記憶體模 組腳位之設計中，一般而言，是在有瑕疵之記憶體中予以篩 選出可用的記憶體，並集合可相容設計之若干個記憶體於記 憶體模組中，針對其可用的資料輸出/入腳位(DQPIN)予以適 當組合’以將若干個記憶體製成於一記憶體模組中。 而在現行所使用之對記憶體腳位之切割設計中需對同一 規格之記憶體製作不同佈線組合之模組佈線設計，方能涵蓋 經濟部智慧財產局員工消費合作社印制衣 521273 A7 一 — —_ — 一 — B/ 五、發明說明（j ) 該規格之記憶體在各資料輪出/入腳位產生暇疲時之各種情 況下之所做之輯’方能完全的细觀憶體可制各種腳 位切割方式。 請參閱圖- A，係為習用技術對一含有4支資料輸出/ 入腳位之記鍾所狀設定，射_纖體之触/入腳位 DQO〜DQ3分為四部分，分別是Dq〇為A、卿為B、卿 為C、DQ3 $ D，則在對記憶體模組之佈線設計時對記情體 輸出/入腳位DQPIN作選擇，則有六種變化分別是（A，⑴、 (A’C)、（A，D)、（B，C)、（B，D) ' (c，D) 這些不同組合方式。這些組合方式係可將有瑕症之相同規格 記憶體，針對發生在不同輸出/入腳位之情形予以有效利用與 分類而所作之設定。 明芩閱圖一 B，係為習用技術對一含有8支資料輸出/入 腳位之記憶體所作之設定，其中將該記憶體之輸出/入腳位 DQO〜DQ7分為四部分，分別是(DQ〇，DQ1)為A、（卿， ，请B、（DQ4，DQ5)為c、（DQ6，吵)為d，則在對記 十思體杈組之佈線設計時對記憶體輸出/入腳位DQ PIN作選 擇，則有六種變化分別是（A，B)、（A，C) ' (A，D)二 (B’C)、（B，D)、（c，Dw些不同組合方這些 組合方式係可將有瑕疵之相同規格記憶體，針對發生在不同 輸出/入腳位之情料財效_與分_所作之設定。 明ί閱圖一 C，係為習用技術對一含有％支資料輸出/ 入腳位之記髓所作之奴，其帽航紐之輸似入腳位 DQ〇〜DQ 15分為四部分，分別是(DQO，DQ1，Dq2，DQ3) --------------裝--- (請先閱讀背面之注¥?事項再本頁) · ;線·Mbytes ’8Mbytes’ 16Mbytes ’32Mbytes and so on, and with the design of different memory modules, memory particles with different design specifications and capacities. And whether it is SDR or DDR or other types of memory particles, there will be some problems in manufacturing. That is, although the process of manufacturing the memory particles is a semiconductor process with complicated processes and strict conditions, the improvement of its yield is also the goal of the semiconductor manufacturers, but in this case § the memory particles are in the process There will still be defective products. Except for a few of these defective memory particles, which are completely unusable due to serious damage, the other are small areas of damage, and these areas can still be used in small areas. The damaged memory particles are used and designed. In actual design, most of them are to logically distinguish the memory particles or to design the pins of the memory module to achieve the purpose of reusing the memory particles and achieving the effective reuse of resources. . In the design of the memory module pins, in general, the available memory is selected from the defective memory, and a number of compatible designs are collected in the memory module. According to the available data input / output pins (DQPIN), appropriate combinations are made to make several memories in one memory module. In the current cutting design of the memory pins, the module wiring design of different wiring combinations needs to be made for the memory of the same specification, so as to cover the printed clothing of the Intellectual Property Bureau employee consumer cooperative of the Ministry of Economic Affairs 521273 A7 —_ — I — B / V. Description of the invention (j) The memory of this specification can only be fully memorized when it is used in various situations when the data is rotated out / entered. Various foot cutting methods can be made. Please refer to Figure-A, which is a conventional technique for setting a clock with 4 data output / input pins. The shooting_slimming touch / input pins DQO ~ DQ3 are divided into four parts, which are Dq〇 For A, Qing for B, Qing for C, DQ3 $ D, then when selecting the memory output / input pin DQPIN when wiring the memory module, there are six changes: (A, ⑴ , (A'C), (A, D), (B, C), (B, D) '(c, D). These combinations can be used to store the same size of memory with defects. The settings made for the effective use and classification of situations that occur in different output / input pins. Clearly refer to Figure 1B, which is a setting for conventional technology on a memory with 8 data input / input pins. Among them, the memory input / output pins DQO ~ DQ7 are divided into four parts: (DQ0, DQ1) is A, (Qing, please B, (DQ4, DQ5) is c, (DQ6, noisy) When it is d, when selecting the memory output / input pin DQ PIN in the wiring design of the mind ten body group, there are six changes: (A, B), (A, C) '(A , D) two (B'C ), (B, D), (c, Dw) These different combinations can be used to make defective memory of the same specification, for the effects that occur at different output / input positions. The setting is shown in Figure 1C, which is a slave of the conventional technique to a memory containing% data output / input position. The input and output of the hat flight are like four input positions DQ0 ~ DQ 15. It is divided into four parts. , Which are (DQO, DQ1, Dq2, DQ3) -------------- install --- (please read the note on the back of the ¥? Matter and then this page) ·; line ·
521273 A7 經濟部智慧財產局員工消費合作社印製 B7 五、發明說明（ψ) ' ~ 為 A、（DQ4，DQ5，DQ6，DQ7)為 Β、（DQ8，DQ9，DQ1〇， DQ11)為 C、（DQ12 ’ DQ13，DQ14 ’ DQ15)為 D，則在對記 憶體模組之佈線設計時對記憶體輪出/入腳位DQ画作選 擇’則有六種變化分別是（Α，Β)、（Α，〇、（a，d): (B’C)/、（B，D)、（C，D)這些不同組合方式。這些 組合方式係可將有瑕疵之相同規格記憶體，針對發生在不同 輸出/入腳位之情形予以有效利用與分類而所作之設定。 請參晒二A至®二C ’均係針對圖―B在對記憶體作 資料輸出/入腳位之設定後對於輪出/入腳位電路佈線之設 計。圖二A係習用技術針對圖一 B在對記憶體作資料輸出又/ 入腳位之設定中以（A，B)之選财式對於輸出/入腳位電 路佈線之設計。如圖三A所示係在（A，B) ;^式時之佈線 設計，DQO、DQ1係為A部分，DQ2、Dq3係為B部分， DQ4、DQ5係為C部分，DQ6、DQ7係為〇部分，並且每 一支資料輸出輪入腳位(DQO〜DQ7)分別連接有一 私卿a、122a、123a、124a、125a、126a、127a=^ 再者，相對應於記憶體資料輸出/入腳位之（DQ〇〜D(^7)， 亦設計連接有來自記憶體模組上俗稱金手指腳位中之 SDQO、SDQ卜 SDQ2、SDQ3 腳位之銲墊 12ib、i22b、123b、 124b、125b、126b、127b、128b。其中藉由零歐姆電阻 12〇 分別連接銲墊 121a 與 121b、122a 與 122b、123a 與 123b、124a 與124b而選擇到記憶體顆粒12中之資料輸出/入腳位中之 (DQO〜DQ3)，此亦表示記憶體12中資料輪出輸入腳位 DQ4〜DQ7可能至少有一支不能使用，亦即表示相對於該不 本紙張尺度適財關家標準（CNS)A4祕（21G x 29s7公餐） -------- f請先閱讀背面之>i¥?事項再β►本頁> 裝 二叮· --線· 521273 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（f ) 可使用之資料輸出/入腳位之記憶體内部有瑕疵，而不能使用 該有瑕/疵區域所相對的資料輸出/入腳位。 圖二B係習用技術針對圖一 B在對記憶體作資料輸出/ 入腳位之設定中以（B，C)之選擇方式對於輪出/入腳位電 路佈線之設計。如圖二B所示，DQ2、DQ3係為B部分， DQ4、DQ5係為C部分，並且資料輸出輸入腳位(DQ2〜Dq5) 分別連接有一接觸銲墊123a、124a、125a ' 126a。再者，相 對應於記憶體資料輸出/入腳位之（DQ2〜DQ5)，亦設計連 接有來自記憶體模組上俗稱金手指腳位中之SDqq、SDQ1、 SDQ2、SDQ3 腳位之銲墊 121b、122b、123b、124b、125b、 126b、127b、128b。其中，銲墊 121b 與 126b 連接，122b 與 125b連接123b與127b連接，124b與128b連接，其中藉由 零歐姆電阻120分別連接銲墊123a與123b、124a與124b、 125a與125b、126a與126b而選擇到記憶體顆粒丨2中之資 料輸出/入腳位中之(DQ2〜DQ5)，此亦表示記憶體12中資料 輸出輸入腳位DQ0與DQ1可能至少有一支不能使用，而且 賀料輸出輸入腳位DQ6與DQ7可能至少有一支不能使用， 故選擇此種佈線設計方式。 圖二B係習用技術針對圖一 B在對記憶體作資料輸出/ 入腳位之設定中以（C，D)之選擇方式對於輸出/入腳位電 路佈線之設計。如圖二C所示，DQ4、DQ5係為c部分， DQ6 ' DQ7係為D部分，並且資料輸出輸入腳位(Dq4〜Dq7) 分別連接有一接觸銲墊125a、126a、127a、128a。再者，相 對應於記憶體資料輸出/入腳位之（DQ4〜DQ7)，亦設計連 請 先 閱 讀 面 之 注 意 事 項 f 裝 叮 線 發明說明（L) 接有來自記憶體模组上俗稱金手指腳位中之SDQO、SDQ1、 SDQ2、SDQ3腳位之銲墊121b〜128b。其中，銲墊121b與 126b 連接，122b 與 125b 連接 123b 與 127b 連接，124b 與 128b 連接，其中藉由零歐姆電阻120分別連接銲墊125a與125b、 126a與126b、127a與127b、128a與128b而選擇到記憶體顆 粒12中之資料輪出/入腳位中之①q4〜Dq7)，此亦表示記憶 體12中資料輸出輸入腳位DQ0〜DQ4可能至少有一支不能使 用，故選擇此種佈線設計方式。… 絲合圖二A至圖二C，可知一具有8條輸出/入腳位之具 有部分瑕疲區域記憶體在安農i至一記憶麵組作腳位佈線 設計時，必須適當選擇有興同類型的具瑕疵之記憶體，依其 習用對資料腳位之切割設計來作佈線只能有3種形式的佈線 没汁，亦即是當有組合若干個有瑕疵但尚可使用之記憶體 時’需挑選類型相同且各若干個記憶體之瑕錄出/入聊位均 可互相配合之情況下方能作有效之利用。若要完全利用所有 圮fe體貧料輸出/入腳位之各種情形，則需製作相對應於該類 型之佈線方式的電路板。 、 、而不管記憶體是如圖-A所示僅具有4條輪出/入腳位， 或者是如同圖一 C所示具有16條輸出/入腳位，甚至具有更 多條的資料輪出/入腳位，其針對有瑕敵記憶體之記憶體模 組之線路佈線設計均有類似之設計方式與問題。 、 、，根據上述習用技術在對記憶體輸出/入腳位之切割與合 併’仍然具雜多之缺點與所需改進之處，亦即是對於某二 規格之記憶體而言，必須製作多種不同佈線設計方式的模 ^1273 A7 五、發明說明（^ ; 組，以期能對各種不同情形之輸出/入腳位之瑕疲予以全部概 括在此情形下對於記憶體模、板之開發與設計均增加成本負 擔’不僅要耗費人力與物力之龍、，在整健程上亦顯得複 雜 經濟部智慧財產局員工消費合作社印制衣 (三）發明簡要說明： 本發明係為解決上述習用技術之缺點所做的進一步改 ^。^發明之主要目的，係藉由記髓模組巾電路佈線之設 2提出-種記憶體模組對記憶體顆粒之輸似入腳位設定、 :併與利狀改良方法，以對記㈣馳與記髓之記憶容利職有效設計歧良。本發3狀ρ目的，係可對有域她之記鐘_分與騎，並可賴數個損壞之 體二十边合亚設計於—記體模組巾，以觸複數個記憶 體之心It體容量之制用翻較高之效果。 本1⑽提供-種以I體模組腳位佈線S計之裝置與方 Uli括有—電路板、—第—銲墊組、—第二銲墊組成。 二、—板係提供記憶體之安袭並且有電性通路；該第一鮮墊 f，^數個係連接到該複數個記憶體所域；該第二銲墊 ’、由複數個連接觀憶雜組連接到記憶雜組插槽之 置塾，成:藉由對第一鲜塾組與第二銲墊級交錯設細φ件該第—㈣組巾之任何—個銲墊對赫近之第一銲 、、、中之若干個銲墊之連接具有選擇性。 請 先 間 讀 一背 意 事 項 t 裝 訂 線 521273 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（） (四）發明圖示說明： 圖-A係為習用技術對—含有4支資料輸出/入腳位之蕾 體所作之設定。 ° ^ 圖-B係為習用技術對一含有8支資料輸出/入腳位之娜 體所作之設定。 圖- c係為習用技術對一含有16支資料輸出/入腳位之記 憶體所作之設定。 圖二八係習用技術針對圖—8在對記憶體之資料輪出/入腳 位之奴中以（A，Bk選擇方式之電路佈線設計。 圖二B係習用技術針對圖—B在對記憶體之資料輸出/入腳 位之設定巾以（B，C)之聰方紅佈線設計。 圖以係習用技術針對圖一 ^對記憶體之資料輸出/入腳 =設定中以（C，Dk選擇方式之電路佈線設計。 圖二A係、本發明對具有8支資料輸出/入腳位之記憶體之電 路佈線之設計。 圖三B係本發明對具有8支資料輪出/入腳位之記憶體以 U ’ B)之選擇方式之電路佈線設計。 C係本發明對具有8支資料輪出/入腳位之記憶體以 (A ’ C)之選擇方式之電路佈線設計。 D係本發賴料8支轉輪出从雜之記憶體以 U’D)之選擇方式之電路佈線設計。 E係本發明對具有8支資料輪出/入腳位之記憶體以 Q - F二\C)之選擇方式之―佈線設計。 圖二Ρ彳棘伽有8支轉續位之記憶體以 圖 圖 圖 --------------裝--- (請先閱讀-t面之注咅心事項里本頁) 訂： -·線- 本纸張尺度適用中國®^i^NS)A4規格（21〇: 297 公f ) 521273 A7 五、發明說明（1 ) (B，D)之選擇方式之電路佈線設計。 圖三G係本發明對具有8支資料輪出/入腳位之記憶體以 (c，D)之選擇方式之電路佈線設計。 圖號說明： 11，12，13記憶體 120，300零歐姆電阻 121a，121b ’ 122a，122b，123a，123b，124a，124b 銲墊 125a ’ 125b，126a，126b，127a，127b，128a，128b 銲墊 200，201 ’ 202 ’ 203 ’ 204 ’ 205 ’ 206，207 銲墊 30，302，303，304 銲墊 (五）發明詳細說明： 本叙明係在一 §己丨思體模組之電路基板上，針對該電路板 上可文裝複數個記憶體顆粒之資料輸出/入腳位，以及相關電 性連結通路所做之設計。藉由第一個銲墊組與第二個銲墊組 之父錯設計，並利用零歐姆電阻來選擇性的連接所要連接該 鲜塾所相對之腳位，以達到對記憶體顆粒中輸出/入腳位之切 割選擇與設計。其中第-銲墊組係由連接至記憶體顆粒之資 料輸出/入腳位(DQ PIN)之銲墊經成，第二銲墊組係由連接至 記憶體模組之金手指之資料腳位（SDQpiN)之銲墊組成。 圖二A至圖二F ’係本發明對8支資料輸出/入腳位之 記憶體之電路佈線設計之一較佳實施例。其中如圖三a所 示，銲墊 200、2m、202、203、204、205、206'2〇7 係分別 連接至記憶體顆粒之輸出輸入腳位DQ〇、DQ1、DQ2、D(^3、 --------------裝—— (請先閱讀’面之注咅？事項本頁) · ' 線· 經濟部智慧財產局員工消費合作社印製 M氏張尺度翻巾關家鮮（CNS)A4規格（2ι〇· χ 297 公 f ) 521273521273 A7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs B7 5. The description of the invention (ψ) '~ is A, (DQ4, DQ5, DQ6, DQ7) is B, (DQ8, DQ9, DQ10, DQ11) is C, (DQ12 'DQ13, DQ14' DQ15) is D, then when the wiring design of the memory module is selected, the memory wheel out / in pin DQ drawing is selected. 'There are six changes: (Α, Β), ( Α, 〇, (a, d): (B'C) /, (B, D), (C, D) These different combinations. These combinations can be defective memory of the same specification, for The settings for different output / input pins are effectively used and classified. Please refer to the two A to ®C 'for the figure-B. After setting the data input / input pins to the memory, The design of the wiring of the I / O pins. Figure 2A is a conventional technique for Figure 1B. In the setting of data output to the memory and the I / O pins, the choice of (A, B) is used for the I / O pins. Bit circuit wiring design. As shown in Figure 3A, the wiring design is in (A, B); ^ type, DQO, DQ1 is part A, DQ2, Dq3 is part B DQ4 and DQ5 are part C, DQ6 and DQ7 are part 0, and each data output wheel input pin (DQO ~ DQ7) is connected with a private secretary a, 122a, 123a, 124a, 125a, 126a, 127a = ^ Furthermore, corresponding to the memory data output / input pin (DQ〇 ~ D (^ 7)), it is also designed to connect SDQO, SDQ and SDQ2 from the commonly known golden finger pins on the memory module. , SDQ3 pads 12ib, i22b, 123b, 124b, 125b, 126b, 127b, 128b. Among them, pads 121a and 121b, 122a and 122b, 123a and 123b, 124a and 124b are connected by a zero ohm resistance 120. And the data output / input pin (DQO ~ DQ3) in the memory particle 12 is selected, which also means that at least one of the data rotation input pins DQ4 ~ DQ7 in the memory 12 cannot be used, which means that it is relatively In this paper, the standard of financially appropriate family standards (CNS) A4 (21G x 29s7 meals) -------- f Please read the > i ¥? Items on the back first and then β►this page > Zhuang Erding · --line · 521273 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (f) Available Information There is a defect in the memory of the input / output pin, and the relative data output / input pin of the defective / defective area cannot be used. Figure 2B is a conventional technology. For Figure 1B, data is output / input to the memory. In the setting of the pin position, the design of (B, C) is used to design the circuit of the wheel out / in pin position. As shown in FIG. 2B, DQ2 and DQ3 are part B, DQ4 and DQ5 are part C, and the data input / output pins (DQ2 ~ Dq5) are respectively connected with contact pads 123a, 124a, 125a '126a. In addition, corresponding to the memory data output / input pins (DQ2 ~ DQ5), it is also designed to connect the pads from SDqq, SDQ1, SDQ2, SDQ3 pins commonly known as golden finger pins on the memory module. 121b, 122b, 123b, 124b, 125b, 126b, 127b, 128b. Among them, pads 121b and 126b are connected, 122b and 125b are connected 123b and 127b, and 124b and 128b are connected. Among them, pads 123a and 123b, 124a and 124b, 125a and 125b, 126a and 126b are connected by zero ohm resistance 120, respectively. Select to the data output / input pin (DQ2 ~ DQ5) in the memory particle 丨 2, which also means that at least one of the data output input pins DQ0 and DQ1 in the memory 12 may not be used, and the consignment output input At least one of DQ6 and DQ7 pins may not be used, so this wiring design method is selected. Figure 2B is the conventional technology. For Figure 1B, in the setting of the data output / input pin to the memory, (C, D) is used to design the output / input pin circuit wiring. As shown in FIG. 2C, DQ4 and DQ5 are part c, DQ6 'and DQ7 are part D, and the data input and input pins (Dq4 ~ Dq7) are respectively connected with contact pads 125a, 126a, 127a, and 128a. In addition, corresponding to the memory data output / input pin (DQ4 ~ DQ7), it is also designed. Please read the precautions on the front side. F. Description of the invention of the installation wire (L). It is commonly called gold from the memory module. Pads 121b ~ 128b for SDQO, SDQ1, SDQ2, and SDQ3 pin positions in the fingers. Among them, pads 121b and 126b are connected, 122b and 125b are connected, 123b and 127b are connected, and 124b and 128b are connected. Among them, pads 125a and 125b, 126a and 126b, 127a and 127b, and 128a and 128b are connected through a zero-ohm resistor 120, respectively. Select the data in / out pin of the memory particle 12 (①q4 ~ Dq7), which also means that at least one of the data output / input pins DQ0 ~ DQ4 in the memory 12 may not be used, so choose this wiring design the way. … Figure 2A to Figure 2C, we can see that a memory with partial defect area with 8 output / input pins has the proper wiring design when it is used for pin layout in Annong i to a memory surface group. Defective memory of the same type can only be wired in three forms according to its cutting design for data pins. That is, when there are several defective but usable memories When you need to select the same type, and each of the several memory defect recording / entrying bits can cooperate with each other, it can be effectively used. If you want to fully use all the situations of the input / output pins of the 贫 fe body, you need to make a circuit board corresponding to this type of wiring method. , Regardless of whether the memory is shown in Figure-A with only 4 round-out / in-pins, or as shown in Figure 1C with 16 output / in-pins, or even more data rotation-out / In the foot position, the circuit wiring design for memory modules with defective memory has similar design methods and problems. According to the above-mentioned conventional techniques, the cutting and merging of the memory input / output pins still has a variety of disadvantages and required improvements, that is, for a memory of a two specifications, a variety of Modules with different wiring design methods ^ 1273 A7 V. Description of the invention (^; group, in order to be able to summarize all the flaws of the output / input pins in various situations. In this case, the development and design of memory modules and boards Both increase the cost burden 'not only consumes the dragon of manpower and material resources, but also appears complicated in the whole health process. The clothing of the Intellectual Property Bureau of the Ministry of Economic Affairs's consumer cooperatives prints clothing. (III) Brief description of the invention: This invention is to solve the above-mentioned conventional technologies. Disadvantages made further changes. ^ The main purpose of the invention is to propose the circuit wiring design of the memory module module 2-a memory module to the memory particle input pin settings, and the same shape Improved method to effectively design ambiguity with the memory and memory of the memory and the memory of the mind. The purpose of this 3-phase ρ is to be able to use the clock_minute and ride of her domain, and can rely on several damaged bodies. Icosa Counting in — remembering the body module towel, it has a higher effect by touching the memory capacity of several memory cores. It provides a kind of device and side Uli brackets based on the I body module pin wiring S There are-circuit board,-first-solder pad group,-second solder pad. Second,-the board is to provide the security of the memory and has an electrical path; the first fresh pad f, ^ several are connected to the The area of the plurality of memories; the second pad is connected to the slot of the memory miscellaneous group by a plurality of connection memorizer groups, so that the first pad group and the second pad level are staggered It is assumed that any of the ㈣ pads of any of the ㈣ pads is selective to the connection of several pads near the first welding pad, 、, and 赫. Please read a note first t binding line 521273 A7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention () (4) Illustration of the invention: Figure-A is a set of conventional technology for a bud body with 4 data input / output positions. ° ^ Figure-B is a conventional technique for setting a body with 8 data input / output pins. Figure-c The conventional technology is used to set a memory with 16 data output / input pins. Figure 28 is the conventional technology for Figure-8. (A, Bk) The circuit wiring design of the selected method. Figure 2 B is the conventional technology for the figure-B is set to the data output / input pin of the memory with the (B, C) of the smart red wiring design. The diagram is based on the conventional technology. Figure 1 ^ Data output / input pin for memory = circuit wiring design with (C, Dk selection mode in the setting. Figure 2 A, the present invention circuit wiring for memory with 8 data output / input pins The design is shown in Figure 3. B is the circuit wiring design of the invention with U'B) for the memory with 8 data wheels out / in. The C is the invention with 8 data wheels out / in. The circuit layout design of the bit memory is (A'C). D is the circuit wiring design based on the choice of 8 runners out of miscellaneous memory in the U'D) selection mode. E is the wiring design of the present invention in the form of Q-F2 \ C) for memory with 8 data wheel out / in pins. Figure 2 P 彳 Acupuncture memory with 8 renewal positions -------------- install --- (Please read the note on -t side first (This page) Order:-· Line-This paper size is applicable to China® ^ i ^ NS) A4 specification (21〇: 297 gf) 521273 A7 V. Description of the invention (1) (B, D) Circuit of selection method Wiring design. Fig. 3G is a circuit wiring design of the present invention using the (c, D) selection method for a memory having eight data wheel out / in pins. Drawing number description: 11, 12, 13 memory 120, 300 zero ohm resistance 121a, 121b '122a, 122b, 123a, 123b, 124a, 124b pads 125a' 125b, 126a, 126b, 127a, 127b, 128a, 128b Pads 200, 201 '202' 203 '204' 205 '206, 207 Pads 30, 302, 303, 304 (5) Detailed description of the invention: This description is a circuit board of a module In the above, the design for the data input / output pins of a plurality of memory particles that can be mounted on the circuit board and related electrical connection paths. By using the wrong design of the first pad group and the second pad group, and using a zero ohm resistor to selectively connect the opposite pins of the fresh pad to be connected, the output of the memory particles / Choice and design of cutting into the feet. The first pad group is formed by the pad connected to the data output / input pin (DQ PIN) of the memory particles, and the second pad group is formed by the data pin of the gold finger connected to the memory module. (SDQpiN). Figures 2A to 2F 'are a preferred embodiment of the circuit wiring design of the present invention for the memory of 8 data input / output pins. Among them, as shown in FIG. 3a, the pads 200, 2m, 202, 203, 204, 205, and 206'207 are connected to the output and input pins DQ0, DQ1, DQ2, and D (^ 3 of the memory particle, respectively). 、 -------------- install—— (Please read the 'Notes on the noodles? Matters page first] ·' Line · Printed M-sheet scale by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Folding towels Guan Jiaxian (CNS) A4 size (2ιχ · 297 male f) 521273
五、發明說明（γ) DQ4、DQ5、DQ6、DQ7。並且銲墊 300'30卜 302、303 係 分別連接至記憶體模組中俗稱金手指之連接至記憶體模組插 槽之腳位SDQ0、SDQ卜SDQ2、SDQ3中。並且其銲墊之設 計方式係將連接至金手指之銲墊3〇〇、301、302、303交錯設 計於連接至記憶體輸出/入腳位DQ0〜DQ7腳位之銲墊中，形 成銲墊300與銲墊200、202、204鄰接，銲墊301與銲塾202、 204、206鄰接，銲墊302與銲墊201、203、205鄰接，銲墊 303與銲墊203、205'207鄰接。並將(DQ〇 , DQ1)設為A、 (DQ2 ’ DQ3)設為 B、（DQ4，DQ5)設為 C、（DQ6，DQ7)設 為D。接者可使用零歐姆電阻來選擇性的連接與SDQ〇〜SDQ3 的各鄰接DQ0〜DQ7之腳位，以達到對有瑕寐區域記憶體之 資料輸出/入腳位之切割與設計。 請參閱圖三B，係本發明對具有8支資料輸出/入腳位之 記憶體以（A，B)之選擇方式之電路佈線設計。其中以零歐 姆電阻300分別地連接SDq〇之銲墊3〇〇與DQ〇之銲墊2〇〇、 SDQ1之麵墊301與DQ2之銲墊202、SDQ2之銲墊302與 DQ1之銲塾201、SDQ3之銲塾303與DQ3之銲塾203。如 此則使DQG、DQ卜DQ2 ' DQ3分別連接至SDQG〜SDQ4， 經濟部智慧財產局員工消費合作社印製 此種設計之方式用到該記體輸出入腳位之DQ〇〜DQ3，表示 該顆記憶體其他之輸出入腳位DQ4〜Dq7中可能至少有一支 腳位，因記憶體内部之瑕疵而不能使用該腳位。 請參閱圖三(：，係本發明對具有8支資料輸出/入腳位之 疏、體以（A，C)之獅方式之電路佈線設計。其中以零歐 姆電阻300分別地連接SDQ〇之鮮塾3〇〇與卿之鲜塾游 521273 A7 ' -------—---- 五、發明說明（"） ---- --- (請先閱讀"t面之注咅？事項本頁) SDQ1之銲墊301與DQ4之銲墊204、SDQ2之銲墊302與 DQ1之銲墊201、SDQ3之銲墊303與DQ5之銲墊205，如 此則使DQ0、DQ卜DQ4、DQ5分別連接至SDQ0〜SDQ4， 此種設計之方式用到該記體輸出入腳位之DQ〇、dqi、DQ4、 DQ5 ’表示該顆記憶體其他之輸出入腳位dq]、DQ3、DQ6、 DQ6中可能至少有一支腳位因記憶體内部之瑕疵而不能使用 該腳位。 請參閱圖三D，係本發明對具有8支資料輸出/入腳位 之記憶體以（A，D)之選擇方式之電路佈線設計。其中以零 歐姆電阻300分別地連接SDQ0之銲墊300與DQ0之銲塾 200、SDQ1之銲墊301與DQ6之銲墊206、SDQ2之銲墊302 與DQ1之銲墊201、SDQ3之銲墊303與DQ7之銲墊207， 如此則使DQ0、DQ卜DQ6、DQ7分別連接至SDQ0〜SDQ4， 此種设計之方式用到該記體輸出入腳位之DQ〇、dqi、DQ6、 DQ7 ’表示該顆記憶體其他之輸出入腳位DQ2、DQ3、DQ4、 -線- DQ5中可能至少有一支腳位因記憶體内部之瑕疵而不能使用 該腳位。 經濟部智慧財產局員工消費合作社印製 請參閱圖三E，係本發明對具有8支資料輸出/入腳位 之記憶體以（B，C)之選擇方式之電路佈線設計。其中以零 歐姆電阻300分別地連接SDq〇之銲墊3〇〇與Dq4之銲墊 204、SDQ1之銲墊3〇1與DQ2之銲墊2〇2、SDq2之銲墊3〇2 與DQ5之銲墊205、SDQ3之銲墊303與DQ3之銲墊203， 如此則使DQ2、DQ3、DQ4、DQ5分別連接至SDQ0〜SDQ4， 此種没计之方式用到該記體輸出入腳位之Dq2、Dq3、Dq4、 本紙張尺錢財關家標準(CNS)A4 X 297公f ) A7 五、發明說明（ Q5表示u亥顆d己憶體其他之輸出入腳位DQo'DQi、DQ6、 DQ7中可^至少有—支卿L目記紐内部之碱而不能使用 該腳位。 3請參_三F，係本發日麟具有8支資料輸出/入腳位之 Zfe體以（B ’D)之選擇方式之電路佈線設計。其中以零歐 姆迅阻300分別地連接SDq〇之銲墊3⑻與dq2之銲墊2犯、 SDQ1之銲墊301與DQ6之銲墊2〇6、sdq2之鲜塾搬與 DQ3之銲塾203、SDQ3之銲塾303與DQ7之銲塾207，如 此則使DQ2、DQ3、DQ6、DQ7分別連接至SDQ0〜SDQ4， 此種认。十之方式用到该記體輸出入腳位之、dq3、dq6、 DQ7，表示該顆記憶體其他之輸出入腳位DQ〇、DQh DQ4、 DQ5中可能至少有 — χ驗目記憶動部之瑕赫不能使用 該腳位。 請參閱圖三G，縣發明對具有8支資料輸出/入腳位之 記憶體以（C，D)之選擇方式之電路佈線設計。其中以零歐 姆電阻300分別地連接SDQ0之銲墊3⑻與DQ4之銲墊 2〇42、SDQ1之銲墊3〇1與Dq6之銲墊2〇6、SDQ2之鲜墊 302與DQ5之銲塾2〇5、SDQ3之銲塾3〇3與DQ7之鲜塾 207，如此則使DQ4 ' Dq5 ' DQ6、DQ7分別連接至 SDQ0〜SDQ4，此種設計之方式用到該記體輸出入腳位之 DQ4、DQ5、DQ6 ' DQ7，表示該顆記憶體其他之輸出入腳 位DQ0、DQ卜DQ2、DQ3巾可能至少有一支腳位因記憶體 内部之瑕疵而不能使用該腳位。 綜合圖三B至圖三G所述，可知只要設計一種電路佈線 521273 A7 五、發明說明（θ 〜 之設計方式，剔零_電阻之選擇變化种可對記體 之輸出入腳位有6種之聊方式。itt觀計方式可節情 體模、、且之開發、組裝與設計之成本並改善制技術之缺失i &當然圖三A至圖三G之所述’僅對本發明應用至—具8 支資料輪出/入腳位之記憶體設計彳式之較佳實顧列，事每上 此種設計方法亦可制至具有其錄目的㈣輸出/入ς位 之记憶體’譬如是具有16支或32支倾腳位之記憶體均可 利用本發明方法實施之。 -4上所述’本發明之結構特徵及較佳實施例皆已詳細揭 不充刀顯不出本發明案在目的及功效上均深富實施之進步 性，極具產業之利用價值，且為目前市面上前所未見之運用， 依專利法之精神所述，本發日輯完全符合發明專利之要件。 唯以上所述者’僅為本發明之各較佳實施例而已，因此 貝細例之所述’當不能用來限定本發明所實施之範圍。即大 凡依本發明申請專利範圍所作之均等變化與修飾，皆應仍屬 於本發明專利涵蓋之範圍内，謹請貴審查委員明鑑，並祈惠 准，是所至禱。 rtt先閱身背面之注意事項 r本頁} 裝 •線' 經濟部智慧財產局員工消費合作社印製 本^^尺度適用中國國家標準（CNS)A4 pV. Description of the invention (γ) DQ4, DQ5, DQ6, DQ7. And the pads 300'30, 302, and 303 are respectively connected to the pins SDQ0, SDQ, SDQ2, and SDQ3 of the memory module which are commonly referred to as golden fingers. And the design method of the pads is that the pads 300, 301, 302, and 303 connected to the gold fingers are staggered in the pads connected to the memory input / output pins DQ0 to DQ7 to form a solder pad. 300 is adjacent to pads 200, 202, 204, pad 301 is adjacent to pads 202, 204, 206, pad 302 is adjacent to pads 201, 203, 205, and pad 303 is adjacent to pads 203, 205'207. Let (DQ0, DQ1) be A, (DQ2 'DQ3) be B, (DQ4, DQ5) be C, and (DQ6, DQ7) be D. The user can use a zero ohm resistor to selectively connect the pins DQ0 to DQ7 adjacent to SDQ0 ~ SDQ3 to achieve the cutting and design of the data output / input pins of the defective area memory. Please refer to FIG. 3B, which is a circuit wiring design of the present invention in a manner of selecting (A, B) for a memory having 8 data input / output pins. Among them, zero-ohm resistance 300 is used to connect SDq〇 pad 300 and DQ〇 pad 200, SDQ1 pad 301 and DQ2 pad 202, SDQ2 pad 302 and DQ1 pad 201. , Welding pad 303 of SDQ3 and welding pad 203 of DQ3. In this way, DQG, DQ and DQ2 'DQ3 are connected to SDQG ~ SDQ4 respectively. The method of printing this design by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs uses DQ0 ~ DQ3 of the input and output pins of the recorder to indicate that the There may be at least one pin in the other input / output pins DQ4 ~ Dq7 of the memory. This pin cannot be used due to a defect in the memory. Please refer to FIG. 3 (:), which is a circuit wiring design of the present invention for a lion mode with 8 data output / input pins. The zero-ohm resistance 300 is connected to SDQ0. Xianjian 300 and Qingzhi Xianyou 521273 A7 '--------------- 5. Description of the invention (") ---- --- (Please read " t (Note? Matters on this page) Pads 301 and 204 of SDQ1, pads 302 and 302 of SDQ2, pads 201 of DQ1, pads 303 of SDQ3, and pads 205 of DQ5. DQ4, DQ5 are connected to SDQ0 ~ SDQ4 respectively. This design method uses the DQ0, dqi, DQ4, and DQ5 of the input and output pins of the recorder to indicate the other input and output pins of the memory dq], DQ3, At least one of the DQ6 and DQ6 pins cannot be used due to a defect in the memory. Please refer to FIG. 3D, which refers to a memory having eight data input / output pins according to the present invention (A, D ) Circuit layout design. Among them, zero-ohm resistance 300 is used to connect SDQ0 solder pad 300 and DQ0 solder pad 200, SDQ1 solder pad 301 and DQ6 solder pad 206, and SDQ2 solder. 302 and DQ1 pads 201, SDQ3 pads 303 and DQ7 pads 207, so that DQ0, DQ, DQ6, and DQ7 are connected to SDQ0 ~ SDQ4 respectively. This design method uses the recorder input and output Pin DQ0, dqi, DQ6, DQ7 'indicates that the other input and output pins of the memory DQ2, DQ3, DQ4, -line-At least one of the DQ5 pins cannot be used due to a defect in the memory. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics Please refer to Figure 3E, which is the circuit wiring design of the invention with (B, C) for the memory with 8 data input / input pins. The pad 300 of SDq〇 and pad 204 of Dq4, the pad of SDQ1 30, the pad of DQ2 202, the pad of SDQ2 30, and the pad of SDQ2 are respectively connected with a zero ohm resistance 300. Pad 205, pad 303 of SDQ3, and pad 203 of DQ3. In this way, DQ2, DQ3, DQ4, and DQ5 are connected to SDQ0 to SDQ4, respectively. This way of using DQ2, which is the input / output pin of the recorder, is not used. Dq3, Dq4, The paper rule for money and wealth (CNS) A4 X 297 male f) A7 V. Description of the invention The input and output pins DQo'DQi, DQ6, and DQ7 may have at least-the base inside the branch is not available for use. 3 Please refer to _three F, which has 8 data outputs. / The Zfe body in the pin position is designed with (B 'D) circuit layout. Among them, zero ohmic resistance 300 is used to connect the pad 3 of SDq0 and the pad 2 of dq2, the pad 301 of SDQ1 and the pad 20 of DQ6, the fresh pad of sdq2, and the pad 203 of DQ3. Solder pad 303 of SDQ3 and solder pad 207 of DQ7, so that DQ2, DQ3, DQ6, and DQ7 are connected to SDQ0 to SDQ4, respectively. The ten methods use the dq3, dq6, and DQ7 of the input and output pins of the record, indicating that there may be at least one of the other input and output pins of the memory, DQ0, DQh, DQ4, and DQ5-χ Imperfections cannot use this foot position. Please refer to Figure 3G. The county invented a circuit layout design for the memory with 8 data input / output pins in the (C, D) selection mode. Among them, the pad 3 of SDQ0 and the pad 2 of DQ4 2042, the pad of SDQ1 3 0 and pad 2 of Dq6, the pad 302 of SDQ2 and the pad 2 of DQ5 are respectively connected with a zero ohm resistance 300. 〇5, SDQ3 soldering 塾 3〇 and DQ7 fresh 207, so DQ4 'Dq5' DQ6, DQ7 are connected to SDQ0 ~ SDQ4, this design method uses the DQ4 of the input and output pins , DQ5, DQ6 'DQ7, it means that the other I / O pins DQ0, DQ, DQ2, and DQ3 of the memory may have at least one pin that cannot be used because of a defect in the memory. Based on the combination of Figure 3B and Figure 3G, we can know that as long as you design a circuit wiring 521273 A7 V. Description of the invention (θ ~ Design method, there are 6 types of choices for the input and output pins of the resistor. Talk method. The itt observation method can reduce the cost of phantoms, and the development, assembly, and design costs and improve the lack of manufacturing technology. Of course, the description in Figures 3A to 3G is only applicable to the present invention. —The best practical considerations of the memory design mode with 8 data wheel out / in positions, each design method can also be made to the memory with its recorded ㈣ output / in bit position ' For example, a memory with 16 or 32 tilted feet can be implemented by the method of the present invention. -4 The structural features and preferred embodiments of the present invention described above have not been revealed in detail. The invention case is deeply implemented in terms of purpose and effect. It has great industrial use value and is an application that has never been seen on the market. According to the spirit of the patent law, this issue is fully in line with the invention patent. The only requirements described above are merely preferred embodiments of the present invention. It ’s just an example, so the “before and after” detailed in the detailed example of “Beijing” cannot be used to limit the scope of the present invention. That is to say, all equal changes and modifications made according to the scope of the patent application for the present invention should still fall within the scope of the invention patent I would like to ask your reviewing committee to make a clear reference and ask for your respect. Rtt Please read the notes on the back of this page. R This page} Installation and wiring 'Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ^^ The standard is applicable to China Standard (CNS) A4 p