CN212990051U - Mainboard memory bank layout structure - Google Patents
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- CN212990051U CN212990051U CN202022441718.8U CN202022441718U CN212990051U CN 212990051 U CN212990051 U CN 212990051U CN 202022441718 U CN202022441718 U CN 202022441718U CN 212990051 U CN212990051 U CN 212990051U
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Abstract
The utility model provides a pair of mainboard DRAM layout structure, include: the PCB board is provided with a CPU, and a first memory bank slot and a second memory bank slot are symmetrically arranged on two sides of the CPU board; the CPU is connected with a first memory bank slot through an MC0 channel, and is connected with a second memory bank slot through an MC1 channel; the MC0 channel and the MC1 channel have the same structure and both comprise: a signal line and a power supply line; the signal line and the power line are respectively connected with different reference layers; the utility model discloses have the beneficial effect of interference between the reducible high-speed signal, be applicable to the technical field of PCB board design.
Description
Technical Field
The utility model belongs to the technical field of the design of PCB board, concretely relates to mainboard DRAM layout structure.
Background
In the main stream main board design, the position of the memory bank is indispensable, a dedicated memory slot needs to be left for the memory bank on the main board, and two independent memory bank slots are needed to meet the requirement of user expandability.
At present, various manufacturers are used to design a mainboard memory slot on the same side of a CPU, and this way can lead to the concentration of high-speed signal lines in the area of the memory and the CPU, along with the update iteration of DDR4/DDR5, the high-speed wiring of the memory is more and more increased, the speed is faster and faster, and in the layout and wiring of the PCB, in order to meet the requirement of the same length in a signal line group, the wiring area is limited to be processed between the memory and the CPU, so that the high-speed wiring is too dense, and the risks of crosstalk, impedance mismatching and the like are increased.
For the above problems, a general manufacturer usually adopts a method of increasing the layer thickness, or enlarging the wiring area or sacrificing the performance, and reducing the yield in the design and production of the motherboard to solve the problem, and the above methods all bring unnecessary cost increase to the enterprise.
In addition, unnecessary workload brought by the same side setting of the memory slots also has the memory power supply requirement, for example: according to the PCB design principle, the power supply and the high-speed signal are isolated, and at the moment, a designer has to continuously divide a necessary power supply area in a limited space to design a power supply scheme.
The above problems not only increase the design workload, but also easily cause the whole DDR design to be compact and the interference between high-speed signals to increase.
SUMMERY OF THE UTILITY MODEL
The utility model overcomes the deficiencies in the prior art, the technical problem who solves is: a motherboard memory layout structure capable of reducing interference between high-speed signals is provided.
In order to solve the technical problem, the utility model discloses a technical scheme be:
a motherboard memory bank layout structure, comprising: the PCB board is provided with a CPU, and a first memory bank slot and a second memory bank slot are symmetrically arranged on two sides of the CPU board;
the CPU is connected with a first memory bank slot through an MC0 channel, and is connected with a second memory bank slot through an MC1 channel;
the MC0 channel and the MC1 channel have the same structure and both comprise: the signal lines are used for communicating the CPU with the first memory bank slot and communicating with the CPU second memory bank slot; and the reference layer of the signal line is the fifth layer of the PCB.
Preferably, the method further comprises the following steps: the power supply module is arranged on the other side of the CPU and is positioned between the first memory bank slot and the second memory bank slot;
the power module is electrically connected with the CPU, the first memory bank slot and the second memory bank slot through power lines.
Preferably, the signal line includes: the circuit comprises a data line, an address line, a bidirectional data strobe signal line, a data mask signal line, a logic BANK signal line, a physical chip selection signal line, a clock differential signal line, a clock enable signal line and a control signal line;
the power cord includes: a VDD power line, a VTT power line and a VREF power line;
the data line, the address line, the bidirectional data strobe signal line, the data mask signal line, the logic BANK signal line, the physical chip selection signal line, the clock differential signal line, the clock enable signal line, the control signal line, the VDD power line, the VTT power line and the VREF power line are respectively and correspondingly electrically connected with the data pin, the address pin, the bidirectional data strobe signal pin, the data mask signal pin, the logic BANK signal pin, the physical chip selection signal pin, the clock differential signal pin, the clock enable signal pin, the control signal pin, the VDD pin, the VTT pin and the VREF pin of the CPU.
Preferably, the PCB board is eight layers.
Preferably, the first memory bank slot and the second memory bank slot are both DDR3 memory slots.
Preferably, the CPU is a loongson 3a3000 processor.
Compared with the prior art, the utility model following beneficial effect has:
1. the utility model relates to a mainboard DRAM layout structure, fully consider the relevant pin position of CPU and the signal trend, improved the mounted position of DRAM, set up the DRAM in CPU 10's both sides respectively through first DRAM slot 20 and second DRAM slot 30 for high-speed on the mainboard is walked the line and is no longer intensive, reduces the interference between the high-speed signal, and simultaneously, also can satisfy comparatively complicated high-speed signal in less range upon range of design and arrange, and the practicality is strong.
2. In the utility model, the signal wire and the power wire are connected with different reference layers; the reference layer of the whole memory signal line is a fifth layer, the central symmetry principle is adopted, and the signal reference plane is a whole GND signal layer; and corresponding power supply segmentation is carried out on the third layer, the fourth layer, the sixth layer and the seventh layer, signals of the memory are distinguished from the power supply, and the interference between the signal line and the power line can be reduced.
Drawings
The present invention will be described in further detail with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of the circuit structure of the present invention;
FIG. 2 is a circuit diagram of a VDD power supply of the present invention;
FIG. 3 is a circuit diagram of a VREF power supply according to the present invention;
fig. 4 is a circuit connection diagram of the VTT power supply of the present invention;
in the figure: the CPU10, the first memory bank slot 20, the second memory bank slot 30, the MC0 channel 40 and the MC1 channel 50.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention; based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Next, the present invention will be described in detail with reference to the schematic drawings, and in the detailed description of the embodiments of the present invention, for convenience of illustration, the sectional view showing the device structure will not be enlarged partially according to the general scale, and the schematic drawings are only examples, and should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
The following describes an embodiment of a motherboard memory bank layout structure in detail with reference to the accompanying drawings.
Example one
Fig. 1 is a schematic diagram of the circuit structure of the present invention; as shown in fig. 1, a layout structure of a motherboard memory bank includes: the memory card comprises a PCB, wherein a CPU10 is arranged on the PCB, and a first memory bank slot 20 and a second memory bank slot 30 are symmetrically arranged on two sides of the CPU 10; the CPU10 is connected to the first memory bank slot 20 through the MC0 channel 40, and the CPU10 is connected to the second memory bank slot 30 through the MC1 channel 50; the MC0 channel 40 and the MC1 channel 50 have the same structure and both comprise: a plurality of signal lines for communicating the CPU10 with the first memory bank slot 20 and communicating the CPU10 with the second memory bank slot 30; and the reference layer of the signal line is the fifth layer of the PCB.
Specifically, the first memory bank slot 20 and the second memory bank slot 30 are both DDR3 memory slots.
Further, the CPU10 is a loongson 3a3000 processor.
The utility model relates to a mainboard DRAM layout structure, fully consider the relevant pin position of CPU and the signal trend, improved the mounted position of DRAM, set up the DRAM in CPU 10's both sides respectively through first DRAM slot 20 and second DRAM slot 30 for high-speed on the mainboard is walked the line and is no longer intensive, reduces the interference between the high-speed signal, and simultaneously, also can satisfy comparatively complicated high-speed signal in less range upon range of design and arrange, and the practicality is strong.
Example two
On the basis of the first embodiment, the method further comprises the following steps: and the power supply module 60 is arranged on the other side of the CPU10, and is positioned between the first memory bank slot 20 and the second memory bank slot 30.
In the second embodiment, the power module 60 is disposed on the other side of the CPU10 and located between the first memory bank slot 20 and the second memory bank slot 30, so that the distribution of power in the motherboard can be effectively reduced, and unnecessary influence of the power on high-speed signals is reduced to the minimum standard.
In the embodiment, the signal line and the power line are connected with different reference layers; the reference layer of the whole memory signal line is a fifth layer, the central symmetry principle is adopted, and the signal reference plane is a whole GND signal layer; and corresponding power supply segmentation is carried out on the third layer, the fourth layer, the sixth layer and the seventh layer, signals of the memory are distinguished from the power supply, and the interference between the signal line and the power line can be reduced.
EXAMPLE III
On the basis of the second embodiment, a layout structure of a main board memory bank is provided, where the signal line includes: the circuit comprises a data line, an address line, a bidirectional data strobe signal line, a data mask signal line, a logic BANK signal line, a physical chip selection signal line, a clock differential signal line, a clock enable signal line and a control signal line; the power cord includes: a VDD power line, a VTT power line and a VREF power line;
the data line, the address line, the bidirectional data strobe signal line, the data mask signal line, the logic BANK signal line, the physical chip selection signal line, the clock differential signal line, the clock enable signal line, the control signal line, the VDD power line, the VTT power line and the VREF power line are respectively and correspondingly electrically connected with the data pin, the address pin, the bidirectional data strobe signal pin, the data mask signal pin, the logic BANK signal pin, the physical chip selection signal pin, the clock differential signal pin, the clock enable signal pin, the control signal pin, the VDD pin, the VTT pin and the VREF pin of the CPU 10.
In this embodiment, each channel (MC 0 channel 40 or MC1 channel 50) is electrically connected to a pin of the CPU10 through a corresponding signal line.
Specifically, the pins of the CPU10 include: the device comprises a 64-bit data pin, a 15-bit address pin, a 9-bit bidirectional data strobe signal pin, a 9-bit data mask signal pin, a 3-bit logic BANK signal pin, a 4-bit physical chip selection signal pin, a 6-bit clock differential signal pin, a 4-bit clock enable signal pin, various control signal pins, a VDD pin, a VTT pin and a VREF pin which are correspondingly connected with a power line.
Wherein: the data pin is responsible for data transmission between the CPU and the memory;
the address pin is responsible for address information during data reading and writing each time and helps the CPU to accurately read the required data;
the bidirectional strobe signal pin functions to allow data to be transmitted through the rising and falling edges of DQS, which is sent from the memory to the CPU in read mode, aligned with the data edges. In a write mode, the DQS is sent to a memory by the CPU, and the DQS is aligned with the data in the middle;
the data mask signal pin is used for preventing effective information from being covered by a small data size in the write operation;
the logic BANK signal pin is used for processing the cooperative work among different memory grains;
the physical chip selection signal pin is used for selecting a high bus and a low bus;
the clock differential signal pin is used for providing a clock for the bus;
the clock enable signal pin is used for providing a transmission period for signal transmission.
In this embodiment, the power supply module 60 includes: VDD power supply circuit, VREF power supply circuit and VTT power supply circuit.
FIG. 2 is a circuit diagram of a VDD power supply of the present invention; as shown in fig. 2, the circuit structure of the VDD power supply includes: the PWM controller PU12 is characterized in that a VCC pin of the PWM controller PU12 is connected with one end of a resistor PR84 in parallel and then connected with one end of a capacitor PC125, the other end of the resistor PR84 is connected with a power supply end P5V _ DUAL in parallel and then connected with the anode of a diode PD2, and the cathode of the diode PD2 is connected with a power supply output end P1V5_ DUAL _ BOOT _ 20; the other end of the capacitor PC125 is grounded;
a COMP/EN pin of the PWM controller PU12 is connected with one end of a capacitor PC126 in parallel and then connected with one end of the capacitor PC127, the other end of the capacitor PC126 is connected with a resistor PR86 in series and then connected with the other end of the capacitor PC127, an FB pin of the PWM controller PU12, one end of a resistor PR95, one end of a resistor PR94 and one end of a resistor PR96 respectively, the other end of the resistor PR95 is grounded, the other end of the resistor PR96 is connected with one end of a capacitor PC135, and the other end of the resistor PR94 is connected with one end of a capacitor PC130, one end of a capacitor PC129, one end of a capacitor PC128, one end of a capacitor PC132, one end of a capacitor PC131, one end of an inductor PL5 and a power output end P1V5_ DUAL in parallel and then connected with; the other end of the capacitor PC130, the other end of the capacitor PC129, the other end of the capacitor PC128, the other end of the capacitor PC132 and the other end of the capacitor PC131 are all grounded;
the GND pin of the PWM controller PU12 is grounded, the LGATE pin of the PWM controller PU12 is connected with one end of a resistor PR91 in parallel and then is connected with the G pole of a field-effect tube PQ8, the S pole of the field-effect tube PQ8 is grounded, the D pole of the field-effect tube PQ8 is connected with the S pole of a field-effect tube PQ7 in parallel and then is connected with one end of a resistor PR89, the other end of an inductor PL5, one end of a resistor PR87, one end of a resistor PR88 and the PHASE pin of the PWM controller PU 12; the other end of the resistor PR89 is connected in series with a capacitor PC134 and then is grounded; the other end of the resistor PR87 is connected with one end of a resistor PR85 in parallel and then is connected with the G pole of a field effect transistor PQ7, and the other end of the resistor PR85 is connected with the UGATE pin of the PWM controller PU 12; the other end of the resistor PR88 is connected with a capacitor PC133 in series and then is connected with a BOOT pin of the PWM controller PU 12;
the D electrode of the field-effect tube PQ7 is connected with one end of an inductor PFB12 in parallel and then connected with one end of an inductor PFB13, one end of a capacitor PC121, one end of a capacitor PC122, one end of a capacitor PC123 and one end of a capacitor PC124, the other end of the inductor PFB12 is connected with the other end of an inductor PFB13 in parallel and then connected with a power supply end P5V _ DUAL, and the other end of the capacitor PC121, the other end of the capacitor PC122, the other end of the capacitor PC123 and the other end of the capacitor PC124 are all grounded;
a PGOOD pin of the PWM controller PU12 is connected with a resistor PR93 in series and then is connected with a power output end P1V5_ DUAL, a VOS pin of the PWM controller PU12 is connected with one end of a resistor PR92 and one end of a resistor PR93 in parallel, the other end of the resistor PR92 is grounded, and the other end of the resistor PR93 is connected with the power output end P1V5_ DUAL;
a COMP/EN pin of the PWM controller PU12 is connected with a collector of a triode PQ9, a base of the triode PQ9 is connected with one end of a resistor PR97 in parallel and then connected with the collector of the triode PQ10, the other end of the resistor PR97 is connected with a power supply end P5VSB, a base of the triode PQ10 is connected in series, the resistor PR920 is connected with an external power interface LS7A _ ACPI _ S4N in back, and an emitter of the triode PQ9 and an emitter of the triode PQ10 are both grounded;
the LGATE pin of the PWM controller PU12, the UGATE pin of the PWM controller PU12, the PHASE pin of the PWM controller PU12, and the BOOT pin of the PWM controller PU12 are respectively connected to the power output terminal P1V5_ DUAL _ LGATE _20, the power output terminal P1V5_ DUAL _ UGATE _20, the power output terminal P1V5_ DUAL _ PHASE _20, and the power output terminal P1V5_ DUAL _ BOOT _ 20.
FIG. 3 is a circuit diagram of a VREF power supply according to the present invention; as shown in fig. 3, the circuit structure of the VREF power supply includes: one end of the resistor R195 is connected with a power supply end P1V5_ DUAL, the other end of the resistor R195 is connected with one end of a resistor R197, one end of a capacitor C270, one end of a capacitor C271 and one end of a capacitor C272 after being connected with a power supply output end VREFA in parallel, and the other end of the resistor R197, the other end of the capacitor C270, the other end of the capacitor C271 and the other end of the capacitor C272 are all grounded.
Fig. 4 is a circuit connection diagram of the VTT power supply of the present invention; as shown in fig. 4, the circuit structure of the VTT power supply includes: a Vcntl pin of the voltage regulator PU13 is connected with a power supply end P3V3 and then connected with one end of a capacitor PC136, the other end of the capacitor PC136 is grounded, a VIN pin of the voltage regulator PU13 is connected with a power supply end P1V5_ VDDQ _3A and then connected with one end of a resistor PR98, the other end of the resistor PR98 is connected with one end of a resistor PR99 and one end of a capacitor PC137 and then connected with a REFEN pin of a voltage regulator PU13, and the other end of the resistor PR99 is connected with a GND pin of a voltage regulator PU13 and the other end of the capacitor PC137 and then grounded;
and the VOUT pin of the voltage stabilizer PU13 is connected with one end of a capacitor PC140, one end of a capacitor PC139 and one end of a capacitor PC138 in parallel and then connected with a power output end P0V75_ VTT _3A, and the other end of the capacitor PC140, the other end of the capacitor PC139 and the other end of the capacitor PC138 are grounded.
In this embodiment, the VDD power supply mainly provides power to the chip internal address/control signal interface and the main control logic circuit; the VTT power supply mainly provides power for the bus end, and the voltage value of the VTT power supply is half of VDD; the VREF power supply is a reference voltage and is equal to the voltage value of VTT.
The utility model discloses in, on following DDR3 memory theory of operation's basis, satisfy the smooth mode of being qualified for the next round of competitions of data line on the mainboard through the connection order of adjusting the line is walked to the data bit, in PCB's the line of walking, can carry out the high-speed signal line with fourth layer and sixth layer and walk the line, regard the top layer as low-speed class signal to walk the line.
The utility model discloses having fully considered desktop machine case size, mainboard size, under the condition that will all satisfy, having set up the DRAM in CPU 10's both sides through first DRAM slot 20 and second DRAM slot 30 for high-speed line of walking on the mainboard is no longer intensive, and the practicality is strong.
In the description of the present invention, it is to be understood that the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.
Claims (6)
1. A motherboard memory bank layout structure, comprising: the PCB board, be provided with CPU (10) on the PCB board, its characterized in that: a first memory bank slot (20) and a second memory bank slot (30) are symmetrically arranged on two sides of the CPU (10);
the CPU (10) is connected with a first memory bank slot (20) through an MC0 channel (40), and the CPU (10) is connected with a second memory bank slot (30) through an MC1 channel (50);
the MC0 channel (40) and the MC1 channel (50) have the same structure and respectively comprise a plurality of signal lines, and the signal lines are used for communicating the CPU (10) with the first memory bank slot (20) and communicating the CPU (10) with the second memory bank slot (30); and the reference layer of the signal line is the fifth layer of the PCB.
2. The motherboard memory bank layout structure of claim 1, wherein: further comprising: the power supply module (60) is arranged on the other side of the CPU (10) and is positioned between the first memory bank slot (20) and the second memory bank slot (30);
the power module (60) is electrically connected with the CPU (10), the first memory bank slot (20) and the second memory bank slot (30) through power lines.
3. The motherboard memory bank layout structure of claim 2, wherein: the signal line includes: the circuit comprises a data line, an address line, a bidirectional data strobe signal line, a data mask signal line, a logic BANK signal line, a physical chip selection signal line, a clock differential signal line, a clock enable signal line and a control signal line;
the power cord includes: a VDD power line, a VTT power line and a VREF power line;
the data line, the address line, the bidirectional data strobe signal line, the data mask signal line, the logic BANK signal line, the physical chip selection signal line, the clock differential signal line, the clock enable signal line, the control signal line, the VDD power line, the VTT power line and the VREF power line are respectively and correspondingly electrically connected with the data pin, the address pin, the bidirectional data strobe signal pin, the data mask signal pin, the logic BANK signal pin, the physical chip selection signal pin, the clock differential signal pin, the clock enable signal pin, the control signal pin, the VDD pin, the VTT pin and the VREF pin of the CPU (10).
4. The motherboard memory bank layout structure of claim 1, wherein: the PCB comprises eight layers.
5. The motherboard memory bank layout structure of claim 1, wherein: the first memory bank slot (20) and the second memory bank slot (30) are both DDR3 memory slots.
6. The motherboard memory bank layout structure of claim 1, wherein: the CPU (10) is a Loongson 3A3000 processor.
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| CN202022441718.8U CN212990051U (en) | 2020-10-28 | 2020-10-28 | Mainboard memory bank layout structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113535636A (en) * | 2021-06-30 | 2021-10-22 | 成都中微达信科技有限公司 | Computing device |
| CN113792518A (en) * | 2021-09-27 | 2021-12-14 | 中科可控信息产业有限公司 | PCB layout structure, server mainboard and server |
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2020
- 2020-10-28 CN CN202022441718.8U patent/CN212990051U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113535636A (en) * | 2021-06-30 | 2021-10-22 | 成都中微达信科技有限公司 | Computing device |
| CN113792518A (en) * | 2021-09-27 | 2021-12-14 | 中科可控信息产业有限公司 | PCB layout structure, server mainboard and server |
| CN113792518B (en) * | 2021-09-27 | 2023-12-19 | 中科可控信息产业有限公司 | PCB layout structure, server motherboard and server |
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Address after: 301-310, 3 / F, building 6, Baixin creative industry base, No.5, West Lane 2, Henghe, Tanghuai Park, Taiyuan City, Shanxi Province Patentee after: Baixin Information Technology Co.,Ltd. Address before: 301-310, 3 / F, building 6, Baixin creative industry base, No.5, West Lane 2, Henghe, Tanghuai Park, Taiyuan City, Shanxi Province Patentee before: SHANXI BAIXIN INFORMATION TECHNOLOGY Co.,Ltd. |