517390 五、發明説明（1 ) [發明所屬之技術領域] 本發明有關於GalnP系積層構造體以及使用其製作 之場效電晶體，其中之GalnP系積層構造體是積層在 GaAs單結晶基板之表面上至少具備有：緩衝層；由 GaxIm-xAsiOSXgl)構成之電子行走層；由 GazIm-zPCOS Zg 1)構成之間隔物層；和由Gaylm-YP (OS 1)構成之電子供給層。 [習知之技術] 可以以毫米波帶進行動作之場效電晶體（MESFET)之 一種包含有利用磷化鎵·銦混晶（Gaylm-YP : OS 1) 之GalnP系高電子移動度場效電晶體（簡稱爲TEFGET 、MODFET 等）（參照 IEEE Trans· Electron Devices，517390 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a GalnP-based multilayer structure and a field-effect transistor manufactured by using the same, wherein the GalnP-based multilayer structure is laminated on the surface of a GaAs single crystal substrate It has at least: a buffer layer; an electron walking layer made of GaxIm-xAsiOSXgl); a spacer layer made of GazIm-zPCOS Zg 1); and an electron supply layer made of Gaylm-YP (OS 1). [Known technology] A type of field effect transistor (MESFET) that can operate in the millimeter-wave band. GalnP is a high-electron mobility field-effect transistor that contains a gallium phosphide-indium mixed crystal (Gaylm-YP: OS 1). Crystals (referred to as TEFGET, MODFET, etc.) (refer to IEEE Trans · Electron Devices,
Vol. 37, No. 1 0(1 990)，2141 〜2147 頁）。GalnP 系 MODFET例如在微米波帶區域被利用作爲低雜訊信號 放大元件（參照 IEEE Trans· Electron Devices, Vol. 46， No· 1 (1 999)，48〜54頁）。另外，亦被利用作爲高頻發訊 裝置（參照 IEEE Trans· Electron Devices，Vol. 44，No. 9 (1 997), 1 341〜1 348 頁）。 第4圖是習知之GalnP系TEGFET之剖面構造之槪 略圖。基板90利用以{00 1}結晶面作爲主面之半絕緣性 之砷化鎵（化學式：GaAs)。在基板90之表面上堆積由 高電阻之ΙΠ- V族化合物半導體層構成之緩衝層91。 在緩衝層9 1上堆積由η型之砷化鎵·銦混晶 (GaxInuAs : OS XS 1)構成之電子行走層（通道層）92。 517390 五、發明説明（2 ) 在電子行走層9 2上堆積間隔物層9 3。間隔物層9 3 — 般由未摻雜之GazIm-zP^S ZS 1)構成（參照上述之 IEEE Trans. Electron Devices，Vol· 44,（1997))。在間隔 物層93上堆積由η型之磷化鎵·銦混晶（GaYlm-γΡ : 〇$ Yg 1)構成之電子供給層94。經由故意的添加（摻雜）矽 (Si)等之較難擴散之η型雜質，用來調整電子供給層94 之載子（電子）濃度。在電子供給層94上一般設有由η 型GaAS等構成之接觸層95，用來形成低接觸電阻之 源極電極96和汲極電極97之各個歐姆性電極。在源極 和汲極電極96，97之中間之凹陷構造部，於露出之電 子供給層94之表面，設置肯特基接面型閘極電極98用 來構成 TEGFET910。 在電子行走層92之與間隔物層93 (在未配置有間隔 物層93之情況時爲電子供給層94)接合之接合界面92b 之近傍之區域，儲存供給自電子供給層94之電子作爲 2次元電子。在一般之情況，當電子行走層92和間隔 物層93(或電子供給層94)之接合界面92b之障壁變高 時，可以更有效的儲存發揮高移動度之2次元電子。另 外，電子行走層92通常是由在層厚方向成分爲一定之 GaxIm-xAs構成。銦之成分比最大爲大約0.25(25%)(參 照 Solid— State Electron·，36(9)( 1 993)，1 23 5〜1 237 頁）。 [發明所欲解決之問題] 但是，如同上述之習知之電子行走層92之方式，當 銦成分（ = (1-X))爲大致一定而且最大爲〇·25程度之情況 -4- 517390 五、發明説明（3 ) 時，在與間隔物層93接合之接合界面92b之近傍其障 壁之變高具有一定之限度，因此，在接合界面92b之近 傍區域不能有效的儲存2次元電子。因此，不能提高2 次元電子之移動度，要利用其移動度獲得低雜訊之 GalnP系TEGFET會有困難爲其問題。 本發明之提案針對上述之問題，其目的是提供GalnP 系積層構造體以及使用其所製作之場效電晶體，經由有 效的儲存2次元電子可以用來提高2次元電子之移動度 ，利用該高移動度可以用來形成低雜訊之裝置。 [解決問題之手段] 用以達成上述目的之本發明之申請專利範圍第1項 是一種GalnP系積層構造體，積層在GaAs單結晶基板 之表面上者至少具備有：緩衝層；由GaxInuAs(〇SX € 1)構成之電子行走層；由GazIni_zP(〇S ZS 1)構成之 間隔物層；和由GaYlm-YPWS 1)構成之電子供給層 •，其特徵是：該電子行走層包含有成分梯度區域’隨著 朝向電子供給層側使銦成分比（1-X)增加。 另外，本發明之申請專利範圍第2項是在申請專利 範圍第1項之構造中，該成分梯度區域使銦成分比 (H)連續的或不連續的變化。 另外，本發明之申請專利範圍第3項是在申請專利 範圍第1或2項之構造中，使該銦成分比（卜x)在電子 供給層側之界面爲〇.3〇以上〇.50以下。 另外，本發明之申請專利範圍第4項是在申請專利 517390 五、發明説明（4 ) 範圍第1至3項之任一項之構造中，使該電子行走層之 層厚爲1奈米以上5奈米以下。 另外，本發明之申請專利範圍第5項是在申請專利 範圍第Γ至4項之任一項之構造中，使該電子行走層是 由添加有硼（元素符號：B)之η型GaxIn】-XAs(0$ XS 1) 構成之層。 另外，本發明之申請專利範圍第6項是在申請專利 範圍第1至5項之任一項之構造中，使該間隔物層是由 GazIm-zPiOS ZS1)構成之層，包含有成分梯度區域隨 著朝向電子供給層側使鎵成分比減小。 本發明之申請專利範圍第7項是在申請專利範圍第1 至6項之任一項之構造中，使其未具備該間隔物層。 另外，本發明之申請專利範圍第8項是一種場效電晶 體，其特徵是使用該申請專利範圍第1至7項之任一項 之GalnP系積層構造體製作。 [發明之實施例] 下面將根據圖面用來詳細的說明本發明之實施例。 第1圖是本發明之GalnP系積層構造體之說明圖， (a)槪略的表示GalnP系積層構造體之剖面，（b)，（〇， (d)表示電子行走層之銦之成分梯度。在該圖中，本發 明之GalnP系積層構造體1，於GaAs單結晶基板10上 積層的形成有：緩衝層11 ;由GaxInuAWOiXg 1)構 成之電子行走層12;由GazIni_zP(〇$ZSl)構成之間隔 物層13 ;和由GaYluYPCO^ 1)構成之電子供給層 -6- 517390 五、發明説明（5 ) 14。另外，該GalnP系積層構造體1在其電子行走層 12包含有成分梯度區域，所具有之梯度是隨著朝向與 間隔物層1 3側接合之接合界面1 2b，層厚增加時銦成 分比（1-X)就增加。 例如，在（b)中，從與緩衝層11接合之接合界面12a 朝向與間隔物層1 3接合之接合界面1 2b，當層厚增加 時銦成分比（ = (1-X))就直線式的增加。另外，在（c)中， 從接合界面1 2a起至指定之層厚，銦成分比保持一定， 然後在層厚之增加方向，至接合界面1 2b成爲直線式的 增加。另外，在（d)中，從接合界面12a朝向接合界面 1 2b，在層厚之增加方向，銦成分比成爲不連續的增加 。例如從與緩衝層1 1接合之接合界面1 2a到層厚爲 7 n m之區域，銦成分比爲大約〇 . 1 8，在其次之到2 n m 層厚之區域，銦成分比大約0·25，再其次之到與間隔 物層13接合之接合界面12b之2nm之層厚之區域，銦 成分比爲〇·30，使成分比不連續的增加。 另外，在本發明之實施例中，在電子行走層1 2之與 間隔物層1 3接合之接合界面1 2b，使其銦成分比成爲 0 · 3 0以上0.5 0以下。 在此處當以Ga成分比爲0.51之Ga〇.51In().49P構成間 隔物層1 3時，算出之間隔物層1 3之禁止帶幅大約爲 1.88eV(參照赤崎勇編著，「III— V族化合物半導體」 (培風館股份公司，1 994年5月20日發行初版），（8 7 頁）。另外一方面，當以接合界面12b之銦成分比爲 517390 五、發明説明（6 ) 0.30之Gao.7oIno.3oAs構成電子行走層12時，其室溫時 之禁止帶幅爲大約1 .01電子伏特（eV)(參照上述之「III 一 V族化合物半導體」）。因此，電子行走層〗2和間隔 物層13之間禁止帶幅之差異變成爲大約〇.87eV。另外 ，當在接合界面12b之電子行走層12之銦成分比爲 〇·30以上時’可以使電子行走層12和間隔物層13之 禁止帶幅之差異不會如習知者的擴大，在該電子行走層 1 2之接合界面1 2 b側，可以有效的儲存2次元電子爲 其優點。 另外一方面，當極端的提高銦成分比時，銦成分之 不均一性會變爲顯著，不利於電子行走層1 2之表面之 平坦性。因此，不能形成與間隔物層1 3接合之平坦接 合界面12b’要獲得穩定之局移動度變爲困難。因此， 在電子行走層1 2之與間隔物層1 3接合之接合界面1 2 b 之銦成分比最好爲0.5以下。 但是，形成間隔物層1 3之GazIr^.zP，或形成電子供 給層14之GaYln^yP之禁止帶幅隨著鎵成分比之增大 而變大（參照上述之「III 一 V族化合物半導體」，187 頁）’形成電子行走層12之GaxIni_xAs之禁止帶幅隨 著銦成分比之增大而變小。因此，間隔物層1 3朝向接 合界面12b使鎵成分比變大，電子行走層12朝向接合 界面1 2 b使銦成分比變小，可以使電子行走層1 2和間 隔物層1 3之間之禁止帶幅之差異變成更大，可以使兩 層間之障壁變成更高。亦即，可以有效的將2次元電子 517390 五、發明説明（7 ) 之儲存局限在電子行走層12之內部，可以形成高電子 移動度之優良之異接面構造。 另外，在本發明之實施例中，使設在電子行走層1 2 之內部之成分梯’度區域之層厚成爲1奈米（nm)以上5nm 以F。當成分梯度區域之厚度小於1 n m時，不能充分 的局限2次電子之儲存。另外，當使銦成分變大之成分 梯度區域之層厚超過5 nm厚時，與構成上層之間隔物 層1 3之G az Iη ! ·zP之晶格不匹配性會增大，會阻礙優 質之間隔物層1 3之形成，所以不好。當使構成成分梯 度區域之GaxInuAs之銦成分比（ = (1-X))變大時，成分 梯度區域之層厚成爲薄層用來獲得良好之結果。另外， 成分梯度區域最好由低載子濃度之高純度之η型 GaxIn^xAs層構成。載子濃度較好爲5xl016cm_3以下 ，更好爲lxl 016cm_3以下。載子濃度之測定可以利用 通常之霍爾（Hell)效應測定法或電容—電壓（C — V)法等。 另外，在本發明之實施例中，使用添加有硼（元素符 號：B)之η型GaxIn^As所形成之層用來構成電子行 走層1 2。經由摻雜硼，可以減小電子行走層1 2之載子 濃度。特別是當銦成分比變大，硼之摻雜量變大時，可 以有效的減小載子濃度。例如，在未摻雜狀態之由 4xl016cm'3之GaxInuAs構成之電子行走層12之載子 濃度，當與摻雜硼者比較時，減小大約1位數（1 〇倍） 以上。利用此種方式，可以減小被儲存在電子行走層 1 2之內部之2次元電子被散亂之影響。因此，高電子 -9- 517390 五、發明説明（8 ) 移動度變爲顯著，可以提供互導（gm)特性優良之GalnP 系高電子移動度電晶體。 包含成分梯度區域之摻雜硼之電子行走層1 2可以經 由成膜GaxIn^As層和摻雜硼而形成。作爲硼之摻雜 源者例如可以利用三甲基硼（.（CH3)3B)或三乙基硼 ((C2H5)3B)。較好之方式是將硼摻雜成爲硼之原子濃度 是lxlO16個原子/cm3以上和lxlO18個原子/cm3以下 。另外，最好使硼之摻雜之施加成爲大致上超過 GaxIni_xAs層之載子濃度之原子濃度。利用硼摻雜源對 成長反應成長系統供給之供給量，可以用來調整 GaxIni_xAs層內部之硼原子濃度。另外，例如利用一般 之2次離子質量分析法（SIMS)可以計測GaxIni-XAs層 之內部之硼之原子濃度。 在此種方式之本發明之實施例中，因爲在電子行走 層1 2設有成分梯度區域，所具有之梯度是朝向與間隔 物層1 3側接合之接合界面1 2b，在層厚之增加方向使 銦成分比增加，所以可以使電子行走層1 2和間隔物層 1 3之間之禁止帶幅之差異變大，可以使兩層間之障壁 變成更高。因此，在電子行走層1 2之內部，可以有效 的儲存供給自電子供給層1 4之電子作爲2次元電子， 可以實現高電子移動度，因此，可以提供互導（gm)特性 優良之場效電晶體。 另外，因爲使電子行走層1 2之與間隔物層1 3接合 之接合界面12b之銦成分比成爲0.30以上0.50以下， -10- 517390 五、發明説明（9 ) 所以在電子行走層1 2之內部可以有效的儲存2次元電 子，和可以確實的抑制當銦成分比變成太高時由於損及 電子行走層1 2表面之平坦性而發生之間隔物層1 3或電 子供給層1 4之結晶性之劣化，因此，可以確保高電子 移動度用來使電子行走層12之構造成爲最佳。 另外，因爲設在電子行走層1 2之內部之成分梯度區 域之層厚爲Inm以上5nm以下，所以可以確保電子行 走層12之層厚，將2次元電子之儲存充分的局限在層 內，和可以防止太厚時發生之與上層之晶格不匹配，可 以確實的形成結晶性優良之間隔物層1 3和電子供給層 1 4 〇 另外，因爲在電子行走層1 2摻雜硼，所以可以使電 子行走層1 2之載子濃度減小，可以減小儲存在電子行 走層1 2之內部之2次元電子被散亂之影響。因此’利 用此點亦可以實現高電子移動度，可以提供互導（g。特 性優良之場效電晶體。 另外，因爲電子行走層12由包含有成分梯度區域之 GazIn i _ZP (0 $ ZS 1)層構成，所具有之梯度是朝向與間 隔物層1 3側接合之接合界面1 2b，在層厚之增加方向 使銦成分比增加，和從間隔物層1 3與電子行走層1 2接 合之接合界面12b朝向電子供給層14側’在層厚之增 加方向使鎵成分比減小，所以可以使兩層1 2，1 3間之 障壁更進一層的確實變高，因此，可以將2次元電子有 效的儲存在電子行走層1 2之內部，可以顯現高電子移 -11 - 517390 五、發明説明（1G ) 動度。 下面將以更具體之實施例用來說明本發明之GalnP 系積層構造體和使用其製作之場效電晶體。 [實施例] (第1實施例） 第2圖是第1實施例之TEGFET之剖面槪略圖。 在本實施例中，用以詳細說明本發明之實例是構建 成爲GalnP系高電子移動度場效電晶體（TEGFET)其中 具備設有成分梯度區域之電子行走層。 TEGFET用之外延積層構造體1A以未摻雜半絕緣性 之（100)2°(off)GaAs單結晶構建成爲基板100。基板 100之GaAs單結晶之比電阻在室溫大約爲3χ107Ω · cm。 在直徑大約100mm之基板100之表面上，堆積用以 構成緩衝層101之AlcGauAs/GaAs系超晶格構造。該 超晶格構造體之構成包含有使鋁成分比（ = C)成爲0.30 之未摻雜之Alo.3oGao.7oAs層和摻雜之p型之GaAs層 。Al〇.3〇Ga().7()As層之載子濃度大約爲lxl014cnT3，層 厚爲45nm。p型GaAs層之載子濃度爲7xl013crrT3， 層厚爲50nm。Al〇.3()Ga().7()As層和p型GaAs層之積層 週期數爲5個週期。Alo.3oGao.7oAs層和p型GaAs層均 爲依照使用三甲基鎵（（CH3)3Ga)/三甲基鉛（（CH3)3A1)/氫 化砷（AsH3)/氫（H2)反應系之減壓MOCVD法，以640°C 成膜者。成膜時之壓力大約爲1.3x1 04巴斯卡（Pa)。載 運（輸送）氣體使用氫氣。 -12- 517390 五、發明説明（n ) 在緩衝層101上，依照利用（CH3)3Ga/環戊二烯基銦 (C5H5In)/AsH3/H2反應系之減壓MOCVD法，積層摻雜 之η型Ga〇.8〇In〇.2()As層作爲用以構成電子行走層（通道 層02之第1構成層102-1。第1層102-1之層厚爲大 約9nm。在第1層102-1上積層使銦成分比成爲0.3 0 之η型GamInmAs層作爲第2構成層102-2。第2 構成層1 〇 2 - 2之層厚爲大約2 n m。利用第1和第2構成 層102-1，102-2用來構成銦成分具有梯度之電子行走 層102。構成電子行走層102之第1和第2構成層102-1 ，102-2之載子濃度均爲3xl015cnT3。 在GalnAs成分梯度層102上，依照利用 (CH3)3Ga/C5H5In/PH3/H2 反應系之減壓 MOCVD 法，積 層由未摻雜之η型Ga〇.51In().49P構成之間隔物層103。 在間隔物層103之上，依照利用 (CH3)3Ga/C5H5In/PH3/H2 反應系之減壓 MOCVD 法，積 層由摻雜有矽（Si)之η型GaG.51In().49P所構成之電子供 給層1〇4。Si之摻雜源使用氫—乙硅烷（Si2H6)(濃度10 體積ppm)混合氣體。成膜時之壓力爲大約1.3 xlO4帕 斯卡（Pa)。電子供給層104之載子濃度爲2xl018cnT3， 層厚爲25nm。 在電子供給層104之表面上，利用（CH3)3Ga/AsH3/H2 反應系，積層由摻雜Si之η型GaAs構成之接觸層105 。S i之摻雑源使用上述之氫-乙桂院混合氣體。接觸 層105之載子濃度爲2xl018cnr3，層厚爲大約50nm。 -13- 517390 五、發明説明（12 ) 另外，使由ΟαγΙη^γΡ構成之電子供給層104之鎵成分 比成爲0.51，因爲調整成爲與積層在其上之GaAs所構 成之接觸層1 05之晶格間隔成爲大致相同之方式，所以 雙方具有良好之匹配性。 利用上述之方式，在完成成爲積層構造體100A之構 成層101〜105之外延成長後，在包含氫化砷（AsH3)之環 境氣體內，降溫到大約500°C，然後在氫氣之環境氣體 內冷卻到室溫。 在最表層之η型GaAs接觸層1 05之表面，形成由銦 •錫（In · Sn)合金構成之歐姆性電極。其次，依照通常 之霍爾（Hall)效應測定法，測定在電子行走層102行走 之2次元電子之電子移動度。室溫（大約3 00克耳文 (K))之片載子濃度（ns)爲大約1.8xl012cm_2,電子移動 度（// r τ)變成爲大約5 7 0 0 c m 2 / V · S。亦即，習知之情況 是GaG.80Ino.20As層未包含有成分梯度區域，銦成分比 固定爲0.20，當以此構成電子行走層之情況時，其電 子移動度U rt)爲大約3 5 00 cm2/V · s，當與此比較時 ，可以看出本實施例具有顯著之改善。 利用習知之光刻技術之圖型製作法，將最表層之η 型GaAs接觸層105之表面加工成爲凹陷（recess)狀。 在殘留爲台面（mesa)狀之η型GaAs接觸層105上，形 成源極電極1 〇 6和汲極電極1 0 7。源極和汲極之各個歐 姆性電極1 〇 6，1 0 7由金•鎳（A u 9 3重量％ · G e 7重量 %) •鎳（Ni) ·金（Αι〇之疊層構造構成。源極電極106和 -14- 517390 13 五、發明説明（） 汲極電極107之間隔爲ΙΟμηι。在凹陷部露出之 Ga〇.51In().49P電子供給層1〇4之表面，形成下層爲鈦 (Ti)，上層爲鋁（A1)之疊層構造之肖特基（Schottky)接面 型閘極電極1 08。閘極電極1 08之閘極長度爲大約1 μιη。 評估以此方式構成之GalnP系TEGFET1 10之直流 (DC)特性。使汲極電壓成爲2伏特（V)時之飽和汲極電 流（Idss)爲大約68毫安培（mA)。當使汲極電壓在0V至 5 V之間掃描時，大致未觀測到在汲極電流上有迴環（滯 後）。使源極/汲極間電壓成爲2.0V時所計測到之室溫 之互導（gm)高至200±5毫西門子（Siemens)(mS)/mm， 而且變爲均一。亦即，習知之情況是GaG.8()In().2()As層 未包含有成分梯度區域，銦成分比固定爲0.20，當以 此構成電子行走層之情況時，其互導（gm)爲大約150毫 西門子（mS)/mm，當與此比較時，可看出本實施例具有 顯著之改善。 另外，當用來使緩衝層1 0 1之表面露出之間隔成爲 ΙΟΟμιη時，在Au · Ge歐姆性電極間流動之洩漏電流於 40V時小於1 μΑ，顯示具有高耐壓性。因此，閘極夾止 電壓變成爲大約-〇.9V±0.03V，可以提供具有均一之臨 限値之GalnP系TEGFET。 (第2實施例） 第3圖是第2實施例之TEGFET之剖面槪略圖。在 與第1實施例相同之構成元件，將第1實施例之符號之 第1位數之數字1改寫成爲2，而其說明刖加以省略。 -15- 517390 五、發明説明（14 ) 本實施例之電子行走層202被構建成爲具有Gaxln^ xAs成分梯度區域，在與緩衝層201接合之接合界面 2〇2a，使銦成分比成爲0.20，在與間隔物層203接合 之接合界面202b，使銦成分比成爲大約0.35。電子行 走層202之層厚爲大約8nm。銦成分比之梯度是隨著層 厚之增加，使銦源（三甲基銦：（CH3)3In)對用以供給到 MOCVD反應系之鎵源之比率（=((：113)3111/((：1*13)3〇3)經常 直線式的增加。電子行走層202之載子濃度被設定爲大 約 4xl016cm_3。 對於積層構造體200A，依照一般之霍爾（Hall)效應測 定法所測定到之在室溫（大約300K)之片（sheet)載子濃 度（ns)大約爲1 .7x1 012cm_2，平均之電子移動度（// RT) 爲大約6000cm2/V · s，因此顯現具有高電子移動度。 另外，在利用與第1實施例相同之方法構成之GalnP 系TEGFET210中，當使汲極電壓成爲2.0V時，在室溫 之互導（gm)變高至210±5毫西門子（mS)/mm，可以提供 高性倉g之TEGFET。 (第3實施例） 在本實施例中，以具備有摻雜硼（B)之GaxIni_xAs電 子行走層之GalnP系TEGFET爲例，用來具體的說明 本發明，其中具有與第2實施例所述者相同之銦成分之 梯度。本實施例之TEGFET與第2實施例比較時，只 有GaxIm-xAs電子行走層不同，所以利用第3圖用來 進行說明。 -16- 517390 五、發明説明（15 ) 在本第3實施例中，於構成電子行走層202之 GaxIimAs成分梯度區域之成長時，摻雜硼。硼之摻雜 源使用市面上所販賣之電子工業用之三乙基硼 ((C2H5)3B)。三乙基硼對MOCVD反應系之摻雜量，針 對使未摻雜狀態之η型GaxIn^As成分梯度層之載子 濃度成爲大約4x10 16cnT3，所以在層內設定成爲大約 4xlOI7cnT3之硼原子濃度。GaxIm-xAs電子行走層202 之載子濃度由於硼之摻雜成爲小於大約5x10 15cnT3。 依照一般之霍爾（Hall)效應測定法所測定到之在室溫 (大約3 00K)之片（sheet)載子濃度（ns)爲大約1.6x 1012cnT2,平均之電子移動度（//RT)變成爲大約 6400cm2/V · s，依照此種方式，經由在電子行走層202 摻雜硼，當與第2實施例之情況進行比較時，可以產生 更高之電子移動度。汲極電壓被設定在2V時之飽和源 極·汲極電流變成爲大約70mA，和在汲極電流大致未 發現有滯後（迴環）。另外，當源極/汲極間電壓爲2.0V 時，在室溫之互導（gm)變成高達大約250毫西門子 (m S )/mm 〇 [發明之效果] 本發明因爲以上述方式構成，所以具有下面所說明 之效果。 在本發明之申請專利範圍第1或第2項中，因爲在 電子行走層設有成分梯度區域，所具有之梯度是隨著朝 向與電子供給層側接合之接合界面，在層厚之增加方向 -17- 517390 五、發明説明（16 ) 使銦成分比增加，所以可以使電子行走層和電子供給層 之間之接合界面之禁止帶幅之差異變成更大，可以使包 夾接合界面之兩層間之障壁變成更高。因此，在電子行 走層之內部，可以有效的儲存供給自電子供給層之電子 作爲2次元電子，可以實現高電子移動度，因此，可以 提供互導特性優良之場效電晶體。 另外，在本發明之申請專利範圍第3項中，因爲使 電子行走層和電子供給層之接合界面之銦成分比成爲 0.3 0以上〇 · 5 0以下，所以在電子行走層之內部可以有 效的儲存2次元電子，和可以確實的抑制當銦成分比太 高時有損電子行走層表面之平坦性而發生之間隔物層或 電子供給層之結晶性之劣化。 另外，在本發明之申請專利範圍第4項中，因爲使 電子行走層之層厚成爲Inm以上5nm以下，所以可以 確保電子行走層之層厚，將2次元電子之儲存充分局限 在層內，和可以防止太厚之情況時所發生之與上層之晶 格不匹配，可以確實的形成結晶性優良之間隔物層和電 子供給層。 另外，在本發明之申請專利範圍第5項中，因爲在 電子行走層摻雜硼，所以可以使電子行走層之載子濃度 減小，可以減小電子行走層之內部所儲存之2次元電子 之被散亂之影響。因此，利用此點亦可以實現高電子移 動度，可以提供互導特性優良之場效電晶體。 在本發明之申請專利範圍第6項中，因爲間隔物層 -18- 517390 五、發明説明（17 ) 由含有成分梯度區域之GaxIm-xPiOS XS 1)層構成，所 具有之梯度是朝向與電子供給層接合之接合界面，在層 厚之增加方向使鎵成分比減小，所以電子行走層和間隔 物層間之障壁可以更進一層的確實變高，因此，在電子 行走層之內部可以有效的儲存2次元電子，可以顯現高 電子移動度。 [圖示之簡單說明] 第1圖是本發明之GalnP系積層構造體之說明圖， U)槪略的表示GalnP系積層構造體之剖面，（b)，（c)， (d)表示電子行走層之銦之成分梯度。 第2圖表示第1實施例之TEGFET之剖面槪略圖。 第3圖表示第2實施例之TEGFET之剖面槪略圖。 第4圖是習知之GalnP系TEGFET之剖面構造之槪 略圖。 [符號說明] 1.....GalnP系積層構造體 10· · · · •單結晶基板 11·· —— •緩衝層 12 · · · · •電子行走層 12a· · · ••接合界面 12b · · · ••接合界面 13 · · ·. •間隔物層 14 · · · · •電子供給層 100 · · · .•基板 -19- 517390 五、發明説明（18 ) 100A · • · ••積層構造體 101 · · • · •緩衝層 102 · · • · •電子行走層 102-1 · • · ••構成層 102-2 · • · · •構成層 103 · · • ••間隔物層 104 · · •·•電子供給層 105 · · •·.接觸層 106 · · •·•源極電極 107 · · •••汲極電極 108 · · • · ·閘極電極 200A · • · ••積層構造體 20 \ · · • · •緩衝層 202 · · • · •電子行走層 202a · • · ••接合界面 202b · • ·..接合界面 203 · · • ••間隔物層 -20-Vol. 37, No. 1 0 (1 990), pages 2141 to 2147). GalnP-based MODFETs are used, for example, as low-noise signal amplifiers in the micro-wave band region (see IEEE Trans. Electron Devices, Vol. 46, No. 1 (1 999), pages 48 to 54). It is also used as a high-frequency transmission device (see IEEE Trans · Electron Devices, Vol. 44, No. 9 (1 997), 1 341 ~ 1 348). Fig. 4 is a schematic diagram of a cross-sectional structure of a conventional GalnP-based TEGFET. The substrate 90 uses semi-insulating gallium arsenide (chemical formula: GaAs) having a {00 1} crystal plane as a main surface. A buffer layer 91 composed of a high-resistance group III-V compound semiconductor layer is deposited on the surface of the substrate 90. An electron walking layer (channel layer) 92 composed of n-type gallium arsenide-indium mixed crystal (GaxInuAs: OS XS 1) is deposited on the buffer layer 91. 517390 V. Description of the invention (2) A spacer layer 93 is stacked on the electron walking layer 92. The spacer layer 9 3 is generally composed of undoped GazIm-zP ^ S ZS 1) (refer to the aforementioned IEEE Trans. Electron Devices, Vol. 44, (1997)). On the spacer layer 93, an electron supply layer 94 composed of an n-type gallium phosphide-indium mixed crystal (GaYlm-γP: 0 $ Yg 1) is deposited. The intentionally added (doped) n-type impurity such as silicon (Si) is used to adjust the carrier (electron) concentration of the electron supply layer 94. A contact layer 95 composed of n-type GaAS or the like is generally provided on the electron supply layer 94, and is used to form each of the ohmic electrodes of the source electrode 96 and the drain electrode 97 with low contact resistance. In the recessed structure between the source and drain electrodes 96 and 97, a Kentky junction gate electrode 98 is provided on the surface of the exposed electron supply layer 94 to form a TEGFET910. In the area near the bonding interface 92b where the electron walking layer 92 is bonded to the spacer layer 93 (the electron supply layer 94 when the spacer layer 93 is not arranged), the electrons supplied from the electron supply layer 94 are stored as 2 Dimensional electronics. In general, when the barriers at the joint interface 92b of the electron walking layer 92 and the spacer layer 93 (or the electron supply layer 94) become high, the two-dimensional electrons exhibiting high mobility can be stored more efficiently. In addition, the electron walking layer 92 is usually made of GaxIm-xAs whose composition is constant in the layer thickness direction. The maximum indium composition ratio is approximately 0.25 (25%) (refer to Solid State Electron ·, 36 (9) (1 993), 1 23 5 ~ 1 237). [Problems to be Solved by the Invention] However, as in the conventional method of the electronic walking layer 92 described above, when the indium composition (= (1-X)) is approximately constant and the maximum value is about 0.25 −4 517390 5 2. Description of the invention (3) In the vicinity of the bonding interface 92b that is bonded to the spacer layer 93, the height of the barriers has a certain limit. Therefore, the two-dimensional electrons cannot be effectively stored in the vicinity of the bonding interface 92b. Therefore, the mobility of the two-dimensional electrons cannot be improved, and it is difficult to use the mobility to obtain GalnP-based TEGFETs with low noise. The proposal of the present invention is directed to the above-mentioned problems, and the purpose thereof is to provide a GalnP-based multilayer structure and a field effect transistor manufactured using the same. By effectively storing the two-dimensional electrons, it can be used to improve the mobility of the two-dimensional electrons. Mobility can be used to form low noise devices. [Means for Solving the Problem] The first item of the scope of patent application of the present invention to achieve the above-mentioned object is a GalnP-based laminated structure, which is laminated on the surface of a GaAs single crystal substrate and has at least: a buffer layer; and a GaxInuAs (〇 SX € 1) an electron walking layer; a spacer layer consisting of GazIni_zP (〇S ZS 1); and an electron supply layer consisting of GaYlm-YPWS 1) • characterized in that the electron walking layer contains a composition gradient The region 'increases the indium composition ratio (1-X) toward the electron supply layer side. In addition, the second scope of the patent application of the present invention is the structure of the first scope of the patent application, in which the composition gradient region changes the indium composition ratio (H) continuously or discontinuously. In addition, the third item of the patent application scope of the present invention is that in the structure of the first or second patent application scope, the interface of the indium composition ratio (Bu x) on the electron supply layer side is 0.30 or more and 0.50 or less. the following. In addition, the fourth item of the scope of patent application of the present invention is in the structure of any one of the first to third aspects of the scope of application patent 517390 5. The invention description (4), the layer thickness of the electronic walking layer is 1 nm or more 5 nanometers or less. In addition, the fifth aspect of the patent application scope of the present invention is that in the structure of any one of the first to fourth patent scopes, the electron walking layer is made of η-type GaxIn with boron (element symbol: B)] -XAs (0 $ XS 1). In addition, the sixth aspect of the patent application scope of the present invention is a structure in which the spacer layer is composed of GazIm-zPiOS ZS1) in the structure of any one of the first to fifth patent scopes, and includes a component gradient region. The gallium composition ratio decreases toward the electron supply layer side. Item 7 of the scope of patent application of the present invention is such that the spacer layer is not provided in the structure of any one of claims 1 to 6 of the scope of patent application. In addition, item 8 of the scope of patent application of the present invention is a field-effect electric crystal, which is characterized in that it is manufactured using a GalnP-based multilayer structure of any one of the scope of patent applications 1 to 7. [Embodiment of the Invention] The embodiment of the present invention will be described in detail below with reference to the drawings. Fig. 1 is an explanatory diagram of the GalnP-based laminated structure of the present invention. (A) The cross-section of the GalnP-based laminated structure is schematically shown. (B), (0, (d) represents the indium composition gradient of the electron walking layer. In the figure, the GalnP-based multilayer structure 1 of the present invention is formed on a GaAs single crystal substrate 10 by: a buffer layer 11; an electronic walking layer 12 composed of GaxInuAWOiXg 1); and GazIni_zP (〇 $ ZSl) The spacer layer 13 is composed of; and the electron supply layer composed of GaYluYPCO ^ 1) -6- 517390 5. Description of the invention (5) 14. In addition, the GalnP-based multilayer structure 1 includes a composition gradient region in the electron walking layer 12 thereof, and the gradient has an indium composition ratio as the layer thickness increases as it goes toward the bonding interface 1 2b that is bonded to the spacer layer 13 side. (1-X) increases. For example, in (b), from the bonding interface 12a that is bonded to the buffer layer 11 to the bonding interface 12b that is bonded to the spacer layer 13, the indium composition ratio (= (1-X)) becomes straight as the layer thickness increases. Increase. In addition, in (c), the indium composition ratio is kept constant from the bonding interface 12a to a specified layer thickness, and then increases in a linear manner until the bonding interface 12b is increased in the direction of increasing the layer thickness. In addition, in (d), from the bonding interface 12a toward the bonding interface 12b, the indium composition ratio increases discontinuously in the direction of increasing the layer thickness. For example, from the bonding interface 12a to the buffer layer 11 to the region with a layer thickness of 7 nm, the indium composition ratio is about 0.18, and in the region next to the 2 nm layer thickness, the indium composition ratio is about 0.25 Then, the area of the 2 nm layer thickness of the bonding interface 12b to be bonded to the spacer layer 13 is followed by an indium composition ratio of 0.30, which increases the composition ratio discontinuously. In addition, in the embodiment of the present invention, the indium composition ratio at the junction interface 12b where the electron walking layer 12 is joined to the spacer layer 13 is set to 0. 3 0 or more and 0.5 0 or less. Here, when the spacer layer 13 is composed of Ga.51In (). 49P with a Ga composition ratio of 0.51, the calculated forbidden band width of the spacer layer 13 is approximately 1.88 eV (referred to by Akasaki, "III — Group V compound semiconductors ”(Peifeng Pavilion Co., Ltd., first edition issued on May 20, 1994), (87 pages). On the other hand, when the indium composition ratio of the joint interface 12b is 517390 V. Description of the invention (6) When Gao.7oIno.3oAs of 0.30 constitutes the electronic walking layer 12, the forbidden band at room temperature is about 1.01 electron volts (eV) (refer to the above-mentioned "III-V compound semiconductor"). Therefore, electronic walking The difference in forbidden band width between the layer 2 and the spacer layer 13 becomes approximately 0.87 eV. In addition, when the indium composition ratio of the electron walking layer 12 at the bonding interface 12b is 0.30 or more, the electron walking layer can be made The difference between the forbidden band width of 12 and the spacer layer 13 will not be enlarged as known, and on the joint interface 1 2 b side of the electron walking layer 12, it is possible to effectively store 2D electrons as its advantage. When the indium composition ratio is extremely increased, the heterogeneity of the indium composition will be It becomes significant, which is not conducive to the flatness of the surface of the electron walking layer 12. Therefore, it is difficult to obtain a stable local mobility of the flat bonding interface 12b 'that cannot be joined with the spacer layer 13. Therefore, in the electron walking The indium composition ratio of the bonding interface 1 2 b of the layer 12 to the spacer layer 13 is preferably 0.5 or less. However, GazIr ^ .zP forming the spacer layer 13 or GaYln ^ forming the electron supply layer 14 The forbidden band of yP becomes larger as the gallium composition ratio increases (refer to the above-mentioned "Group III-V compound semiconductor", page 187). The forbidden band of GaxIni_xAs forming the electronic walking layer 12 varies with the indium composition ratio. It becomes larger and becomes smaller. Therefore, the spacer layer 13 faces the bonding interface 12b to increase the gallium composition ratio, and the electron walking layer 12 faces the bonding interface 12b to reduce the indium composition ratio, so that the electron walking layer 12 and the spacer can be made smaller. The difference in the forbidden band width between the physical layers 1 and 3 becomes larger, which can make the barrier between the two layers higher. That is, it can effectively limit the storage of the two-dimensional electron 517390 V. The invention description (7) is limited to electronic walking Inside layer 12, can be formed Excellent interface structure of the electron mobility. In addition, in the embodiment of the present invention, the layer thickness of the component gradient region provided inside the electronic walking layer 12 is set to be 1 nm (nm) or more and 5 nm or more. F. When the thickness of the component gradient region is less than 1 nm, the storage of secondary electrons cannot be sufficiently limited. In addition, when the layer thickness of the component gradient region that makes the indium composition larger than 5 nm, it becomes a spacer with the upper layer. The lattice mismatch of G az Iη! · ZP of layer 13 will increase, which will hinder the formation of high-quality spacer layer 13 and is not good. When the indium composition ratio (= (1-X)) of GaxInuAs constituting the component gradient region is made larger, the layer thickness in the component gradient region becomes a thin layer to obtain a good result. The composition gradient region is preferably composed of a high-purity n-type GaxIn ^ xAs layer with a low carrier concentration. The carrier concentration is preferably 5xl016cm_3 or less, and more preferably lxl 016cm_3 or less. The carrier concentration can be measured by the usual Hall effect method or the capacitance-voltage (C-V) method. In addition, in the embodiment of the present invention, a layer formed of n-type GaxIn ^ As to which boron (element symbol: B) is added is used to constitute the electronic traveling layer 12. By doping boron, the carrier concentration of the electron walking layer 12 can be reduced. Especially when the indium composition ratio becomes larger and the doping amount of boron becomes larger, the carrier concentration can be effectively reduced. For example, in the undoped state, the carrier concentration of the electron walking layer 12 composed of 4x1016 cm'3 of GaxInuAs is reduced by about one digit (10 times) or more when compared with the boron-doped one. In this way, the influence of the two-dimensional electrons stored in the electron walking layer 12 can be reduced. Therefore, high electron -9- 517390 V. Description of the invention (8) The mobility becomes significant, and it can provide a GalnP-based high electron mobility transistor with excellent transconductance (gm) characteristics. A boron-doped electron walking layer 12 including a composition gradient region can be formed by forming a GaxIn ^ As layer and doping boron. As the doping source of boron, for example, trimethylboron (. (CH3) 3B) or triethylboron ((C2H5) 3B) can be used. A preferred method is to dope boron to the atomic concentration of boron of lxlO16 atoms / cm3 or more and lxlO18 atoms / cm3 or less. In addition, it is preferable that the doping of boron is performed at an atomic concentration that substantially exceeds the carrier concentration of the GaxIni_xAs layer. The amount of boron doped source supplied to the growth reaction growth system can be used to adjust the boron atom concentration inside the GaxIni_xAs layer. In addition, the atomic concentration of boron in the GaxIni-XAs layer can be measured using a general secondary ion mass spectrometry (SIMS). In the embodiment of the present invention in this manner, since the compositional gradient region is provided in the electron walking layer 12, the gradient is toward the bonding interface 12b which is bonded to the spacer layer 13 side, and the layer thickness increases. The direction increases the indium composition ratio, so the difference in the forbidden band between the electron walking layer 12 and the spacer layer 13 can be made larger, and the barrier between the two layers can be made higher. Therefore, in the electron walking layer 12, electrons supplied from the electron supply layer 14 can be efficiently stored as two-dimensional electrons, and a high electron mobility can be achieved. Therefore, a field effect with excellent cross-conductance (gm) characteristics can be provided. Transistor. In addition, since the indium composition ratio of the bonding interface 12b of the electronic walking layer 12 and the spacer layer 13 is 0.30 or more and 0.50 or less, -10- 517390 V. Description of the invention (9) The inside can effectively store two-dimensional electrons, and can reliably prevent the crystals of the spacer layer 13 or the electron supply layer 14 from occurring when the indium composition ratio becomes too high, which damages the flatness of the surface of the electron walking layer 12 Because of the deterioration in properties, high electron mobility can be ensured to optimize the structure of the electron walking layer 12. In addition, since the layer thickness of the component gradient region provided inside the electron walking layer 12 is greater than or equal to Inm and 5 nm or less, the layer thickness of the electron walking layer 12 can be ensured, and the storage of the two-dimensional electrons is sufficiently limited to the layer, It can prevent the lattice mismatch with the upper layer when it is too thick, and it is possible to reliably form the spacer layer 13 and the electron supply layer 1 4 with excellent crystallinity. In addition, since the electron walking layer 12 is doped with boron, it can be formed. Decreasing the carrier concentration of the electron walking layer 12 can reduce the influence of the 2D electrons stored in the electron walking layer 12 being scattered. Therefore, 'Using this point can also achieve high electron mobility, which can provide cross-conduction (g. Field-effect transistor with excellent characteristics. In addition, because the electron walking layer 12 is composed of GazIn i _ZP (0 $ ZS 1 ) Layer structure, which has a gradient toward the bonding interface 1 2b that is bonded to the spacer layer 13 side, increases the indium composition ratio in the direction of increasing layer thickness, and bonds from the spacer layer 13 to the electron walking layer 12 The bonding interface 12b faces the electron supply layer 14 side, and the gallium composition ratio decreases in the direction of increasing the layer thickness. Therefore, the barrier between the two layers 12 and 13 can be further increased to one level. Therefore, 2 Dimensional electrons are effectively stored inside the electronic walking layer 12 and can exhibit high electron shifts -11-517390 V. Description of the invention (1G) Mobility. A more specific example will be used to explain the GalnP tethering layer of the present invention. Structure and field effect transistor using the same. [Embodiment] (First Embodiment) Fig. 2 is a schematic cross-sectional view of a TEGFET of the first embodiment. In this embodiment, the details of the present invention are explained. Examples are built into GalnP The high electron mobility field effect transistor (TEGFET) includes an electron walking layer provided with a composition gradient region. The epitaxial layer structure for TEGFET 1A is (100) 2 ° (off) GaAs single crystal which is undoped and semi-insulating. The substrate 100 is constructed. The specific resistance of the GaAs single crystal of the substrate 100 is approximately 3 × 107 Ω · cm at room temperature. On the surface of the substrate 100 having a diameter of approximately 100 mm, an AlcGauAs / GaAs-based superlattice structure for forming the buffer layer 101 is deposited. The structure of the superlattice structure includes an undoped Alo.3oGao.7oAs layer and a doped p-type GaAs layer with an aluminum composition ratio (= C) of 0.30. Al 0.30 Ga () The carrier concentration of the .7 () As layer is approximately lxl014cnT3 with a layer thickness of 45nm. The carrier concentration of the p-type GaAs layer is 7xl013crrT3 and the layer thickness is 50nm. Al0.3. The number of stacked cycles with the p-type GaAs layer is 5 cycles. Both the Alo.3oGao.7oAs layer and the p-type GaAs layer are based on the use of trimethylgallium ((CH3) 3Ga) / trimethyllead ((CH3) 3A1) / CVD of arsenic (AsH3) / hydrogen (H2) reaction system under reduced pressure MOCVD, film formation at 640 ° C. The pressure during film formation is approximately 1.3x104 Pascal (Pa). Send) The gas uses hydrogen. -12- 517390 V. Description of the invention (n) On the buffer layer 101, according to the reduced pressure MOCVD method using (CH3) 3Ga / cyclopentadienyl indium (C5H5In) / AsH3 / H2 reaction system The n-type Ga0.80In0.2 () As layer that is doped in layers is used as an electronic walking layer (the first constituent layer 102-1 of the channel layer 02). The thickness of the first layer 102-1 is about 9 nm. An n-type GamInmAs layer having an indium composition ratio of 0.3 0 was laminated on the first layer 102-1 as the second constituent layer 102-2. The layer thickness of the second constituent layer 10-2-2 was about 2 nm. The first and second constituent layers 102-1 and 102-2 are used to form an electron walking layer 102 having a gradient indium composition. The carrier concentrations of the first and second constituent layers 102-1 and 102-2 constituting the electron walking layer 102 are both 3xl015cnT3. On the GalnAs composition gradient layer 102, a spacer layer 103 composed of undoped n-type Ga.51In (). 49P is laminated according to a reduced pressure MOCVD method using a (CH3) 3Ga / C5H5In / PH3 / H2 reaction system. . On the spacer layer 103, according to a reduced pressure MOCVD method using a (CH3) 3Ga / C5H5In / PH3 / H2 reaction system, the laminate is composed of η-type GaG.51In (). 49P doped with silicon (Si). Electron supply layer 104. The Si doping source used a hydrogen-disilane (Si2H6) (concentration of 10 vol. Ppm) mixed gas. The pressure during film formation was approximately 1.3 x 10 Pascal (Pa). The electron supply layer 104 has a carrier concentration of 2 × 1018cnT3 and a layer thickness of 25 nm. On the surface of the electron supply layer 104, a contact layer 105 made of Si-doped n-type GaAs is laminated using a (CH3) 3Ga / AsH3 / H2 reaction system. The erbium-doped source of Si uses the above-mentioned hydrogen-Yiguiyuan mixed gas. The carrier concentration of the contact layer 105 is 2 × 1018cnr3, and the layer thickness is about 50 nm. -13- 517390 V. Description of the invention (12) In addition, the gallium composition ratio of the electron supply layer 104 composed of 0αγΙη ^ γP is set to 0.51 because it is adjusted to be a crystal of the contact layer 105 formed of the GaAs laminated thereon. The grid spacing becomes substantially the same, so both sides have good matching. In the manner described above, after completing the epitaxial growth of the constituent layers 101 to 105 of the laminated structure 100A, the temperature is lowered to about 500 ° C in an ambient gas containing arsenic hydride (AsH3), and then cooled in an ambient gas of hydrogen. To room temperature. On the surface of the n-type GaAs contact layer 105, which is the outermost layer, an ohmic electrode made of an indium tin alloy is formed. Next, according to the ordinary Hall effect measurement method, the electron mobility of the two-dimensional electrons walking in the electron walking layer 102 is measured. The chip carrier concentration (ns) at room temperature (approximately 300 grams of Arvin (K)) is approximately 1.8xl012cm_2, and the electron mobility (// r τ) becomes approximately 570 0 c m 2 / V · S. That is, the conventional case is that the GaG.80Ino.20As layer does not include a composition gradient region, and the indium composition ratio is fixed at 0.20. When the electron walking layer is formed by this, the electron mobility U rt) is about 3 5 00 cm2 / V · s, when compared with this, it can be seen that this embodiment has a significant improvement. The surface of the n-type GaAs contact layer 105 on the outermost layer is processed into a recess shape by using a conventional patterning method of photolithography. On the n-type GaAs contact layer 105 remaining in a mesa shape, a source electrode 106 and a drain electrode 107 are formed. Each of the source and drain ohmic electrodes 106, 107 is composed of a stacked structure of gold and nickel (Au 93% by weight, Ge 7 by weight), nickel (Ni), and gold (Alm). Source electrode 106 and -14-517390 13 V. Description of the invention () The distance between the drain electrode 107 is 10 μηι. The surface of Ga.51In (). 49P electron supply layer 104 exposed on the recessed portion forms the lower layer. Schottky junction gate electrode 108, which is a laminated structure of titanium (Ti) and aluminum (A1) on the upper layer. The gate length of the gate electrode 108 is about 1 μm. Evaluation in this way The constructed GalnP is the direct current (DC) characteristic of TEGFET1 10. The saturation drain current (Idss) when the drain voltage is 2 volts (V) is about 68 milliamperes (mA). When the drain voltage is between 0V and 5 When scanning between V, there is almost no loop (hysteresis) in the drain current. The room temperature transconductance (gm) measured when the source / drain voltage is 2.0V is as high as 200 ± 5 MilliSiemens (mS) / mm, and become uniform. That is, it is known that the GaG.8 () In (). 2 () As layer does not contain a composition gradient region, and the indium composition ratio It is set to 0.20, and when the electron walking layer is constituted by this, its transconductance (gm) is about 150 milliSiemens (mS) / mm, and when compared with this, it can be seen that this embodiment has a significant improvement. When the interval for exposing the surface of the buffer layer 101 is 100 μm, the leakage current flowing between the Au · Ge ohmic electrodes is less than 1 μA at 40 V, which shows high voltage resistance. Therefore, the gate clamp The stop voltage becomes approximately -0.9V ± 0.03V, and a GalnP-based TEGFET having a uniform threshold can be provided. (Second Embodiment) FIG. 3 is a schematic cross-sectional view of the TEGFET of the second embodiment. The same constituent elements as in the first embodiment, the number 1 in the first digit of the symbol of the first embodiment is rewritten into 2, and its description is omitted. -15- 517390 V. Description of the invention (14) Electronics of this embodiment The walking layer 202 is constructed to have a Gaxln ^ xAs composition gradient region. The indium composition ratio is 0.20 at the bonding interface 202a bonded to the buffer layer 201, and the indium composition ratio is made at the bonding interface 202b bonded to the spacer layer 203. Becomes about 0.35. Of the electron walking layer 202 The layer thickness is approximately 8 nm. The gradient of the indium composition ratio is the ratio of the indium source (trimethylindium: (CH3) 3In) to the gallium source to be supplied to the MOCVD reaction system as the layer thickness increases (= (( : 113) 3111 / ((: 1 * 13) 3〇3) often increases linearly. The carrier concentration of the electron walking layer 202 is set to about 4 × 1016 cm_3. For the laminated structure 200A, the sheet carrier concentration (ns) at room temperature (approximately 300K) measured according to a general Hall effect measurement method is about 1.7x1 012cm_2, and the average electron movement is Degree (// RT) is about 6000 cm2 / V · s, so it appears to have a high electron mobility. In addition, in the GalnP-based TEGFET210 configured by the same method as the first embodiment, when the drain voltage is set to 2.0V, the transconductance (gm) at room temperature becomes 210 ± 5 milliSiemens (mS) / mm, can provide TEGFET with high performance g. (Third Embodiment) In this embodiment, a GalnP-based TEGFET provided with a GaxIni_xAs electron-walking layer doped with boron (B) is used as an example to describe the present invention in detail. The gradient of the same indium composition. When the TEGFET of this embodiment is compared with the second embodiment, only the GaxIm-xAs electron walking layer is different. Therefore, FIG. 3 is used for explanation. -16- 517390 V. Description of the invention (15) In the third embodiment, boron is doped during the growth of the GaxIimAs component gradient region constituting the electron walking layer 202. The doping source of boron is triethyl boron ((C2H5) 3B), which is commercially available for the electronics industry. The doping amount of triethylboron to the MOCVD reaction system is such that the carrier concentration of the n-type GaxIn ^ As component gradient layer in an undoped state is about 4x10 16cnT3, so the boron atom concentration in the layer is set to about 4x10I7cnT3. The carrier concentration of the GaxIm-xAs electron walking layer 202 is less than about 5x10 15cnT3 due to the doping of boron. The carrier concentration (ns) of the sheet at room temperature (approximately 300K) measured according to the ordinary Hall effect measurement method is approximately 1.6x 1012cnT2, and the average electron mobility (// RT) In this way, by doping boron in the electron walking layer 202 in this way, when compared with the case of the second embodiment, a higher electron mobility can be generated. When the drain voltage is set to 2V, the saturated source · drain current becomes about 70mA, and there is almost no hysteresis (loopback) at the drain current. In addition, when the source / drain voltage is 2.0 V, the transconductance (gm) at room temperature becomes as high as about 250 milli-Siemens (m S) / mm. [Effect of the invention] The present invention is configured in the above manner, Therefore, the effects described below are obtained. In the first or second item of the scope of patent application of the present invention, since the component gradient region is provided in the electronic walking layer, the gradient has a direction of increasing the layer thickness as it goes toward the bonding interface that is bonded to the electron supply layer side. -17- 517390 V. Description of the invention (16) Increase the indium composition ratio, so that the difference in the prohibited band width of the joint interface between the electronic walking layer and the electron supply layer can be made larger, which can make the two The barrier between layers becomes higher. Therefore, electrons supplied from the electron supply layer can be efficiently stored in the electron traveling layer as a two-dimensional electron, which can realize high electron mobility, and therefore, a field-effect transistor having excellent mutual conductivity characteristics can be provided. In addition, in the third item of the scope of patent application of the present invention, since the indium composition ratio of the joint interface between the electron walking layer and the electron supply layer is set to 0.30 or more and 0.5 or less, it can be effectively used inside the electron walking layer. Storage of two-dimensional electrons, and it is possible to reliably suppress the deterioration of the crystallinity of the spacer layer or the electron supply layer that occurs when the flatness of the surface of the electron walking layer is impaired when the indium composition ratio is too high. In addition, in item 4 of the scope of patent application of the present invention, the layer thickness of the electronic walking layer is set to be greater than Inm and 5 nm, so the layer thickness of the electronic walking layer can be ensured, and the storage of the two-dimensional electrons is sufficiently limited to the layer. It can prevent the lattice mismatch with the upper layer that occurs when it is too thick, and can reliably form a spacer layer and an electron supply layer with excellent crystallinity. In addition, in item 5 of the scope of patent application of the present invention, since the electron walking layer is doped with boron, the carrier concentration of the electron walking layer can be reduced, and the two-dimensional electrons stored in the electron walking layer can be reduced. The influence of being scattered. Therefore, using this point can also achieve high electron mobility, and can provide field-effect transistors with excellent mutual conductivity characteristics. In item 6 of the scope of patent application of the present invention, because the spacer layer is -18- 517390 5. The description of the invention (17) is composed of a GaxIm-xPiOS XS 1) layer containing a component gradient region, and the gradient has orientation and electron The bonding interface of the supply layer bonding decreases the gallium composition ratio in the direction of increasing layer thickness, so the barrier between the electron walking layer and the spacer layer can be further increased and indeed become higher. Therefore, it can be effectively inside the electron walking layer. Storage of two-dimensional electrons can reveal high electron mobility. [Brief description of the figure] Fig. 1 is an explanatory diagram of the GalnP-based multilayer structure of the present invention. U) A cross-section of the GalnP-based multilayer structure is schematically shown. The composition gradient of indium in the walking layer. Fig. 2 is a schematic cross-sectional view of the TEGFET of the first embodiment. Fig. 3 is a schematic cross-sectional view of a TEGFET according to the second embodiment. Fig. 4 is a schematic diagram of a cross-sectional structure of a conventional GalnP-based TEGFET. [Description of symbols] 1 ..... GalnP-based laminated structure 10 ····· Single crystalline substrate 11 ·· —— ·· Buffer layer 12 ····· Electronic walking layer 12a ··· •• Joining interface 12b ··· •• Joining interface 13 · · ·. · Spacer layer 14 · · · · • Electron supply layer 100 · · ·. · Substrate -19- 517390 V. Description of the invention (18) 100A · • · • • Multilayer Structure 101 • • • • • Buffer layer 102 • • • • • Electronic walking layer 102-1 • • • • • Composition layer 102-2 • • • • • Composition layer 103 • • • • • Spacer layer 104 • ···· Electronic supply layer 105 · · · ·. Contact layer 106 · · ··· Source electrode 107 · · · • • Drain electrode 108 · · · · · Gate electrode 200A · · · • • Multilayer structure Body 20 \ · · • • • Buffer layer 202 • • • • • Electronic walking layer 202a • • • • • Joint interface 202b • • .. Joint interface 203 • • • • • Spacer layer -20-