JP2001102568A - Iii-v compound semiconductor epitaxial wafer - Google Patents

Iii-v compound semiconductor epitaxial wafer

Info

Publication number
JP2001102568A
JP2001102568A JP27952899A JP27952899A JP2001102568A JP 2001102568 A JP2001102568 A JP 2001102568A JP 27952899 A JP27952899 A JP 27952899A JP 27952899 A JP27952899 A JP 27952899A JP 2001102568 A JP2001102568 A JP 2001102568A
Authority
JP
Japan
Prior art keywords
layer
epitaxial wafer
composition
compound semiconductor
channel layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27952899A
Other languages
Japanese (ja)
Inventor
Kazuto Takano
和人 高野
Tadaitsu Tsuchiya
忠厳 土屋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP27952899A priority Critical patent/JP2001102568A/en
Publication of JP2001102568A publication Critical patent/JP2001102568A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a III-IV compound semiconductor epitaxial wafer with improved electrical characteristics. SOLUTION: Since an In composition near the hetero-interface of a channel layer 30 constituted of InGaAs is similar to that of an electron supply layer 4, constituted of InGaP and In composition in the channel layer 30 changes continuously, the diffusion of In atoms is suppressed, and superior interface steepness is obtained. Thus, HEMT of high electron mobility is obtained by using such a III-V compound semiconductor epitaxial wafer.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、III-V族化合物半
導体エピタキシャルウェハに関する。
The present invention relates to a group III-V compound semiconductor epitaxial wafer.

【0002】[0002]

【従来の技術】一般に、III-V族化合物半導体の薄膜結
晶を結晶基板表面上にエピタキシャル成長させるには、
リアクター内で加熱状態にある結晶基板に、複数の III
族元素か、あるいはV族元素の原料ガスを含んだキャリ
アガスを送り込み、これらの原料ガスを結晶基板上で熱
分解させることによって行われる。
2. Description of the Related Art Generally, in order to epitaxially grow a thin film crystal of a group III-V compound semiconductor on a crystal substrate surface,
Multiple III substrates are placed on the heated crystal substrate in the reactor.
This is performed by feeding a carrier gas containing a source gas of a group V element or a group V element, and thermally decomposing these source gases on a crystal substrate.

【0003】図4は従来のIII-V族化合物半導体エピタ
キシャルウェハの断面図である。
FIG. 4 is a cross-sectional view of a conventional III-V compound semiconductor epitaxial wafer.

【0004】同図に示すエピタキシャルウェハは、Ga
As基板1の上に、厚さ200nmのun−GaAs層
2と、厚さ15nmのun−In0.15Ga0.85As層3
と、厚さ25nmで二次元電子ガス濃度2e18cm-3
のn−Ga0.52In0.48P層4とを順次成長させて積層
したものである。
The epitaxial wafer shown in FIG.
On an As substrate 1, a 200 nm thick un-GaAs layer 2 and a 15 nm thick un-In 0.15 Ga 0.85 As layer 3
And a two-dimensional electron gas concentration of 2e18 cm -3 at a thickness of 25 nm.
And n-Ga 0.52 In 0.48 P layer 4 are sequentially grown and laminated.

【0005】このような結晶成長法により異種の結晶を
積層して作製したヘテロ接合を利用したデバイスの一つ
にHEMTと呼ばれる高電子移動度トランジスタがあ
る。HEMTは、基本的には高純度層(例えばAs系化
合物半導体結晶のInGaAs)と、この高純度層より
も電子親和力が小さく、かつドーピングされて電子を供
給する機能を有するドーピング層(例えばP系の化合物
半導体結晶のInGaP)との2層からなる選択ドープ
構造の積層体上に、電極を設けて電界効果トランジスタ
としたものである。
A high electron mobility transistor called HEMT is one of devices using a heterojunction produced by laminating different kinds of crystals by such a crystal growth method. The HEMT is basically composed of a high-purity layer (for example, InGaAs of an As-based compound semiconductor crystal) and a doping layer (for example, P-based) having a function of supplying electrons by being doped with a smaller electron affinity than the high-purity layer. An electrode is provided on a layered structure having a selective doping structure consisting of two layers of a compound semiconductor crystal (InGaP) and a field effect transistor.

【0006】[0006]

【発明が解決しようとする課題】ところで、これらの層
の界面の高純度層側には2次元状に電子が蓄積する。こ
の電子は高純度層に形成されるため電子移動度が非常に
高く、この電子ガスをゲート電極に印加したバイアス電
圧による電界効果によって制御する。このときヘテロ接
合界面で組成が十分に急峻に切り替わってないと電子が
界面の凹凸や電気的に活性な結晶欠陥から散乱を受け、
電子移動度が低下してしまう。
By the way, electrons are accumulated two-dimensionally on the high-purity layer side of the interface between these layers. Since the electrons are formed in the high-purity layer, the electron mobility is very high. The electron gas is controlled by an electric field effect by a bias voltage applied to the gate electrode. At this time, if the composition is not switched sharply at the heterojunction interface, the electrons are scattered by the unevenness of the interface and the electrically active crystal defects,
Electron mobility decreases.

【0007】上述したInを用いた化合物半導体におい
ては、界面においてInが拡散しやすく急峻なヘテロ界
面の形成が困難である。
In the above-described compound semiconductor using In, In is easily diffused at the interface, and it is difficult to form a steep hetero interface.

【0008】Inの拡散を防止し、界面の急峻性を向上
させるためには、成長温度の低温下が望ましい。しか
し、この低温化のデメリットとして結晶への不純物混入
(CやO等)やドーピング効率の低下が起こるという問
題があった。
In order to prevent the diffusion of In and improve the steepness of the interface, it is desirable that the growth temperature be low. However, disadvantages of this low temperature include the problem that impurities are mixed into the crystal (C, O, etc.) and the doping efficiency is reduced.

【0009】そこで、本発明の目的は、上記課題を解決
し、電気的特性を向上させたIII-V族化合物半導体エピ
タキシャルウェハを提供することにある。
Accordingly, an object of the present invention is to provide a group III-V compound semiconductor epitaxial wafer which solves the above problems and has improved electrical characteristics.

【0010】[0010]

【課題を解決するための手段】上記目的を達成するため
に本発明のIII-V族化合物半導体エピタキシャルウェハ
は、基板上に、チャネル層と、チャネル層よりも電子親
和力の小さい電子供給層とが形成されたIII-V族化合物
半導体エピタキシャルウェハにおいて、基板がGaAs
からなり、チャネル層がInGaAsからなり、電子供
給層がInGaPからなり、チャネル層の界面付近の一
部の層の膜厚が臨界膜厚以下であり、かつInGaPと
同じIn組成であるものである。
In order to achieve the above object, a group III-V compound semiconductor epitaxial wafer according to the present invention comprises, on a substrate, a channel layer and an electron supply layer having an electron affinity smaller than that of the channel layer. In the formed III-V compound semiconductor epitaxial wafer, the substrate is GaAs.
, The channel layer is made of InGaAs, the electron supply layer is made of InGaP, the thickness of some layers near the interface of the channel layer is less than or equal to the critical thickness, and has the same In composition as InGaP. .

【0011】上記構成に加え本発明のIII-V族化合物半
導体エピタキシャルウェハは、電子供給層のIn組成が
GaAs基板に格子整合する0.484であり、チャネ
ル層の界面付近の一部の層の膜厚が臨界膜厚以下であ
り、かつIn組成が0.484であるのが好ましい。
In addition to the above structure, the III-V compound semiconductor epitaxial wafer of the present invention has an electron supply layer having an In composition of 0.484 lattice-matched to the GaAs substrate, and a partial layer near the channel layer interface. It is preferable that the film thickness be equal to or less than the critical film thickness and the In composition be 0.484.

【0012】上記構成に加え本発明のIII-V族化合物半
導体エピタキシャルウェハは、チャネル層の界面付近の
一部の層のIn組成が、界面から終端まで0.484か
ら設計組成まで連続的に変化しているのが好ましい。
In addition to the above structure, the III-V compound semiconductor epitaxial wafer of the present invention is characterized in that the In composition of a part of the layer near the interface of the channel layer continuously changes from 0.484 from the interface to the termination to the design composition. Preferably.

【0013】上記構成に加え本発明のIII-V族化合物半
導体エピタキシャルウェハは、In組成が連続的に変化
するチャネル層の一部の厚さが1〜10nmであるのが
好ましい。
In addition to the above constitution, in the group III-V compound semiconductor epitaxial wafer of the present invention, the thickness of a part of the channel layer in which the In composition changes continuously is preferably 1 to 10 nm.

【0014】一般に、結晶内での原子の拡散の度合いは
温度と濃度勾配とで決定される。従来のヘテロ接合構造
のエピタキシャルウェハは、ヘテロ界面においてIn濃
度の不連続が発生するため、界面でのIn拡散がより顕
著に起こる。
Generally, the degree of diffusion of atoms in a crystal is determined by temperature and concentration gradient. In a conventional epitaxial wafer having a heterojunction structure, discontinuity of the In concentration occurs at the hetero interface, so that In diffusion at the interface occurs more remarkably.

【0015】そこで、本発明者らは、InGaAsから
なるチャネル層のヘテロ界面付近でのIn組成を、In
GaPからなる電子供給層の組成と同じ組成とし、チャ
ネル層内のIn組成を連続的に変化させることにより、
In原子の拡散が抑止され優れた界面急峻性が得られる
ことを見出だした。従ってこのような電気的特性の優れ
たエピタキシャルウェハを用いてHEMTを作製すると
高電子移動度のHEMTが得られ、高速の信号処理を行
うことができる。
Therefore, the present inventors set the In composition near the heterointerface of the channel layer made of InGaAs to be In composition.
By making the composition the same as that of the electron supply layer made of GaP and continuously changing the In composition in the channel layer,
It has been found that diffusion of In atoms is suppressed and excellent interface steepness can be obtained. Therefore, when an HEMT is manufactured using such an epitaxial wafer having excellent electric characteristics, a HEMT having high electron mobility can be obtained, and high-speed signal processing can be performed.

【0016】[0016]

【発明の実施の形態】以下、本発明の実施の形態を添付
図面に基づいて詳述する。
Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

【0017】図1は本発明のIII-V族化合物半導体エピ
タキシャルウェハの一実施の形態を示す断面図である。
FIG. 1 is a sectional view showing an embodiment of a group III-V compound semiconductor epitaxial wafer of the present invention.

【0018】同図に示すエピタキシャルウェハは、基板
1上に、チャネル層3と、チャネル層3よりも電子親和
力の小さい電子供給層4とが形成されたIII-V族化合物
半導体エピタキシャルウェハであって、基板1がGaA
sからなり、チャネル層3がInGaAsからなり、電
子供給層4がInGaPからなり、チャネル層3の界面
付近の一部の層の膜厚が臨界膜厚以下であり、かつIn
GaPと同じIn組成としたものである。
The epitaxial wafer shown in FIG. 1 is a group III-V compound semiconductor epitaxial wafer having a substrate 1 on which a channel layer 3 and an electron supply layer 4 having an electron affinity smaller than that of the channel layer 3 are formed. Substrate 1 is GaAs
s, the channel layer 3 is made of InGaAs, the electron supply layer 4 is made of InGaP, the thickness of some layers near the interface of the channel layer 3 is less than the critical thickness, and
It has the same In composition as GaP.

【0019】本エピタキシャルウェハは、InGaAs
からなるチャネル層3のヘテロ界面付近でのIn組成
が、InGaPからなる電子供給層4の組成と同じ組成
であり、チャネル層3内のIn組成が連続的に変化して
いるので、In原子の拡散が抑止され優れた界面急峻性
が得られる。このような電気的特性に優れたエピタキシ
ャルウェハを用いることにより、高電子移動度のHEM
Tを作製することができる。
This epitaxial wafer is made of InGaAs.
Since the In composition near the hetero interface of the channel layer 3 made of In has the same composition as the composition of the electron supply layer 4 made of InGaP, and the In composition in the channel layer 3 changes continuously, Diffusion is suppressed, and excellent interface steepness is obtained. By using such an epitaxial wafer having excellent electrical characteristics, a high electron mobility HEM can be obtained.
T can be made.

【0020】[0020]

【実施例】図1に示すようなIn組成を0.48から
0.15まで連続的に変化させたIn組成変調層付き構
造のエピタキシャルウェハを作製した。すなわち、図1
に示すエピタキシャルウェハは、GaAs基板1の上
に、厚さ約200nmのun−GaAs層2と、厚さ約
13nmのun−In0.15Ga0.85As層3aと、厚さ
約1nmのun−In0.48→0.15 Ga0.52→0.85
As層3bと、厚さ約1nmのun−In0.48Ga0.52
As層3cと、厚さが約25nmで二次元電子ガス濃度
が約2e18cm-3のn−Ga0.52In0.48P層4とを
順次積層したものである。
EXAMPLE An epitaxial wafer having a structure with an In composition modulation layer in which the In composition was continuously changed from 0.48 to 0.15 as shown in FIG. 1 was produced. That is, FIG.
The epitaxial wafer shown in FIG. 1 has an un-GaAs layer 2 having a thickness of about 200 nm, an un-In 0.15 Ga 0.85 As layer 3 a having a thickness of about 13 nm, and an un-In 0.48 layer having a thickness of about 1 nm on a GaAs substrate 1. → 0.15 Ga 0.52 → 0.85
As layer 3b and un-In 0.48 Ga 0.52 about 1 nm thick
An As layer 3c and an n-Ga 0.52 In 0.48 P layer 4 having a thickness of about 25 nm and a two-dimensional electron gas concentration of about 2e18 cm −3 are sequentially laminated.

【0021】図2は図1に示したエピタキシャルウェハ
の成長時のガスシーケンスを示す図である。
FIG. 2 is a view showing a gas sequence during the growth of the epitaxial wafer shown in FIG.

【0022】図示しないサセプタ上に、直径4インチの
GaAs基板1を載置し、サセプタの温度を薄膜の成長
温度である600℃まで加熱する。サセプタは約11r
pmで回転させた。この状態で成長室のガス導入口(図
示せず)からInGaAs層30(3a、3b、3c)
の原料ガスである水素希釈したトリメチルガリウム(T
MG)、トリメチルインジウム(TMI)及びアルシン
(AsH3 )を流量を変えながら供給し、約15.0
sec成長を中断した後続いてGaInP層4の原料ガ
スであるトリメチルインジウム(TMI)、トリエチル
ガリウム(TEG)、フォスフィン(PH3 )及びジ
シラン(H6 Si2 =SiH3 SiH3 )の混合
ガスを供給することによりエピタキシャルウェハが得ら
れる。
A GaAs substrate 1 having a diameter of 4 inches is placed on a susceptor (not shown), and the temperature of the susceptor is heated to 600 ° C., which is the growth temperature of a thin film. Susceptor is about 11r
Rotated at pm. In this state, the InGaAs layer 30 (3a, 3b, 3c) is supplied from a gas inlet (not shown) of the growth chamber.
Hydrogen diluted trimethylgallium (T
MG), trimethylindium (TMI) and arsine (AsH 3 ) with varying flow rates, about 15.0.
After the sec growth is stopped, a mixed gas of trimethyl indium (TMI), triethyl gallium (TEG), phosphine (PH 3 ) and disilane (H 6 Si 2 = SiH 3 SiH 3 ), which are source gases of the GaInP layer 4, is supplied. By doing so, an epitaxial wafer is obtained.

【0023】この結果、図4に示した従来のエピタキシ
ャルウェハの電子移動度は3500cm2 -1sec
-1であったのに対し、図1に示した本発明のエピタキシ
ャルウェハの電子移動度は4800cm2 -1sec
-1と高い電子移動度が得られた。 図3はC−V測定に
より得られたキャリア濃度プロファイルを示す図であ
り、横軸が深さ軸であり、縦軸が二次元電子ガス濃度軸
である。同図において破線が本発明のエピタキシャルウ
ェハ、実線が従来のエピタキシャルウェハのキャリア濃
度プロファイルをそれぞれ示す。
As a result, the electron mobility of the conventional epitaxial wafer shown in FIG. 4 is 3500 cm 2 V −1 sec.
In contrast, the electron mobility of the epitaxial wafer of the present invention shown in FIG. 1 was 4800 cm 2 V −1 sec.
High electron mobility of -1 was obtained. FIG. 3 is a diagram showing a carrier concentration profile obtained by the CV measurement. The horizontal axis is the depth axis, and the vertical axis is the two-dimensional electron gas concentration axis. In the same figure, the broken line shows the carrier concentration profile of the epitaxial wafer of the present invention, and the solid line shows the carrier concentration profile of the conventional epitaxial wafer.

【0024】同図より、電子移動度が高いものはun−
GaAs層とチャネル層との界面に電子が閉じ込めら
れ、二次元電子ガスのピークが高くなることが分る。従
って、チャネル層内のIn組成を連続的に変化させるこ
とにより、界面急峻性を実現することができ、電子移動
度を高める効果があることが分った。従って図1に示す
エピタキシャルウェハを用いてHEMTを作製すること
により高電子移動度のHEMTが得られ高速の信号に対
応できるという優れた電気的特性が得られる。
As shown in the figure, those having a high electron mobility are un-
It can be seen that electrons are confined at the interface between the GaAs layer and the channel layer, and the peak of the two-dimensional electron gas increases. Therefore, it has been found that by continuously changing the In composition in the channel layer, the interface steepness can be realized, and the effect of increasing the electron mobility can be obtained. Therefore, by manufacturing a HEMT using the epitaxial wafer shown in FIG. 1, a HEMT having a high electron mobility can be obtained, and excellent electrical characteristics that can respond to a high-speed signal can be obtained.

【0025】ここで、ヘテロ界面でのInGaPとIn
GaAsとのIn組成が等しいことが最適条件である。
しかし、InGaAs層界面付近の組成変調部の厚さ
は、臨界膜厚以下でなくてはならないが、薄すぎても組
成の不連続部が生じることになり特性は低下してしま
う。この構造はp−HEMTエピタキシャルウェハの構
造や成長条件により異なるため、試行錯誤によりおさえ
なければならない。
Here, InGaP and In at the hetero interface are used.
The optimum condition is that the In composition with GaAs is equal.
However, the thickness of the composition modulation portion near the interface of the InGaAs layer must be equal to or less than the critical film thickness. However, if the thickness is too small, a discontinuous portion of the composition occurs, and the characteristics are degraded. This structure depends on the structure and growth conditions of the p-HEMT epitaxial wafer, and must be suppressed by trial and error.

【0026】なお、本実施例では電子デバイス用薄膜成
長の例を述べたが、本発明のIII-V族化合物半導体エピ
タキシャルはヘテロ接合を用いるデバイスならレーザ用
薄膜成長にも適用できる。
In this embodiment, an example of the growth of a thin film for an electronic device has been described. However, the III-V compound semiconductor epitaxial of the present invention can be applied to the growth of a thin film for a laser as long as the device uses a heterojunction.

【0027】[0027]

【発明の効果】以上要するに本発明によれば、次のよう
な優れた効果を発揮する。
In summary, according to the present invention, the following excellent effects are exhibited.

【0028】電気的特性を向上させたIII-V族化合物半
導体エピタキシャルウェハの提供を実現することができ
る。
It is possible to provide a III-V compound semiconductor epitaxial wafer having improved electrical characteristics.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のIII-V族化合物半導体エピタキシャル
ウェハの一実施の形態を示す断面図である。
FIG. 1 is a sectional view showing an embodiment of a group III-V compound semiconductor epitaxial wafer of the present invention.

【図2】図1に示したエピタキシャルウェハの成長時の
ガスシーケンスを示す図である。
FIG. 2 is a view showing a gas sequence when the epitaxial wafer shown in FIG. 1 is grown.

【図3】C−V測定により得られたキャリア濃度プロフ
ァイルを示す図である。
FIG. 3 is a diagram showing a carrier concentration profile obtained by CV measurement.

【図4】従来のIII-V族化合物半導体エピタキシャルウ
ェハの断面図である。
FIG. 4 is a cross-sectional view of a conventional III-V compound semiconductor epitaxial wafer.

【符号の説明】[Explanation of symbols]

1 GaAs基板 2 チャネル層(un−GaAs層) 3a チャネル層(un−In0.15Ga0.85As層) 3b チャネル層(un−In0.48→0.15 Ga
0.52→0.85 As層) 3c チャネル層(un−In0.48Ga0.52As層) 4 電子供給層(n−Ga0.52In0.48P層、GaIn
P層) 30 チャネル層(InGaAs層)
1 GaAs substrate 2 Channel layer (un-GaAs layer) 3a Channel layer (un-In 0.15 Ga 0.85 As layer) 3b Channel layer (un-In 0.48 → 0.15 Ga
0.52 → 0.85 As layer) 3c channel layer (un-In 0.48 Ga 0.52 As layer) 4 electron supply layer (n-Ga 0.52 In 0.48 P layer, GaIn
P layer) 30 Channel layer (InGaAs layer)

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01S 5/323 // H01L 29/20 Fターム(参考) 4G077 AA03 BE47 DB01 ED06 EF03 5F045 AB10 AB17 AC01 AC08 AC19 AD10 AF04 BB05 BB12 BB16 CA07 CA12 DA52 DA58 DA66 5F073 CA07 CB02 DA05 5F102 FA00 GB01 GC01 GD01 GJ05 GK05 GL00 GL04 GL07 GL08 GL16 GL17 GM04 GM10 GQ01 HC01 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI theme coat ゛ (Reference) H01S 5/323 // H01L 29/20 F term (Reference) 4G077 AA03 BE47 DB01 ED06 EF03 5F045 AB10 AB17 AC01 AC08 AC19 AD10 AF04 BB05 BB12 BB16 CA07 CA12 DA52 DA58 DA66 5F073 CA07 CB02 DA05 5F102 FA00 GB01 GC01 GD01 GJ05 GK05 GL00 GL04 GL07 GL08 GL16 GL17 GM04 GM10 GQ01 HC01

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 基板上に、チャネル層と、該チャネル層
よりも電子親和力の小さい電子供給層とが形成されたII
I-V族化合物半導体エピタキシャルウェハにおいて、上
記基板がGaAsからなり、上記チャネル層がInGa
Asからなり、上記電子供給層がInGaPからなり、
上記チャネル層の界面付近の一部の層の膜厚が臨界膜厚
以下であり、かつInGaPと同じIn組成であること
を特徴とするIII-V族化合物半導体エピタキシャルウェ
ハ。
1. A semiconductor device comprising: a substrate, a channel layer, and an electron supply layer having an electron affinity smaller than that of the channel layer.
In the IV compound semiconductor epitaxial wafer, the substrate is made of GaAs, and the channel layer is made of InGa.
As, the electron supply layer is made of InGaP,
A III-V compound semiconductor epitaxial wafer, wherein the thickness of a part of the layer near the interface of the channel layer is equal to or less than the critical thickness and has the same In composition as InGaP.
【請求項2】 上記電子供給層のIn組成がGaAs基
板に格子整合する0.484であり、上記チャネル層の
界面付近の一部の層の膜厚が臨界膜厚以下であり、かつ
In組成が0.484である請求項1に記載のIII-V族
化合物半導体エピタキシャルウェハ。
2. The electron supply layer has an In composition of 0.484 lattice-matched to a GaAs substrate, a thickness of a part of the layer near an interface of the channel layer is less than a critical thickness, and an In composition. The III-V compound semiconductor epitaxial wafer according to claim 1, wherein is 0.484.
【請求項3】 上記チャネル層の界面付近の一部の層の
In組成が、界面から終端まで0.484から設計組成
まで連続的に変化している請求項2に記載のIII-V族化
合物半導体エピタキシャルウェハ。
3. The group III-V compound according to claim 2, wherein the In composition of a part of the layer near the interface of the channel layer continuously changes from 0.484 to the design composition from the interface to the terminal. Semiconductor epitaxial wafer.
【請求項4】 上記In組成が連続的に変化するチャネ
ル層の一部の厚さが1〜10nmである請求項3に記載
のIII-V族化合物半導体エピタキシャルウェハ。
4. The III-V compound semiconductor epitaxial wafer according to claim 3, wherein the thickness of a part of the channel layer in which the In composition continuously changes is 1 to 10 nm.
JP27952899A 1999-09-30 1999-09-30 Iii-v compound semiconductor epitaxial wafer Pending JP2001102568A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27952899A JP2001102568A (en) 1999-09-30 1999-09-30 Iii-v compound semiconductor epitaxial wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27952899A JP2001102568A (en) 1999-09-30 1999-09-30 Iii-v compound semiconductor epitaxial wafer

Publications (1)

Publication Number Publication Date
JP2001102568A true JP2001102568A (en) 2001-04-13

Family

ID=17612278

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27952899A Pending JP2001102568A (en) 1999-09-30 1999-09-30 Iii-v compound semiconductor epitaxial wafer

Country Status (1)

Country Link
JP (1) JP2001102568A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002176169A (en) * 2000-12-05 2002-06-21 Showa Denko Kk GaInP-BASED LAMINATED STRUCTURE BODY AND FIELD EFFECT TRANSISTOR MANUFACTURED BY USING THE SAME

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002176169A (en) * 2000-12-05 2002-06-21 Showa Denko Kk GaInP-BASED LAMINATED STRUCTURE BODY AND FIELD EFFECT TRANSISTOR MANUFACTURED BY USING THE SAME

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