經濟部智慧財產局員工消費合作社印制衣 515072 A7 五、發明說明（1 ) 發明領域： 本發明係關於防止基板背面金屬污染問題的方法，特 別是關於防止在顯影以定義出導線結構過程中，基板背面 之金屬沈積作爲蝕刻多晶矽層及氧化矽層之罩幕。 發明背景： 在半導體製程中，利用沈積各式薄膜之手段於基板正面 上，以形成半導體元件及其線路，但在形成薄膜時雖以沈 積薄膜於基板正面爲目的，但在沈積製作過程若使用爐管 (furnace)進行沈積作業，則薄膜並非僅形成於基板正面，基 板的正面及背面皆會沈積薄膜；由於目前半導體製程中， 基板背面並無任何運用，因此，只要基板背面所沈積之薄 膜不會影響半導體元件及其線路之製作即可。 但在沈積鎢金屬以製作導線間之金屬插塞(plug)時，係 使用化學氣相沈積法(chemical vapor deposition ; CVD)沈積 於基板之最上層形成所述之插塞，目前半導體製程中多使 用鎢金屬材質作爲插塞，但在沈積過程中基板背面部分會 有鎢金屬70沈積於其上，鎢金屬70通常於如圖一所示之 化學氣相沈積機台中晶片架3之氣體通孔處7，形成鎢金屬 70之沈積物於基板背面部分，如圖二所示，而位於基板背 面之中心處亦會有同心圓狀之鎢金屬71沈積，倘若在製作 鎢金屬插塞前之基板背面最表層爲氧化矽層，則所沈積之 鎢金屬70或71並不會與所述之氧化矽層進行任何作用。 然後，若在進行製作鎢插塞時其基板背面最上層之沈積 _____ 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)Printed clothing of the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 515072 A7 V. Description of the invention (1) Field of the invention: The present invention relates to a method for preventing metal contamination on the backside of a substrate, and in particular, to prevent the development of a wire structure during development, The metal deposition on the back of the substrate serves as a mask for etching the polycrystalline silicon layer and the silicon oxide layer. Background of the Invention: In the semiconductor manufacturing process, various thin films are deposited on the front surface of a substrate to form semiconductor elements and circuits. However, although the purpose of forming a thin film is to deposit the thin film on the front surface of the substrate, if it is used in the deposition process, Furnace (furnace) for the deposition operation, the film is not only formed on the front side of the substrate, the front side and the back side of the substrate will be deposited on the film; since the current semiconductor manufacturing process, the back side of the substrate is not used, so as long as the film deposited on the back side of the substrate It does not affect the fabrication of semiconductor elements and their circuits. However, when depositing tungsten metal to make metal plugs between wires, chemical vapor deposition (CVD) is used to deposit the plugs on the uppermost layer of the substrate to form the plugs. Currently, many semiconductor processes are used. Tungsten metal is used as the plug, but during the deposition process, tungsten metal 70 will be deposited on the back part of the substrate. The tungsten metal 70 is usually in the gas through hole of the wafer holder 3 in the chemical vapor deposition machine shown in FIG. At 7, a tungsten metal 70 deposit is formed on the back surface of the substrate, as shown in FIG. 2, and a concentric circular tungsten metal 71 is also deposited at the center of the back surface of the substrate. If the substrate before the tungsten metal plug is manufactured, The outermost surface layer is a silicon oxide layer, and the deposited tungsten metal 70 or 71 will not perform any function with the silicon oxide layer. Then, if the deposition of the top layer on the back of the substrate when making tungsten plugs is _____ 2 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling in this page)
515072 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（工） 物爲多晶矽層(P〇lysilic〇n)時，部分之多晶矽層上會有鎢金 屬沈積，但在後續製作下一層金屬導線過程中，需用光阻 定義出導線位置，而半導體製程係使用光阻去除液將光阻 除去時，必須將整片基板直接浸泡(dip)於顯影液中，而由於 光阻去除液不會對金屬材質或氧化矽材質產生侵飩，卻會 侵蝕多晶矽材質，如此，基板背面上多晶矽層上有鎢金屬 加以保護著，故不會受到光阻去除液的蝕刻，而裸露之多 晶矽部分將會遭受光阻去除液触刻，其狀況就如同以鎢金 屬做爲蝕刻多晶矽之保護層，如此將會造成基板之不平整 狀況，將造成後續製程曝光之困難。 鎢金屬形成於基板背面之詳細情況如圖三所示，圖三 A〜C中所使之基板20皆顯示基板之背面，而基板20正面 之元件在圖中並未示出，在經過多步驟製作半導體元件 後，其基板20背面已沈積了多層膜結構，如圖三A所示， 基板20背面係有多層薄膜結構，本示意圖中僅顯現出氧化 矽層21及多晶矽層22及部分之鎢金屬23。在製程中形成 鎢金屬插塞後，接續製作下一層金屬連線，使用灑鍍方式 (sputtering)形成金屬層於基板20正面之上(圖中未示)，由於 使用濺鍍方式形成金屬層，因此，基板背面並不會有金屬 層之沈積，接續，使用光阻定義出金屬導線，並使用顯影 液將軟化之光阻除去，在此過程中，顯影液會將基板2〇背 面之裸露於外之多晶矽層22侵蝕(光阻去除液對金屬材質 或氧化矽材質與多晶矽材質間之鈾刻選擇比差異大），如圖 三B所示，而位於鎢金屬23下之多晶矽層22a會因鎢金屬 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公ΪΓ -----------^----------------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 515072 A7 _____ B7___ 五、發明說明（〕） 23之保護而留下，其多晶矽層厚度大約550埃左右，因此’ 原本受多晶矽22所保護之氧化矽層21因此而裸露出來。 接著，於基板正面使用飩刻方式形成金屬導線，並於所 述之金屬導線間沈積氧化矽材質作爲絕緣之用，而爲了使 後續形成之導線連通所述之金屬導線’因此製程會於所述 之氧化政層中形成基板20正面的接觸窗(via)並塡充金屬材 質於所述之接觸窗中，如此，會於所述之氧化矽層中使用 光阻定義出所述接觸窗形狀，並使用濕式蝕刻(wet etchin§) 形成。但由於基板之背面情況如圖三B所示，基板20背面 之氧化政層21部分有鶴金屬23及多晶政22a，而其他未受 保護之氧化矽層21在經所述之濕式蝕刻時，位於基板20 背面之未受保護的氧化矽層21會隨著使用濕式飩刻之過程 一倂被侵蝕掉，形成如圖三c所示’其狀況如同基板20背 面係有多晶矽22a及鎢金屬23作爲氧化矽層21之硬式罩幕 (hard mask)定義而成。但所述氧化砂層21之沈積厚度大約 6000埃左右，造成基板20背面經蝕刻過後之氧化矽層21a 剝落現象，而污染同一批貨(㈣)之其他基板，即使所述之氧 化矽層21a無剝落現象產生，也會使基板2〇高低不齊造成 後續進行導線製作時，使用微影步驟定義出其它層之導線 時步進機(stepper)之聚焦困難。 因此，本發明係提供防止基板背面遭受鎢金屬污染問題 的方法，以解決上述所造成之問題。 發明之槪述： 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------^--------^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 515072 _______B7__— ----- 五、發明說明（4 ) 本發明之主要目的是提供防止基板背面金屬污染問題 的方法，在使用顯影液定義出插塞上之金屬導線前’先在 晶片背面金屬層及多晶矽層間形成一層薄氧化矽層，防止 多晶砂層被顯影液侵蝕。 本發明之次要目的是提供防止基板背面金屬污染問題 的方法，防止位於多晶矽層下方之氧化矽層暴露於後續之 濕式蝕刻液中，使基板高低不平而導致後續微影之聚焦困 難。 本發明的另一目的是提供防止基板背面金屬污染問題 的方法，防止晶片背面之氧化矽層及多晶矽層產生剝落現 象。 本發明係使用下列步驟來達到上述之各項目的:首先’ 提供一完成主動元件之基板，使用濺鍍方式形成一金屬層 於所述之基板最上層，且所述基板背面之最上層爲多晶矽 層，接著，定義所述之金屬層以形成第一層金屬連線結構， 並形成一氧化矽薄層於基板背面所述之多晶矽層上，防止 形成鎢金屬插塞時，鎢金屬與基板背面所述之多晶矽層彼 此間直接接觸；最後，形成鎢金屬插塞(metal plug)於所述之 第一層金屬連線結構之上。 圖式簡要說明： 圖一爲化學氣相沈積形成鎢金屬之設備示意圖。 圖二爲習知技術中晶片背面上部分沈積之金屬與化學 氣相沈積機台之通氣孔間的結構示意圖。 5 尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） " -----------^w· --------^--------- (請先閱讀背面之注意事項再填寫本頁) 515072 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（y) 圖三A〜C爲習知技術中晶片背面之多晶矽層與沈積之 金屬曾接觸，而造成基板背面受到鶴金屬污染之製程剖面 示意圖。 圖四爲本發明爲防止基板背面受到金屬污染之製程剖 面示意圖。 圖號說明： 1-抽器幫浦 2-加熱器 3-置晶架 4-抽氣孔 5-通氣管 6-通氣管 7-通氣管 8-氣閥 9-氣閥 10-氣閥 11-晶座 12-淋氣結構 20,基板 21-氧化政薄層 22-多晶矽層 23-鎢金屬層 70-鎢金屬層 71-鎢金屬層 100-通氣孔 200-氧化矽層 發明詳細說明‘· 在製作金屬插塞過程中，由於基板背面上會有金屬部 分沈積於其上，若所述基板背面之最上方爲多晶矽層時， 本發明可應用在防止金屬沈積於所述之多晶矽層上時，造 成基板背面有部分被侵飽現象，導致基板不平整之現象而 使後續微影時之聚焦困難，也同時爲避免基板背面未被侵 蝕處在後續步驟中不定時剝落造成同一批貨之其它基板受 6 張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） _ (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------· 515072 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（b) 到污染。以下之實施例將利用已完成超大型積體電路之主 要元件製作後，欲形成多重金屬連線於基板上之多重金屬 連線製程，且使用鎢金屬作爲製作插塞材質來闡述本發明 之技術手段。 追究其形成鎢金屬於基板背面之原因，如圖一所示， 係由於在進行化學氣相反應(CVD)時，將晶片置於反應機台 之晶座11中進行反應，反應氣體氟化鎢(WF6)及砂烷(SiHLO 或氫氣(H2)由淋氣結構12釋出，並運用加熱器2使整個反 應器達到所需的反應溫度，當反應過程中爲了使基板能固 定於晶座11中，會於晶座11下方形成通氣孔5及6，上述 之通氣孔5及6經過一氣閥8與抽器幫浦1相連，將壓力 降低，利用壓力差將基板固定於所述之晶座11上。 當反應結束後，需將基板正面與反面壓力調節至相 同，所以會將氣閥8關閉，並將氣閥9打開釋出鈍性氣體 如氬氣(Ar)以調節壓力，由於，利用外來氣體如氬氣調節基 板正面及反面壓力較不準確，因此會另打開氣閥1〇將原僅 位於基板正面之反應氣體經由通氣管7釋入基板背面使壓 力真正達到平衡。但在釋入反應氣體後，便有鎢金屬沈積 於基板背面之通氣孔7附近，而造成基板背面鎢金屬70和 71部分沈積，如圖二所示，因此，而有習知技術中所述之 以鎢金屬70和71作爲硬式罩幕飩刻至氧化矽層之問題； 上述之鎢金屬可爲其它之金屬材質如鋁(A1)等材質。 硏究指出鎢金屬形成可由三種管道形成： 1. WF6 + SiH4->Ww + SiF4 + 2HF + H2 7 -------.-----φ-裝------ (請先閱讀背面之注意事項再填寫本頁) 訂-------- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 515072 A7 部 智 慧 財 產 局 員 費 合 作 五、發明說明（/ ) 2. WF6 + 3H2->W(S) + 6HF 3. 2WF6 + 3Si^2W(s) + 3SiF4 反應氣體會於基板背面通氣孔7附近沈積鎢金屬 此在半導體製程中沈積鎢金屬於基板正面時’無可避免會 有鎢金屬沈積於基板之部分，因此，本發明係在基板背面 之鎢金屬形成前，先沈積一氧化矽層200以保護其下之多 晶矽層22使其不在定義金屬圖案時，被所使用之顯影液侵 蝕，如此，便不會有習知技術中導致基板不平整的現象產 生。 其製作方法如下所述，首先請參閱圖四，提供一基板 20，其上述之基板20已完成主動元件(圖中未示），於圖四 之製程剖面示意圖中僅表現出基板之背面，係由於本發明 之重點在於保持基板背面之完整性；由於製作電性元件之 故需沈積導電或不導電之各式薄膜，因此基板背面會形成 多層結構，在本實施例中僅描述基板2〇背面上沈積有氧化 矽薄層21及多晶矽層22，係由於導致基板表面不平整之原 因是由位於最外層之多晶政層22及氧化砂薄層21受飽刻 造成，位於氧化矽薄層21下之多層結構爲製作間隙壁 (spacer)、硬式罩幕和閘極結構(gate structure)時沈積於基板 背面。 本發明亦可運用於靜態隨機存取記憶體中(static random acess memory ; SRAM)時，而上述之氧化砂薄層21 係爲兩層之氧化砂層結構(圖中未7。 於完成主動元件製作之基板2〇上，使用濺鍍方式形成 (請先閱讀背面之注意事項再填寫本頁) 裝 II---------#. 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 29/公釐） 515072 經濟部智慧財產局員Η消費合作社印制衣 A7 B7 五、發明說明（i) 第一谓金屬層，並使用光阻(resist)經微影(lithography)步驟以 定義出第一層金屬導線結構(圖中未示），上述之第一層金屬 層材質係爲鋁銅合金(AlCu)及鋁(A1)其中之一 ’接續，進入 本發明之重點，係以氧氣(〇2)爲反應氣體之電漿(Plasma)在 多晶矽層22之上形成一氧化矽層200，其所形成之氧化矽 層200之厚度大於10埃。由於所述之氧化矽層2〇〇保護所 述之多晶矽層22，後續製程步驟中將基板置入顯影液中定 義出第一層金屬導線結構，顯影液對氧化矽層200於反應 溫度小於l〇5°C時之蝕刻效率低，因此可保護多晶矽層22 而不至使多晶矽層22以鎢金屬層23爲蝕刻罩幕進行多晶 矽層22及氧化矽薄層21之蝕刻動作。 接續，使用化學氣相沈積方式(CVD)形成一鎢金屬層以 製作鎢金屬插塞，用以連接兩層導線結構。在製作鎢金屬 插塞過程中，鎢金屬23亦會沈積於基板背面之上，由於多 晶矽層22表面已有氧化砂薄層200保護，因此，鎢金屬23 不是直接沈積於多晶矽層22之上，因此，不會有習知技術 上之問題產生；上述之製作插塞之材質亦可使用其它材質 如銘銅合金(AlCu)或銘(A1)代替，如此，直接沈積於多晶石夕 層22上之金屬即爲鋁銅合金(AlCu)或鋁(A1)。 綜上所述，本發明所提供較習知技術具有下列優點： 1. 本發明中於沈積金屬插塞前較習知技術多加之氧化 矽薄層，可作爲定義金屬結構之顯影過程中的蝕刻中 止層，防止傷害其下之多晶矽層。 2. 本發明不會有多晶矽層及氧化矽層遭受蝕刻現象，因 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 515072 A7 B7 五、發明說明（) 此’便不會有基板高低不平狀況，導致微影之困難。 3·本發明不會有多晶砂層及氧化砂層遭受飩刻現象，因 此，多晶砂層及氧化砍層不會剝落而污染同一批貨之 基板，提高良率降低生產成本。 以上所述係利用較佳實施例詳細說明本發明，而非限制 本發明的範圍’因此熟知此技藝的人士應能明瞭，適當而 作些微的改變與調整，仍將不失本發明之要義所在，亦不 脫離本發明之精神和範圍’故都應視爲本發明的進一步實 施狀況。_請貴審查委員明鑑，並祈惠准，是所至禱。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 票^TCNS)A4 規 1^210 X 297 公釐)515072 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs. 5. Description of Invention (Work) When the polysilicon layer (PolysilicOn) is used, tungsten metal may be deposited on some of the polycrystalline silicon layer, but the next layer will be produced later. In the process of metal wires, a photoresist is used to define the position of the wire. When the semiconductor process uses a photoresist removal solution to remove the photoresist, the entire substrate must be directly immersed (dip) in the developer solution. Does not invade metal materials or silicon oxide materials, but will erode the polycrystalline silicon material. In this way, the polycrystalline silicon layer on the back of the substrate is protected by tungsten metal, so it will not be etched by the photoresist removal solution, and the exposed polycrystalline silicon portion It will be exposed to the photoresist removal liquid, which is similar to the situation where tungsten metal is used as a protective layer for etching polycrystalline silicon. This will cause unevenness of the substrate and make it difficult to expose the subsequent process. The details of the tungsten metal formed on the back of the substrate are shown in Figure 3. The substrates 20 shown in Figures A to C all show the back of the substrate, and the components on the front of the substrate 20 are not shown in the figure. After multiple steps, After the semiconductor device is manufactured, a multilayer film structure has been deposited on the back surface of the substrate 20, as shown in FIG. 3A. The back surface of the substrate 20 has a multilayer thin film structure. In this schematic diagram, only the silicon oxide layer 21 and the polycrystalline silicon layer 22 and a portion of tungsten are shown. Metal 23. After the tungsten metal plug is formed in the manufacturing process, the next layer of metal wiring is successively produced, and a metal layer is formed on the front surface of the substrate 20 by sputtering (not shown). Since the metal layer is formed by sputtering, Therefore, there is no deposition of a metal layer on the back of the substrate. Continuing, a photoresist is used to define the metal wire, and a developing solution is used to remove the softened photoresist. In this process, the developing solution will expose the back of the substrate 20 to the substrate. The outer polycrystalline silicon layer 22 is eroded (the photoresist removal liquid has a large difference in the uranium etch ratio between the metal material or the silicon oxide material and the polycrystalline silicon material), as shown in Figure 3B, and the polycrystalline silicon layer 22a located under the tungsten metal 23 will cause Tungsten metal 3 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) Γ ----------- ^ ----------------- (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 515072 A7 _____ B7___ V. Invention Description ()) 23 is left behind, and its polycrystalline silicon layer is about 550 angstroms thick, Therefore, the silicon oxide layer 21, which was originally protected by polycrystalline silicon 22 Therefore, a metal wire is formed on the front surface of the substrate by using an engraving method, and a silicon oxide material is deposited between the metal wires as insulation, and in order to allow the subsequently formed wires to communicate with the metal wires. In the manufacturing process, a contact window (via) on the front surface of the substrate 20 is formed in the oxide layer and a metal material is filled in the contact window. In this way, a photoresist is used to define the silicon oxide layer in the silicon oxide layer. The contact window shape is described and formed using wet etchin. However, as the back surface of the substrate is shown in FIG. 3B, the oxide layer 21 on the back surface of the substrate 20 includes crane metal 23 and polycrystalline silicon 22a. When the other unprotected silicon oxide layer 21 is wet-etched as described above, the unprotected silicon oxide layer 21 on the back of the substrate 20 will be eroded away with the wet etching process, forming a pattern such as The condition shown in FIG. 3c is defined as the hard mask of the silicon oxide layer 21 with polycrystalline silicon 22a and tungsten metal 23 on the back surface of the substrate 20. However, the thickness of the oxide sand layer 21 is about 6000 angstroms. , Make After the back surface of the substrate 20 is etched, the silicon oxide layer 21a peels off, and contaminates other substrates in the same shipment (㈣). Even if the silicon oxide layer 21a is not peeled off, it will cause the substrate 20 to be uneven. When making the wire, the lithography step is used to define the focus of the stepper when the wires of other layers are difficult. Therefore, the present invention provides a method for preventing the back surface of the substrate from being contaminated by tungsten metal, so as to solve the above-mentioned problems. Description of the invention: This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ----------- ^ -------- ^ (Please read first Note on the back, please fill out this page again) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 515072 _______B7__------ V. Description of the invention (4) The main purpose of the present invention is to provide a method to prevent metal pollution on the back of the substrate Before using the developing solution to define the metal wires on the plug, 'a thin silicon oxide layer is formed between the metal layer on the back of the wafer and the polycrystalline silicon layer to prevent the polycrystalline sand layer from being attacked by the developing solution. A secondary object of the present invention is to provide a method for preventing metal contamination on the back surface of a substrate, preventing a silicon oxide layer located under a polycrystalline silicon layer from being exposed to a subsequent wet etching solution, making the substrate uneven and causing difficulty in focusing subsequent lithography. Another object of the present invention is to provide a method for preventing the metal contamination problem on the back surface of the substrate, and to prevent the silicon oxide layer and the polycrystalline silicon layer on the back surface of the wafer from peeling off. The present invention uses the following steps to achieve the above-mentioned items: First, a substrate for completing an active device is provided, and a metal layer is formed on the uppermost layer of the substrate by sputtering, and the uppermost layer on the rear surface of the substrate is polycrystalline silicon. Layer, and then define the metal layer to form a first metal connection structure, and form a thin layer of silicon oxide on the polycrystalline silicon layer described on the back surface of the substrate to prevent the formation of tungsten metal plugs between the tungsten metal and the back surface of the substrate The polycrystalline silicon layers are in direct contact with each other; finally, a tungsten metal plug is formed on the first metal connection structure. Brief description of the drawings: Figure 1 is a schematic diagram of a device for forming tungsten metal by chemical vapor deposition. FIG. 2 is a schematic diagram showing the structure between a partially deposited metal on the back of a wafer and a vent hole of a chemical vapor deposition machine in the conventional technology. 5 scales are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) " ----------- ^ w · -------- ^ ------- -(Please read the notes on the back before filling out this page) 515072 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (y) Figure 3 A ~ C are the polycrystalline silicon layers on the back of the wafer in the conventional technology Schematic cross-sectional view of the manufacturing process that has been in contact with Shen Jizhi's metal, causing the back of the substrate to be contaminated with crane metal. FIG. 4 is a schematic cross-sectional view of a process for preventing the back surface of the substrate from being contaminated with metal. Description of drawing number: 1-pump pump 2-heater 3-crystal holder 4-exhaust hole 5-vent pipe 6-vent pipe 7-vent pipe 8-pneumatic valve 9-pneumatic valve 10-pneumatic valve 11-crystal Block 12- Air-gushing structure 20, Substrate 21- Oxidation thin layer 22- Polycrystalline silicon layer 23- Tungsten metal layer 70- Tungsten metal layer 71- Tungsten metal layer 100- Vent hole 200- Silicon oxide layer Detailed description of the invention During the metal plug process, since a metal portion is deposited on the back surface of the substrate, if the uppermost part of the back surface of the substrate is a polycrystalline silicon layer, the present invention can be applied to prevent the metal from being deposited on the polycrystalline silicon layer. The back surface of the substrate is partially saturated, which leads to the unevenness of the substrate, which makes it difficult to focus during subsequent lithography. At the same time, in order to prevent the back surface of the substrate from being eroded and peeling off in the subsequent steps, it will cause other substrates in the same batch to be affected. 6 scales are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) _ (Please read the precautions on the back before filling out this page) Installation -------- Order ------- -· 515072 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of Invention b) contamination. The following example will use the multi-metal connection process to form a multi-metal connection on the substrate after the main components of the ultra-large integrated circuit have been completed, and use tungsten metal as the material of the plug to illustrate the technology of the present invention. means. Investigate the reason for the formation of tungsten metal on the back of the substrate. As shown in Figure 1, when the chemical vapor phase reaction (CVD) is performed, the wafer is placed in the crystal base 11 of the reaction machine for reaction, and the reaction gas is tungsten fluoride. (WF6) and sarane (SiHLO or hydrogen (H2) are released from the aerosol structure 12, and the heater 2 is used to make the entire reactor reach the required reaction temperature. During the reaction, the substrate can be fixed to the crystal base 11 In the process, vent holes 5 and 6 will be formed below the crystal base 11. The above-mentioned vent holes 5 and 6 are connected to the pump pump 1 through a gas valve 8 to reduce the pressure and use a pressure difference to fix the substrate to the crystal base. 11. After the reaction is completed, the front and back pressures of the substrate need to be adjusted to the same, so the gas valve 8 is closed, and the gas valve 9 is opened to release a passive gas such as argon (Ar) to adjust the pressure. Using an external gas such as argon to adjust the pressure on the front and back of the substrate is inaccurate. Therefore, the gas valve 10 will be opened to release the reaction gas that was only on the front of the substrate through the vent pipe 7 to the back of the substrate to make the pressure truly reach equilibrium. After entering the reaction gas, there is tungsten gold It is deposited near the vent hole 7 on the back surface of the substrate, which results in the partial deposition of tungsten metals 70 and 71 on the back surface of the substrate, as shown in Figure 2. Therefore, tungsten metals 70 and 71 are used as a hard cover in the conventional technology. The problem of engraving to the silicon oxide layer; The above tungsten metal can be other metal materials such as aluminum (A1). It is pointed out that the formation of tungsten metal can be formed by three kinds of pipes: 1. WF6 + SiH4- > Ww + SiF4 + 2HF + H2 7 -------.----- φ-pack ------ (Please read the precautions on the back before filling this page) Order -------- This paper Standards are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) 515072 A7 Intellectual Property Bureau staff fee cooperation V. Invention description (/) 2. WF6 + 3H2- > W (S) + 6HF 3. 2WF6 + The 3Si ^ 2W (s) + 3SiF4 reaction gas will deposit tungsten metal near the vent holes 7 on the back of the substrate. When tungsten metal is deposited on the front side of the substrate during the semiconductor process, it is inevitable that tungsten metal will be deposited on the part of the substrate. The invention is that before the formation of tungsten metal on the back of the substrate, a silicon oxide layer 200 is deposited to protect the polycrystalline silicon layer 22 below it. The metal pattern is corroded by the developer used, so that there will be no unevenness of the substrate in the conventional technology. The manufacturing method is as follows. First, please refer to FIG. 4 to provide a substrate 20, which The above-mentioned substrate 20 has completed the active device (not shown), and only the back surface of the substrate is shown in the schematic cross-sectional view of the process of FIG. 4 because the focus of the present invention is to maintain the integrity of the back surface of the substrate; Therefore, it is necessary to deposit various conductive or non-conductive thin films, so a multi-layer structure is formed on the back surface of the substrate. In this embodiment, only the silicon oxide thin layer 21 and the polycrystalline silicon layer 22 are deposited on the back surface of the substrate 20. The reason for the leveling is caused by the polycrystalline layer 22 and the oxidized sand thin layer 21 located at the outermost layer being saturated. The multilayer structure under the silicon oxide thin layer 21 is used to make spacers, hard masks and gate structures. (gate structure) is deposited on the back surface of the substrate. The present invention can also be applied to static random access memory (SRAM), and the above-mentioned thin oxide sand layer 21 is a two-layer oxide sand structure (not shown in the figure. 7) The substrate 20 is formed by sputtering (please read the precautions on the back before filling this page). II --------- #. This paper size is applicable to China National Standard (CNS) A4 specifications ( (210 X 29 / mm) 515072 Printed on clothing A7 B7 by a member of the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives V. Description of the invention (i) The first is a metal layer, and the photolithography (resist) is used to define it The first layer of metal wire structure (not shown) is formed. The material of the first layer of metal layer is one of aluminum copper alloy (AlCu) and aluminum (A1). (02) Plasma, which is a reactive gas, forms a silicon oxide layer 200 on the polycrystalline silicon layer 22, and the thickness of the formed silicon oxide layer 200 is greater than 10 angstroms. Because the silicon oxide layer 200 is described above, The polycrystalline silicon layer 22 is protected, and the substrate is placed in a developing solution in the subsequent process steps. The first metal wire structure is defined. The developer has a low etching efficiency for the silicon oxide layer 200 when the reaction temperature is less than 105 ° C. Therefore, the polycrystalline silicon layer 22 can be protected from the tungsten metal layer 23 as The etching mask performs the etching operation of the polycrystalline silicon layer 22 and the silicon oxide thin layer 21. Next, a tungsten metal layer is formed by using a chemical vapor deposition method (CVD) to make a tungsten metal plug for connecting two wire structures. During the tungsten metal plug process, tungsten metal 23 is also deposited on the back surface of the substrate. Since the surface of the polycrystalline silicon layer 22 is protected by a thin layer of sand oxide 200, the tungsten metal 23 is not directly deposited on the polycrystalline silicon layer 22, therefore, No conventional technical problems will occur; the above-mentioned material for making the plug can also be replaced by other materials such as indium copper alloy (AlCu) or indium (A1). In this way, the material is directly deposited on the polycrystalline stone layer 22 The metal is an aluminum-copper alloy (AlCu) or aluminum (A1). In summary, the conventional technique provided by the present invention has the following advantages: 1. The present invention has more oxidation than the conventional technique before depositing a metal plug. Thin layer of silicon As an etching stop layer during the development process defining a metal structure, it prevents damage to the polycrystalline silicon layer underneath. 2. The present invention does not suffer from the etching phenomenon of polycrystalline silicon layer and silicon oxide layer, because this paper scale applies Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) (Please read the precautions on the back before filling out this page) Installation 515072 A7 B7 V. Description of the invention () There will be no unevenness of the substrate, which will cause difficulties in lithography. 3 · The invention does not suffer the engraving phenomenon of the polycrystalline sand layer and the oxidized sand layer. Therefore, the polycrystalline sand layer and the oxidized chopped layer will not peel off and contaminate the substrates of the same batch of goods, which improves the yield and reduces the production cost. The above description uses the preferred embodiments to explain the present invention in detail, but not to limit the scope of the present invention. Therefore, those skilled in the art should understand that appropriate changes and adjustments will still make the essence of the present invention. Without departing from the spirit and scope of the present invention, it should be regarded as a further implementation of the present invention. _I ask your reviewing committee to make a clear reference and pray for your sincere prayer. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ TCNS) A4 Regulation 1 ^ 210 X 297 mm)