A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（f ) 發明領域： 本發明係關於一種積體電路中金屬層蝕刻的方法，特 別是關於—種高深寬比(aspect ratio;深度/寬度)之金 屬層蝕刻方法，可減少光阻厚度以增加解析度，亦可以較 少的金屬層厚度承受較大的電流。 發明背景： 積體電路製程大部份是屬於次微米的尺寸，是一種在 矽晶圓上刻畫極細圖案的技術。以目前半導體技術的發 展’在矽晶圓之上製作半導體元件，線寬的尺寸都小於1 微米’刻畫這種微細線寬的方法，是必須使用微影與触刻 麵。 在矽晶圓之上製作一條細線，首先需在表面塗佈光 阻’然後用微影製程定義細線區域。當細線的尺寸小於某 一尺寸’在曝光的製程中，便很容易產生繞射效應，改變 晶圓上的積體電路圖案，影響積體電路製作的良率(yield) 與可靠度(reliability)。在微影過程中產生繞射效應的原 因’不外是光源波長過長、光阻層較厚與線寬較窄。當積 體電路的製作朝向高積集度的方向，線寬一定是必須逐漸 減小，所以利用減小線寬來避免繞射效應是不可能的》縮 短微影製程的曝光光源的波長，是可以有效降低繞射效應 的發生，但是欲更換曝光光源的種類，必須花費大筆的金 錢與時間，而且並非在積體電路製作過程的每一道微影過 程，都必須符合最小線寬的限制，所以更換曝光光源是一 項有效但非必要的手段。於是，朝向降低光阻厚度的方向 0 _---Ί— ^---裝 II 訂 _ ^ 線 / '' (請先聞讀背面之注意事項再产，_:'本頁) ί 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (f) Field of the Invention: The present invention relates to a method for etching metal layers in integrated circuits, and in particular to an aspect ratio (depth) / Width) metal layer etching method, which can reduce the thickness of the photoresist to increase the resolution, and can bear a larger current with less metal layer thickness. Background of the Invention: Most of the integrated circuit manufacturing process is a sub-micron size, which is a technology for engraving extremely fine patterns on silicon wafers. According to the current development of semiconductor technology, “Semiconductor devices are fabricated on silicon wafers, and the line widths are all smaller than 1 micron.” The method of characterizing such fine line widths requires the use of lithography and touch facets. To make a thin line on a silicon wafer, firstly, a photoresist is coated on the surface, and then a lithography process is used to define the thin line area. When the size of the thin line is smaller than a certain size, in the exposure process, it is easy to produce a diffraction effect, change the integrated circuit pattern on the wafer, and affect the yield and reliability of the integrated circuit production. . The reason for the diffraction effect in the lithography process is that the wavelength of the light source is too long, the photoresist layer is thick and the line width is narrow. When the fabrication of integrated circuits is oriented towards high integration, the line width must be gradually reduced, so it is impossible to avoid the diffraction effect by reducing the line width. "Short the wavelength of the exposure light source for the lithography process is It can effectively reduce the occurrence of diffraction effects, but to change the type of exposure light source, it must cost a lot of money and time, and not every lithography process in the integrated circuit manufacturing process must meet the minimum line width limit. So changing the exposure light source is an effective but not necessary means. Therefore, in the direction of reducing the thickness of the photoresist, 0 _--- Ί— ^ --- binding II order _ ^ line / '' (Please read the precautions on the back to reproduce, _: 'this page) ί This paper Applicable to China National Standard (CNS) A4 specification (210X297 mm)
A7 > · __， _B7_ 五、發明説明（>) 前進，便是一種最有效的方法。降低光阻的厚度，僅需在 塗佈光阻的製程中’控制相關的變數’便能達到控制厚度 的目的，可是在後續的蝕刻製程中，蝕刻積體電路膜層的 反應電漿’會造成光阻層厚度的損失，當光阻層的損失過 大，積體電路的圖案會遭受到蝕刻侵襲，於是圖案的轉移 失去準確性，金屬層的材料也會遭受到破壞，會降低積體 電路生產的良率。 在矽晶圓的表面製作記憶體元件，在後續的製程中必 須製作金屬內連線，將晶圚表面的記憶體元件連接起來， 以形成記憶體元件陣列。當積體電路製程進入次微米或深 次微米製程’積體電路元件的集積密度(packing density) 快速增加’而各層的厚度也顯著減小，各微影步驟所覆蓋 的光阻也較傳統技術變薄許多。由於金屬對光阻之蝕刻選 擇比(etching selectivity)不佳，造成光阻在金屬層蝕刻 過程中會受到蝕刻電漿離子的傷害而逐漸變薄。若所述光 阻太薄’則容易被蝕刻金屬層的離子打穿，無法達到阻隔 離子的功效。 爲解決所述之困難，硬式護罩(Hard Mask)之製程已被 廣泛使用於積體電路之製造業界。請參考圖一A，爲一習知 金屬內連線的剖面示意圖，是在已完成部份前段製程之晶 圓1上，利用濺鍍技術形成擴散阻障層（Diffusion Barrier)2、銘合金層3和抗反射層（Anti-Reflective Coating ; ARC)4後，形成所謂的硬式護罩5，即是沉積一層 氧化砍(oxide)或是氮化砂(nitride)薄膜在抗反射層上， 本纸張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） —Ί. _ ：-----t..-- (請t閲讀背面之注意事項再填@頁) A7 B7 經濟部中央標準局員工消費合作杜印製 五、發明説明（]) 然後塗佈上光阻6，再利用微影技術定義出金屬內連線的位 置，以離子蝕刻技術去除未被光阻覆蓋之氧化矽(如圖一B 所示）；接著’再以此氧化矽層5和光阻6做爲蝕刻之保護 罩’利用離子蝕刻技術去除未被光阻覆蓋之抗反射層4、鋁 合金層3和擴散阻障層2，以製作出金屬內連線，如圖一c所 示(光阻厚度仍會損失）；然後最後再去除光阻6，所欲之金 屬內連線於焉完成。由於金屬對氧化矽之蝕刻選擇比較金 屬對光阻之蝕刻選擇比佳，因此可降低所需覆蓋之光阻厚 度而減低微影製程之困難度，以達到增加集積密度之目 的。 然而’在小於G. 25微米的製程中，高深寬比的金屬蝕 刻製程是無法避免的，即使是使用了硬式護罩，仍須塗佈 相當厚的光阻，因爲光阻在高深寬比金屬層蝕刻過程φ胃 受到蝕刻離子的傷害而逐漸被削薄(如圖一C中所示），光阻 必須夠厚才可避免傷害金屬層結構，但顧及了金屬層 整，就勢必得犧牲光阻解析能力，也因此高深寬比 蝕刻製程需要用到高成本深紫外線(De印UV)光阻以提昇解 析度；而且，做爲硬式護罩的氧化矽對於金屬的鈾麥』選胃 比(約3. 5 : 1)在高深寬比的金屬蝕刻製程中，仍嫌不足， 硬式護罩亦會受到蝕刻離子的傷害。因此，本發明將針對 上述光阻厚度及蝕刻選擇比的問題，提供改善的方法。 發明之概述： 本發明之主要目的是提供一種積體電路之高深寬比金 屬層蝕刻的方法，利用金屬層表面的鎢層作爲硬式護罩， 4 I .-1- I. ^ I I 裝— I I I 訂 ； I 線 (請*,'閱讀背面之注意事項再本頁) 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐）A7 > · __, _B7_ 5. Explanation of the invention (>) Moving forward is one of the most effective methods. To reduce the thickness of the photoresist, it is only necessary to 'control related variables' in the process of coating the photoresist to achieve the purpose of controlling the thickness. However, in the subsequent etching process, the reaction plasma of the integrated circuit film layer will be etched. Causes the loss of the thickness of the photoresist layer. When the loss of the photoresist layer is too large, the pattern of the integrated circuit will be attacked by etching, so the pattern transfer loses accuracy, and the material of the metal layer will also be damaged, which will reduce the integrated circuit Yield of production. A memory element is made on the surface of the silicon wafer. In subsequent processes, metal interconnects must be made to connect the memory elements on the surface of the wafer to form a memory element array. When the integrated circuit process enters the sub-micron or deep sub-micron process, the "packing density of integrated circuit elements increases rapidly" and the thickness of each layer is also significantly reduced. The photoresist covered by each lithography step is also more traditional than that Thinner. Due to the poor etching selectivity of the metal to the photoresist, the photoresist will be gradually thinned by the etch plasma ions during the metal layer etching process. If the photoresist is too thin, it is easily penetrated by the ions of the etched metal layer, and the effect of blocking ions cannot be achieved. In order to solve the above-mentioned difficulties, the manufacturing process of the hard mask has been widely used in the manufacturing industry of integrated circuits. Please refer to FIG. 1A, which is a schematic cross-sectional view of a conventional metal interconnect. On a wafer 1 that has been partially completed in the previous stage, a diffusion barrier layer 2 and an alloy layer are formed by sputtering technology. 3 and an anti-reflective coating (ARC) 4 to form a so-called hard shield 5, which is to deposit an oxide or nitride film on the anti-reflective layer. Zhang scale is applicable to China National Standard (CNS) A4 specification (210X297 mm) —Ί. _: -------- t ..-- (Please read the notes on the back and fill in @page) A7 B7 Central Standard of the Ministry of Economic Affairs Printed by the staff of the Bureau of Du, Co., Ltd. 5. Description of the invention (]) Then apply photoresist 6 and then use lithography to define the position of the metal interconnects. Ion etching technology is used to remove silicon oxide that is not covered by photoresist ( (As shown in Fig. 1B); then 'the silicon oxide layer 5 and the photoresist 6 are used as a protective cover for etching' using the ion etching technology to remove the anti-reflection layer 4, the aluminum alloy layer 3 and the diffusion resistance which are not covered by the photoresist Barrier layer 2 to make metal interconnects, as shown in Figure 1c (the thickness of the photoresist will still be damaged ); And finally removing the photoresist 6, the desired metal interconnect in Yan completed. Since the etching selection of metal to silicon oxide is better than that of metal to photoresist, the thickness of the photoresist to be covered can be reduced and the difficulty of the lithography process can be reduced to achieve the purpose of increasing the accumulation density. However, in a process smaller than G. 25 microns, a high aspect ratio metal etching process is unavoidable. Even if a hard cover is used, a thick photoresist must be applied because the photoresist is in a high aspect ratio metal. In the process of layer etching, the stomach is gradually thinned by the damage of the etching ions (as shown in Figure 1C). The photoresist must be thick enough to avoid damaging the metal layer structure. However, considering the metal layer integration, it is bound to sacrifice light. Resistance analysis ability, so the high aspect ratio etching process requires the use of high-cost deep ultraviolet (De printed UV) photoresist to improve the resolution; moreover, silicon oxide as a hard shield to metal uranium wheat About 3.5: 1) In the metal etching process with high aspect ratio, it is still insufficient, and the hard shield will also be damaged by the etching ions. Therefore, the present invention provides an improved method for the problems of the photoresist thickness and the etching selection ratio. Summary of the invention: The main object of the present invention is to provide a method for etching a high-aspect-ratio metal layer of an integrated circuit. The tungsten layer on the surface of the metal layer is used as a hard shield. 4 I .-1- I. ^ II 装 — III Order; I line (please *, 'read the notes on the back, and then this page) This paper size applies to Chinese national standards (CNS > A4 specification (210X297 mm)
I A7 B7I A7 B7
經濟部中央標準局員工消費合作社印製 五、發明説明（斗） 可有效減少在微影製程中所塗佈的光阻厚度，有效的將金 屬連線圖案轉移至金屬層的表面。 本發明之次一目的是提供一種積體電路之高深寬比金 屬層蝕刻的方法，可有效降低在微影製程中所塗佈光阻的 厚度，以提高黃光光阻解析能力，故可使用較低成本的黃 光光阻（I-line .PR) β 本發明之另一目的是提供一種積體電路之高深寬比金 屬層蝕刻的方法，利用具有較好電子遷移 (electronmigration)特性的鎢爲硬式護罩，可減少金屬層 之厚度且可承受較大電流。 本發明之再一目的是提供一種積體電路之高深寬比金 屬層蝕刻的方法，利用金屬層表面的鎢層作爲硬式護罩， 以提供更佳的鶴對於金屬之蝕刻選擇比。 . 本發明的又一目的是提供一種積體電路之高深寬比金 屬層蝕刻的方法，可在同一蝕刻機台對鎢層與金屬層進行 蝕刻，形成圖案準確的金屬連線圖案。 本發明是利用下列技術手段來達到上述之各項目的： 首先，在已完成前段製程的晶圓上形成一金屬層；接著， 形成鎢硬式護罩及一層氧化氮化矽層；隨後利用光阻定義 出金屬內連線的位置，並進行第一次蝕刻’移除未被光阻 覆蓋的氧化氮化矽層及鎢硬式護罩；再接著’進行第二次 蝕刻，移除未被覆蓋的鋁合金層及擴散阻障層；最後，移 除光阻，以形成金屬內連線。 圖式簡要說明： 本紙浪尺度適用中國國家標準（CNS ) A4規格（210乂297公釐） (請先閲讀背面之注意事項'¾本頁) 裝· 五、發明説明（丄） A7 B7 圖一 A〜C是習知技藝中進行高深寬比金屬層蝕刻的剖 面示意圖。 圖二A〜D是本發明實施例中，以新的金屬層結構進行 高深寬比金屬層蝕刻的剖面示意圖。 圖號說明： 1- 基板 3- 銘合金層 5- 氧化矽硬式護罩 10-基板 30-鋁合金層 50-氧化氮化矽層 100-硬式護罩蝕刻 1000-硬式護罩蝕刻 2- 擴散阻障層 4- 抗反射層 6 - 光阻 20-擴散阻障層 40-鎢硬式護罩 60-光阻 200-金屬層蝕刻 2000-金屬層蝕刻 經濟部中央標準局員工消費合作社印製 發明詳細說明： 請參閱圖二A，首先在已完成前段製程的半導體基板 上，利用金屬濺鍍(Sputter Deposit ion)技術形成金屬層’ 依序包括擴散阻障層(Diffusion Barrier)2G、鋁合金層 30，並沉積鎢〇〇硬式護罩40於所述鋁合金層30表面。然 後，沉積一層抗反射層50後，再將光阻60塗佈在所述抗反 射層50表面，以微影製程技術定義出金屬內連線的位置。 所述擴散阻障層20通常是由鈦/氮化鈦(Ti/TiN)雙層 結構、氮化鈦或鎢化鈦(TiW)所構成，其目的是做爲鋁和矽 的緩衝，以避免尖峰(Spiking)現象的發生；所述鋁合金層 30通常是鋁銅(AlCu)合金或是鋁矽銅(AlSiCu)合金；所述 ----^-------,---裝----- -，.訂-------線 - /} . _ . (請先閲讀背面之注意事項再本頁) 本紙張尺度適用中國國家榡準（CNS > A4規^· ( 2H)X297公釐〉Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (bucket) can effectively reduce the thickness of the photoresist applied in the lithography process and effectively transfer the metal connection pattern to the surface of the metal layer. A secondary object of the present invention is to provide a method for etching a high-aspect-ratio metal layer of an integrated circuit, which can effectively reduce the thickness of the photoresist applied in the lithography process, so as to improve the yellow photoresist resolution capability, so it can be used relatively low Cost yellow photoresist (I-line .PR) β Another object of the present invention is to provide a method for etching a high-aspect-ratio metal layer of an integrated circuit, using tungsten with a better electronimigration characteristic as a hard shield. , Can reduce the thickness of the metal layer and can withstand larger currents. Another object of the present invention is to provide a method for etching a high-aspect-ratio metal layer of an integrated circuit, which uses a tungsten layer on the surface of a metal layer as a hard cover to provide a better crane-to-metal etching selection ratio. Another object of the present invention is to provide a method for etching a high-aspect-ratio metal layer of an integrated circuit, which can etch a tungsten layer and a metal layer in the same etching machine to form a metal wiring pattern with an accurate pattern. The present invention uses the following technical means to achieve the above-mentioned objects: first, a metal layer is formed on the wafer that has completed the previous process; then, a tungsten hard shield and a silicon oxide nitride layer are formed; and then a photoresist is used Define the location of the metal interconnects and perform the first etch to 'remove the silicon oxide nitride layer and tungsten hard cover that are not covered by photoresist; then proceed to the second etch to remove the uncovered The aluminum alloy layer and the diffusion barrier layer; finally, the photoresist is removed to form a metal interconnect. Brief description of the drawings: The scale of this paper applies the Chinese National Standard (CNS) A4 specification (210 乂 297mm) (please read the precautions on the back first '¾ this page) Installation · 5. Description of the invention (丄) A7 B7 Figure 1 A to C are schematic cross-sectional views of etching a high-aspect-ratio metal layer in a conventional technique. Figs. 2A to 2D are schematic cross-sectional views of etching a high-aspect-ratio metal layer with a new metal layer structure in an embodiment of the present invention. Description of drawing number: 1- substrate 3-alloy layer 5-silicon oxide hard cover 10-substrate 30-aluminum alloy layer 50-silicon nitride oxide layer 100-hard cover etching 1000-hard cover etching 2- diffusion resistance Barrier layer 4-Anti-reflective layer 6-Photoresist 20-Diffusion barrier 40-Tungsten hard cover 60-Photoresist 200-Metal layer etching 2000-Metal layer etching Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs : Please refer to FIG. 2A. First, a metal layer is formed on the semiconductor substrate that has completed the previous process by using the Sputter Deposit ion technology. The diffusion barrier layer 2G and the aluminum alloy layer 30 are sequentially included. A tungsten oo hard shield 40 is deposited on the surface of the aluminum alloy layer 30. Then, after depositing an anti-reflection layer 50, a photoresist 60 is coated on the surface of the anti-reflection layer 50, and the position of the metal interconnects is defined by the lithography process technology. The diffusion barrier layer 20 is usually composed of a titanium / titanium nitride (Ti / TiN) double-layer structure, titanium nitride or titanium tungsten (TiW), and its purpose is to serve as a buffer for aluminum and silicon to avoid The occurrence of a spike phenomenon; the aluminum alloy layer 30 is usually an aluminum-copper (AlCu) alloy or an aluminum-silicon-copper (AlSiCu) alloy; the ---- ^ -------, --- Loading ------,. Ordering ------- line- /}. _. (Please read the precautions on the back before this page) This paper size applies to China National Standards (CNS > A4 regulations ^ ((2H) X297mm>
I 經濟部中夬標隼局員工消費合作社印製 A7 B7__ 五、發明説明（ς) 鎢硬式護罩層40通常是以低壓化學氣相沉積法（Low Pressure Chemical Vapor Deposition ; LPCVD)所形成； 所述抗反射層50通常是由非晶砂(Amorphous Silicon ; α-Si)、或氧化氮化矽(oxynitride)所構成。而所述光阻60可 採用一般的黃光光阻。 接下來，以光阻60做爲保護層，進行抗反射層5G及鎢 硬式護罩4G之蝕刻1000，係採用電漿蝕刻技術(Plasma Etching)，其反應氣體是以氟化物氣體爲主(F-based)，請 參閱圖二B ;再接著，對金屬層進行蝕刻2000以製作出金屬 內連線，可利用同一蝕刻機台，進行電漿蝕刻，其反應氣 體則是以氯化物氣體爲主(Cl-based)，形成如圖二C中之結 構，光阻60因蝕刻離子的撞撃而被削尖變薄。 最後，請參閬圖二D，去除光阻及抗反射層，形成由擴 散阻障層20、鋁合金層30、及鎢硬式護罩40所組成的金屬 內連線之金屬層結構。 本發明之重點在於採用鎢做爲硬式護罩，因爲鋁合金蝕 刻是使用以氯化物氣體爲主(Cl-based)的電漿蝕刻，因此 鎢對鋁合金之蝕刻選擇比相當高，大約爲習用氧化物硬式 護罩對鋁合金之蝕刻選擇比的3倍，而且鋁合金層之上覆 蓋一層鎢，與鋁合金層本身相比較，可具有較佳的電子遷 移阻抗能力(electromigration resistance)。基於上述鎢 硬式護罩對鋁合金之高蝕刻選擇比，因此鎢硬式護罩可部 份代替光阻的作用，而達到減少光阻厚度的目的，其中光 阻厚度的減少將視鎢硬式護罩的厚度而定，lk埃的鎢層大 --—_7____ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） | ^ Γ H 1111 n-'1 訂 線 (#先閲讀背面之注意事項再/幻本頁) . A7 B7 五、發明説明（7 ) 約可減少5. 5k埃的光阻厚度，故本發明之高深寬比金屬層 蝕刻製程可使用成本較低的黃光光阻(I-line PR)，較習用 深紫外線光阻(DUV PR)製程可節省約50%之成本。另外，利 用具有較好電子遷移特性的鎢爲硬式護罩，可減少金屬層 之厚度且可承受較大電流，是一般習用非導體之硬式護罩 所沒有的特性。 以上所述係利用較佳實施例詳細說明本發明，而非限制 本發明的範圍，因此熟知此技藝的人士應能明瞭，適當而 作些微的改變與調整，仍將不失本發明之要義所在，亦不 脫離本發明之精神和範圍，故都應視爲本發明的進一步實 施狀況。謹請貴審查委員明鑑，並祈惠准，是所至禱。 .--^---=---屬-- 、 /、 (請先閲讀背面之注意事項再填萬本頁) 經濟部中夬標準局員工消費合作杜印製 本紙浪尺度適用中國國家標準（CNS ) A4規格（210X297公釐）I Printed by A7 B7__ in the Consumers' Cooperative of the Ministry of Economic Affairs of the Ministry of Economic Affairs of the People's Republic of China V. Description of Invention (ς) The tungsten hard cover layer 40 is usually formed by the Low Pressure Chemical Vapor Deposition (LPCVD) method; The anti-reflection layer 50 is usually made of amorphous sand (α-Si) or oxynitride. The photoresist 60 may be a general yellow photoresist. Next, the photoresist 60 is used as the protective layer, and the anti-reflection layer 5G and tungsten hard cover 4G are etched 1000. Plasma Etching is used. The reaction gas is mainly fluoride gas (F -based), please refer to Figure 2B; then, the metal layer is etched 2000 to produce metal interconnects. Plasma etching can be performed using the same etching machine, and the reaction gas is mainly chloride gas. (Cl-based), the structure shown in Figure 2C is formed, and the photoresist 60 is sharpened and thinned by the collision of etching ions. Finally, please refer to Figure 2D to remove the photoresist and anti-reflection layer to form the metal layer structure of the metal interconnects composed of the diffusion barrier layer 20, the aluminum alloy layer 30, and the tungsten hard shield 40. The focus of the present invention is to use tungsten as a hard shield. Because aluminum alloy etching is based on chloride-based plasma etching, the etching selection ratio of tungsten to aluminum alloy is quite high, which is about customary. The oxide hard shield has 3 times the etching selectivity ratio of aluminum alloy, and the aluminum alloy layer is covered with a layer of tungsten. Compared with the aluminum alloy layer itself, it can have better electron migration resistance. Based on the high etching selection ratio of the tungsten hard shield to aluminum alloy, the tungsten hard shield can partially replace the role of the photoresist to achieve the purpose of reducing the thickness of the photoresist. The reduction of the thickness of the photoresist will depend on the tungsten hard shield. Depending on the thickness, the tungsten layer of lk Angstrom is large ---_ 7____ This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) | ^ Γ H 1111 n-'1 (Notes again / Magic page). A7 B7 V. Description of the invention (7) The photoresist thickness can be reduced by about 5.5k angstroms, so the low-cost yellow photoresist can be used for the high aspect ratio metal layer etching process of the present invention ( I-line PR), which can save about 50% of the cost compared with the conventional deep UV photoresist (DUV PR) process. In addition, the use of tungsten with good electron migration characteristics as a hard cover can reduce the thickness of the metal layer and can withstand large currents, which is a feature that is not commonly used in non-conductive hard covers. The above description uses the preferred embodiments to explain the present invention in detail, but not to limit the scope of the present invention. Therefore, those skilled in the art should be able to understand that making appropriate changes and adjustments will still not lose the essence of the present invention. Without departing from the spirit and scope of the present invention, it should be regarded as a further implementation status of the present invention. I would like to ask your reviewers to make a clear reference and pray for your sincere prayer. .-- ^ --- = --- genus-, /, (Please read the notes on the back before filling in this page) Employee consumption cooperation with China Standards Bureau, Ministry of Economic Affairs (CNS) A4 specification (210X297 mm)
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