TW515059B - A leadframe and semiconductor package - Google Patents

A leadframe and semiconductor package Download PDF

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Publication number
TW515059B
TW515059B TW090125920A TW90125920A TW515059B TW 515059 B TW515059 B TW 515059B TW 090125920 A TW090125920 A TW 090125920A TW 90125920 A TW90125920 A TW 90125920A TW 515059 B TW515059 B TW 515059B
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Taiwan
Prior art keywords
leads
lead frame
loading
lead
embedded
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TW090125920A
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Chinese (zh)
Inventor
Wai Wong Chow
Fei Ying Wong
Man Hon Cheng
Wai Keung Ho
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Motorola Inc
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Publication of TW515059B publication Critical patent/TW515059B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A leadframe (4) for a semiconductor package (22) is disclosed. The leadframe (4) has a plurality of tie bars (12) defining a perimeter of the leadframe (4). The leadframe (4) has a plurality of leads (10) inwardly extending from an associated tie bar (12). The leads (10) has circuit board mounting surfaces (15) aligned in a common mounting plane. Each of the mounting surfaces (15) being spaced from the tie bars (12). Each lead has a recessed surface (21) adjacent an associated tie bars (12). The recessed surface (12) is misaligned from the mounting surface such that during singulation of the leadframe (4) burrs extending from the recessed surface (21) do not cross the mounting plane.

Description

五、發明説明（ 發明摘要 本發明大致上與引線框架及半導體封裝相關，且更特定 地與4面平整無引線（QFN)型之半導體封裝及用於製造該封 裝之引線框架相關。 發明背景 Q封裝之組裝通常包括使用包含多種引線框架之引線 框架面板。每個引線框架具有複數個引線和繫桿。引線從 :目關之繫桿向内延伸。引線具有電路板裝載平面排列在共 同裝載平面中。繫桿支撐引線且連接該引線框架在面板^ 。有些引線也包括貼在繫桿其中之一之標記部份。在qfn 封裝之組裝期間’半導體晶片貼至標記部份。使用金線或 是連接器連接在半導體晶片上之片黏結墊至相對應之引 線。使用密封物至少部份地密封該半導體晶片、金線以及 引線以形成完整之QFN封裝。 為了產生個別化之QFN封裝，引線框架面板藉由沿著繫 桿鑛開以分離QFN封裝以及在每個封裝上之引線而切單。 鋸開產生毛邊在引線之被鑛開部份。這些毛邊突出超過共 同裝載平面。當裝載這樣之封裝在印刷電路板（MB)時，這 些毛邊導致共平面性問題。因為毛邊之不規則形狀，引線 之裝載平面不再與PCB表面共平面。戶斤以該裝載表面並不 均句地位於PCB表面上。隨後有些引線與在pcB上之連接墊 並不是適合地接觸以允許銲錫連接。 易於發生這樣問題之半導f 4 +等體封裝之範例係為顯示在美國 專利5,973,388及5,894，1〇8中的這些。 -4 本紙乐尺度適用中國國家標準(CNS) A4規格（210X297公ϋ A7V. Description of the Invention (Summary of the Invention The present invention is generally related to lead frames and semiconductor packages, and more specifically to 4-sided flat leadless (QFN) type semiconductor packages and lead frames used to manufacture the packages. Background of the Invention Q Package assembly usually involves the use of a lead frame panel containing multiple lead frames. Each lead frame has a plurality of leads and tie rods. The leads extend inward from the tie rods. The leads have a circuit board loading plane arranged on a common loading plane. Medium. The tie rod supports the lead and connects the lead frame to the panel ^. Some leads also include a marked portion attached to one of the tie rods. 'Semiconductor wafer is pasted to the marked portion during the assembly of the qfn package. The connector is a piece of bonding pad connected to the semiconductor wafer to the corresponding lead. The semiconductor wafer, gold wire and lead are at least partially sealed with a sealant to form a complete QFN package. In order to produce individualized QFN packages, the leads The frame panel is singulated by mining along the tie bars to separate the QFN package and the leads on each package. The burrs are generated in the mined portions of the leads. These burrs protrude beyond the common loading plane. When mounting such a package on a printed circuit board (MB), these burrs cause coplanarity problems. Because of the irregular shape of the burrs, the leads The loading plane is no longer coplanar with the PCB surface. The load surface is not evenly located on the PCB surface. Then some leads are not in proper contact with the connection pads on the pcB to allow solder connection. This is easy to happen Examples of problematic semiconducting f 4 + isobody packages are those shown in U.S. Patents 5,973,388 and 5,894,108. -4 This paper scale applies the Chinese National Standard (CNS) A4 specification (210X297 public A7)

根據本發明之一觀點，提 Α 供牛導封裝之引線框架。該 I線框架具有定義該引線框牟 H木周長之禝數個繫桿。該引線 框架具有從該繫桿相關之一夕A + 關之t向内延伸之複數個引線。該 弓I線具有電路板裝載表面排列在Α W〜仕共冋裝载平面中且每個該 裝載表面與該繫桿間隔開。該引 引綠也具有甘欠入表面相鄰該 繫桿相關之一。該嵌入表面愈續奘都 ^田/、4裝載表面錯置使得在該引 線框架之切單期間，從該嵌志 t入表面延伸之毛邊並不跨越該 裝載平面。 適當地’該引線框架可以包括貼至至少一該複數個繫桿 之標記部份。 -適當地，該嵌入表面可以藉由 曲該複數個引線而與該 裝載表面錯置。 適當地，該嵌入表面可以藉由割開、切除或是蝕刻該複 數個引線而與該裝載表面錯置。 較佳地，該嵌入表面可以藉由割開、切除或是蝕刻該複 數個引線足夠地而與該裝載表面錯置以允許該密封物以密 封該嵌入表面。 根據本發明之另一觀點，提供半導體封裝，其包括 具有晶片黏結墊和引線電氣地連接至相對應之晶片黏結 墊之半導體晶片。該引線具有電路板裝載表面排列在共同 裝載平面中。該引線也具有散入表面相鄰該封裝之周邊。 該封裝也包括密封物至少部份地密封該晶片和引線。該嵌 入表面與該裝載表面錯置且從該嵌入表面延伸之毛邊並不 -5-本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) A7 B7 五、發明説明（3 ) 跨越該裝載平面。 適當地，該丰墓舻#壯 ^ V體封裝可以包括該半導體晶片附著之標 記部份。 圖式簡述 本^月可以被谷易地了解且放進實際之效果，將會 參考較佳具體實施例，如同參照隨附圖式而說明，其中： 圖1係為弓|線框架面板之部份之頂部平面檢視圖，其顯 不單一完全弓丨線框架和鄰接之引線框架之部份； 圖2係為圖！之引線框架面板部份之底面部份之立體圖， 其顯示表面嵌入以產生根據本發明之第一具體實施例之引 線框架； -圖2A係為沿著線B_B圖2之引·^架之部份之剖面檢視 圖； 圖3係為從圖2之引線框架製造之半導體封裝之剖面檢視 圖；及 圖4係為從根據第二具體實施例之引線框架製造之另一 半導體封裝之剖面檢視圖。 發明之具體貫施例之詳細說明 圖1顯示具有複數個引線框架4之引線框架面板2之部份 。每個該複數個引線框架4，其由虛線所圍住而顯示，具 有定義每個引線框架4周長之繫桿12。繫桿12支援標記部份 8以及相關引線1〇。每個引線10具有内部部份14以及外部部 份16。繫桿12藉由連接外部部份16支撐引線1〇。繫桿丨2也 連接個別引線框架4在引線框架面板2上。引線1〇之内杳立 -6- 515059 A7 _______B7 五、發明説明(~~ " ~-~ 份Η從相關繫桿12向内延伸。内部部份叫有排列在由圖 2A線A-A所指示之共同裝載平面之電路板裝載表面15。電 路板裝載表面15從繫桿12相關之一隔開。 圖2係為顯示具有嵌入之表面18之引線框架面板2之部份 之立體圖。引線框架面板2從已經被钱刻、切割或是壓: 以形成圖案之薄金屬（例如，銅）片形成，如圖以斤顯示。 引線框架面板2之表面18被嵌入以提供沿著繫桿12之縱軸之 溝20。引線框架面板2可以被蝕刻或是彎曲以產生溝2〇。圖 2顯示具有溝20之引線框架面板2之部份。每個溝2〇擴張繫 才干12的整個寬度且延伸在引線1 〇之外部部份16。 溝2 〇之端對端寬度W應該比用於引線框架4之切單之鋸 之覓度要大。線X-X顯示通常地便'背引線框架4組裝之封裝 而延伸之始、封位置以及在面板2上之引線框架4之切單應該 較佳發生之地方。在切單期間，毛邊產生而從引線1〇之嵌 入表面21 (圖3)延伸。毛邊並不跨越由裝載表面15所定義之 裝載平面。 圖3係為根據本發明之第一具體實施例之QFN半導體封裝 22之剖面檢視圖。使用從引線框架面板2切單之引線框架4 組裝半導體封裝22。封裝22具有有晶片黏結墊（未顯示）之 半導體晶片24。半導體晶片24貼至引線框架4之標記部份8 。晶片辨結墊使用如金線26之連接器連接至引線框架4之 相對應引線10。 密封物28至少部份地密封半導體晶片24和引線1〇。密封 物28定義封裝22之整體形狀。密封物28最好被允許流動以 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 515059 A7 B7 發明説明 覆蓋篏入表面21以圍繞引線10之外部部份ι6。由密封物28 圍繞引線10提供較好之支撐在引線10上且提供支撐於外部 引線部份16以防止在切單期間彎曲。在切單之後引線⑺之 嵌入表面21相鄰封裝22之周邊。這些嵌入表面21與震載表 面15錯置使得從嵌入表面21延伸之毛邊3〇並不跨越裝載平 面。 圖4係為根據本發明之第二具體實施例之半導體封裝32 之剖面檢視圖。該半導體封裝32之引線框架4也具有引線1〇 其具有從引線10之裝載表面15喪入之嵌入表面21。產生這 樣之引線框架4包括壓印取代|虫刻該引線框架面板22以導 致相鄰繫桿12之部引線部份16彎曲而遠離引線1〇之内部部 份14。壓印最好在將半導體晶片至引線框架4之前執行。 有利地，本發明提供具有毛邊30在引線之外部部份16上 之改進之半導體封裝22’其中該毛邊並不跨越由引線之内 部部份14之電路板裝載表面15形成之裝載平面。這樣之半 導體封裝22能夠相當均勻坐落在pcB上以允許電路板裝載 表面15與在PCB上之連接墊接觸以有利於適當之銲錫連接。 雖然本發明已經參考較佳具體實施例描述，要了解本發 明並不限制於在此描述之具體實施例。例如，應該注意在 圖3顯示之引線框架4因說明之容易性而簡化。使用在實際 半導體封裝之引線框架4可以具有與已經顯示之不同形狀 且其通常包括更多之引線1〇。 如同對於熟悉此技藝人士係明顯的，引線框架可以不需 要標記部份。不需標記部份之這樣之半導體封裝描述在美 國專利 5,894，108 〇 -8 - 本紙張尺度適用中國國家標準(CNS) A4:%格(21Qx 297公黄） "According to an aspect of the present invention, a lead frame for a lead package is provided. The I-line frame has a plurality of tie rods that define the circumference of the lead frame. The lead frame has a plurality of leads extending inwardly from t, which is related to the tie rod A +. The bow I line has a circuit board loading surface arranged in a loading plane and each of the loading surfaces is spaced from the tie rod. The index green also has one that owes into the surface adjacent to the tie bar. The embedding surface is more and more loaded, and the loading surface is misaligned so that the burr extending from the inlaid surface does not cross the loading plane during the ordering of the lead frame. Suitably 'the lead frame may include a marking portion affixed to at least one of the plurality of tie bars. -Suitably, the embedding surface can be offset from the loading surface by bending the plurality of leads. Suitably, the embedded surface can be offset from the loading surface by cutting, cutting, or etching the plurality of leads. Preferably, the embedded surface may be sufficiently offset from the loading surface by cutting, cutting, or etching the plurality of leads to allow the sealant to seal the embedded surface. According to another aspect of the present invention, there is provided a semiconductor package including a semiconductor wafer having a wafer bonding pad and a lead electrically connected to a corresponding wafer bonding pad. The leads have circuit board loading surfaces arranged in a common loading plane. The lead also has a diffusing surface adjacent to the periphery of the package. The package also includes a seal that at least partially seals the wafer and leads. The embedded surface is misaligned with the loading surface and the burr extending from the embedded surface is not -5- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) A7 B7 V. Description of the invention (3) Across the loading plane. Appropriately, the Feng Tou Zhuang package may include a marked portion to which the semiconductor wafer is attached. Schematic description This month can be easily understood by Gu and put into actual effect. Reference will be made to the preferred embodiment, as explained with reference to the accompanying drawings, where: Figure 1 is a bow | wire frame panel Part of the top plan inspection view, which shows a part of a single fully arched wire frame and adjacent lead frames; Figure 2 is a picture! A perspective view of the bottom surface portion of the lead frame panel portion, the display surface of which is embedded to produce the lead frame according to the first embodiment of the present invention;-Figure 2A is a portion of the lead frame along line B_B of Figure 2 3 is a cross-sectional view of a semiconductor package manufactured from the lead frame of FIG. 2; and FIG. 4 is a cross-sectional view of another semiconductor package manufactured from the lead frame according to the second embodiment . Detailed Description of Specific Embodiments of the Invention FIG. 1 shows a portion of a lead frame panel 2 having a plurality of lead frames 4. Each of the plurality of lead frames 4 is shown surrounded by a dotted line, and has a tie bar 12 defining a circumference of each lead frame 4. The tie bar 12 supports the marked portion 8 and the related lead 10. Each lead 10 has an inner portion 14 and an outer portion 16. The tie bar 12 supports the lead 10 by connecting the outer portion 16. The tie rods 2 are also connected to individual lead frames 4 on the lead frame panel 2. Within the lead 10, stand -6- 515059 A7 _______B7 V. Description of the invention (~~ " ~-~ Η 延伸 extends from the related rod 12 inward. The internal part is called arrayed as indicated by line AA in Figure 2A The circuit board loading surface 15 of the common loading plane. The circuit board loading surface 15 is separated from the related one of the tie bars 12. FIG. 2 is a perspective view showing a part of the lead frame panel 2 having the embedded surface 18. The lead frame panel 2 Formed from thin metal (for example, copper) sheets that have been engraved, cut, or pressed: as shown in the figure. The surface 18 of the lead frame panel 2 is embedded to provide the longitudinal direction along the tie bar 12. Shaft groove 20. The lead frame panel 2 can be etched or bent to create a groove 20. Figure 2 shows a portion of the lead frame panel 2 with a groove 20. Each groove 20 expands the entire width of the talent 12 and extends The outer portion 16 of the lead 10. The end-to-end width W of the groove 20 should be greater than that of the saw used for the singulation of the lead frame 4. The line XX shows that the lead frame 4 is usually assembled. Start of package extension, sealing position, and lead frame 4 on panel 2 Where the cut should preferably occur. During the cut, burrs are generated and extend from the embedded surface 21 (Figure 3) of the lead 10. The burrs do not cross the loading plane defined by the loading surface 15. Figure 3 is based on A cross-sectional view of a QFN semiconductor package 22 according to a first embodiment of the present invention. The semiconductor package 22 is assembled using a lead frame 4 cut from a lead frame panel 2. The package 22 has a semiconductor wafer 24 with a die attach pad (not shown). The semiconductor wafer 24 is affixed to the marked portion 8 of the lead frame 4. The wafer judging pad is connected to the corresponding lead 10 of the lead frame 4 using a connector such as a gold wire 26. A seal 28 at least partially seals the semiconductor wafer 24 and Leads 10. The seal 28 defines the overall shape of the package 22. The seal 28 is best allowed to flow. At this paper size, the Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applied. 515059 A7 B7 The surface 21 surrounds the outer portion ι6 of the lead 10. The seal 28 surrounds the lead 10 to provide better support on the lead 10 and to provide support on the outer lead portion 16 to prevent during singulation After the singulation, the embedded surfaces 21 of the lead wires are adjacent to the periphery of the package 22. These embedded surfaces 21 are offset from the seismic load surface 15 so that the burrs 30 extending from the embedded surfaces 21 do not cross the loading plane. A cross-sectional view of a semiconductor package 32 according to a second specific embodiment of the present invention. The lead frame 4 of the semiconductor package 32 also has leads 10 having an embedded surface 21 recessed from a loading surface 15 of the lead 10. This produces this The lead frame 4 includes embossing instead of etching the lead frame panel 22 to cause a portion of the lead portion 16 of the adjacent tie bar 12 to bend away from the inner portion 14 of the lead 10. Imprinting is preferably performed before the semiconductor wafer is applied to the lead frame 4. Advantageously, the present invention provides an improved semiconductor package 22 'having a burr 30 on the outer portion 16 of the lead, wherein the burr does not span a loading plane formed by the circuit board loading surface 15 of the inner portion 14 of the lead. Such a semiconductor package 22 can be seated fairly uniformly on the pcB to allow the circuit board loading surface 15 to contact the connection pads on the PCB to facilitate proper solder connection. Although the invention has been described with reference to preferred specific embodiments, it is to be understood that the invention is not limited to the specific embodiments described herein. For example, it should be noted that the lead frame 4 shown in FIG. 3 is simplified for ease of explanation. The lead frame 4 used in an actual semiconductor package may have a different shape from what has been shown and it usually includes more leads 10. As will be apparent to those skilled in the art, lead frames may not need to be marked. Such semiconductor packages that do not need to be marked are described in U.S. Patent 5,894,108 〇 -8-This paper size applies Chinese National Standard (CNS) A4:% grid (21Qx 297 yellow) "

Claims (1)

一種半導體封裝之引線框牟 木，该引線框架包括： 複數個繫桿，盆宕蓋# w丄 ”疋義β亥引線框架之周長； 该複數個引線，其從該暫： 繫扣相關之一向内延伸，該引 線具有電路板裝載表面排 开〜在共同裝載平面中，以及每 個該裝載表面與該繫桿間 ^ . α ^ 间^開，該引線亦具有嵌入表面 相郴之該等繫桿相對應之一； 。其中該嵌入表面與該裝載表面錯置使得在該引線框架 單』間從欣入表面延伸之毛邊並不跨越該裝載平面。 2. 如申請專利範圍第】項之引線框架，進一步包括貼至該 寻稷數個繫桿至少其中之_之標記部份。 3. 如申請專利範圍第i項之引線框架，其中該嵌入表面藉 -由彎曲該複數個引線而與該裝載>面錯置。 4 .如申凊專利範圍第丨項之引線框架，其中該嵌入表面藉 由切開、切除和蝕刻該複數個引線其中之一而與該裝載 表面錯置。 5 .如申印專利範圍第4項之引線框架，其中該嵌入表面藉 由切開、切除和蝕刻該複數個引線其中之一足夠地而與 該裝載表面錯置以允許該密封物密封該嵌入表面。 6· —種半導體封裝，包括： 具有晶片黏結墊之半導體晶片； 引線’該等引線電氣連接至相對應之晶片黏結墊，該 引線具有電路板裝載表面排列在共同裝載平面中，該引 線也具有嵌入表面相鄰該封裝之周邊； 密封物’其至少部份地密封該晶片及引線； -9 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 515059 8 8 8 8 A B c D 々、申請專利範圍 其中該嵌入表面與該裝載表面錯置且從該嵌入表面延 伸之毛邊並不跨越該裝載平面。 7.如申請專利範圍第6項之半導體封裝，進一步包括該半 導體晶片附著之標記部份。 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）A lead frame frame for a semiconductor package. The lead frame includes: a plurality of tie rods, a perimeter of a pot lead cover; and a plurality of leads, from which: Extending inward, the lead has a circuit board loading surface arranged ~ in a common loading plane, and each of the loading surface and the tie bar ^. Α ^ space ^ apart, the lead also has an embedded surface corresponding to the A corresponding one of the tie rods; wherein the embedding surface and the loading surface are misaligned so that a burr extending from the surface of the lead frame between the lead frame sheet does not cross the loading plane. The lead frame further includes a marking portion affixed to at least one of the plurality of tie rods. 3. For the lead frame of the scope of application for item i, wherein the embedding surface is formed by bending the plurality of leads with The loading > planes are misaligned. 4. The lead frame as claimed in claim 1, wherein the embedded surface is misaligned with the loading surface by cutting, cutting and etching one of the plurality of leads. 5. The lead frame according to item 4 of the scope of the printed patent, wherein the embedding surface is sufficiently offset from the loading surface by cutting, cutting and etching one of the plurality of leads to allow the sealant to seal the embedding. Surface 6. A semiconductor package comprising: a semiconductor wafer having a wafer bonding pad; leads; the leads are electrically connected to corresponding wafer bonding pads, the leads having a circuit board mounting surface arranged in a common mounting plane, the leads It also has an embedded surface adjacent to the periphery of the package; a sealer that at least partially seals the chip and leads; -9-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 515059 8 8 8 8 AB c D 々. The scope of the patent application where the embedded surface is offset from the loading surface and the burr extending from the embedded surface does not cross the loading plane. 7. If the semiconductor package of item 6 of the patent application scope further includes The marking part attached to the semiconductor wafer. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)
TW090125920A 2000-10-31 2001-10-19 A leadframe and semiconductor package TW515059B (en)

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