TW511225B - Method for forming insulation trench - Google Patents

Method for forming insulation trench Download PDF

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TW511225B
TW511225B TW89124590A TW89124590A TW511225B TW 511225 B TW511225 B TW 511225B TW 89124590 A TW89124590 A TW 89124590A TW 89124590 A TW89124590 A TW 89124590A TW 511225 B TW511225 B TW 511225B
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Taiwan
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substrate
insulating
layer
plug
patent application
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TW89124590A
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Chinese (zh)
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Hung-Huei Tzeng
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Vanguard Int Semiconduct Corp
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Abstract

A method for forming an insulation trench at least comprises: (a) forming a mask layer on a substrate, in which the mask layer comprises an opening exposing a portion of the substrate; (b) removing the substrate beneath the exposed portion to form an opening extending through into the substrate; (c) forming an insulation material on the opening in the substrate, in which the insulation material forms an insulation plug in the opening in the substrate; and (d) after the formation of the insulation plug in the opening, removing the mask layer and a portion of the insulation plug so as to expose the surface of the substrate and to ensure that the residual insulation plug is located only in the substrate.

Description

511225 五、發明說明(1) 5 - 1發明領域: 本發明係有關於形成絕緣溝渠的方法,特別是有關於 形成絕緣溝渠而不會因鄰近絕緣渠溝間隙產生寄生元件的 方法。 5 - 2發明背景: 隨著半導體元件應用廣泛,大量的獨立元件被裝置在 一單一的半導體底材上。許多的獨立元件相互之間都需要 加以的隔離,其中一個常用來達到此目的的方法就是在相 鄰的元件間形成一渠溝隔離。其中,渠溝隔離至少包含了 形成一渠溝(trench)或一洞(cavity)在底材内,然後 填入一絕緣材料,例如二氧化矽。渠溝隔離區通常可區分 為三種:淺渠溝隔離(渠溝深度約一微米),中等深度渠 溝隔離(渠溝深度約一到三微米),以及深渠溝隔離(渠 溝深度約超過三微米)。 一習知形成隔離渠溝的方法如下第一圖至第五圖所示 。參照第一圖,半導體晶片1 0包含一底材1 2,且底材1 2上 依序形成一氧化層14,一氮化層16,和一圖案化光阻層18 。底材1 2使用的材質至少包含有多晶矽,通常被輕摻雜一 促進導電的雜質(dopant)。底材12包含一上表面15,氧化511225 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for forming an insulation trench, and more particularly to a method for forming an insulation trench without generating parasitic elements due to a gap between adjacent insulation trenches. 5-2 Background of the Invention: With the wide application of semiconductor components, a large number of independent components are mounted on a single semiconductor substrate. Many independent components need to be isolated from each other. One of the commonly used methods to achieve this is to form a trench isolation between adjacent components. The trench isolation at least includes forming a trench or a cavity in the substrate, and then filling an insulating material, such as silicon dioxide. Trench isolation areas can generally be divided into three types: shallow trench isolation (ditch depth of about one micron), medium depth trench isolation (ditch depth of about one to three microns), and deep trench isolation (ditch depth of about Three microns). A conventional method for forming an isolation trench is shown in the first to fifth figures below. Referring to the first figure, the semiconductor wafer 10 includes a substrate 12, and an oxide layer 14, a nitride layer 16, and a patterned photoresist layer 18 are sequentially formed on the substrate 12. The material used for the substrate 12 contains at least polycrystalline silicon, and is usually lightly doped with a dopant that promotes conductivity. The substrate 12 includes an upper surface 15 which is oxidized

五、發明說明(2) —-^ 層1 4係形^覆蓋在上表面丨5上,此氧化層的材質係包含氧 化石夕接著’氮化層1 6形成覆蓋在氧化層1 4上,氮化層的 材質係包含氮化石夕。 參照第二圖,圖案化光阻層丨8係用作為蝕刻程序中的 一遮罩。此圖案化光阻層丨8係定義出一洞區域,在蝕刻程 · 序中移除此洞區域内的部分氮化層1 6,部分氧化層1 4,和 -部份底材1 2以形成一開口 20。另外,此蝕刻程序刻區分為 三種蝕刻程序,分別為氮化層1 6,氧化層丨4,以及底材1 2 的蝕刻程序,重點在於在底材丨2内所需的深度以形成此開φ 口 2 0例如,開口 2 〇用作為淺渠溝,則此蝕刻程序主要是 使此開口 2 0的深度小於或相當於一微米。 參妝第二圖,在氮化層1 6上和開口 2 〇内形成絕緣物質 ,然後依序移除部分絕緣物質和氮化層丨6。在此,絕緣物 質不同於氮化層1 6的是在完全移除氮化層丨6時,在開口 2 〇 位置的絕緣物質沒有被移除。此絕緣物質成為一絕緣插塞 3 0在底材1 2上,此絕緣插塞3 0可作為渠溝。V. Description of the invention (2) —- ^ The layer 1 4 is shaped on the upper surface 5 and the material of this oxide layer includes oxide stone and then the nitride layer 16 is formed to cover the oxide layer 14 The material of the nitrided layer is nitride stone. Referring to the second figure, the patterned photoresist layer 8 is used as a mask in the etching process. The patterned photoresist layer 丨 8 defines a hole area. In the etching process, part of the nitride layer 16, part of the oxide layer 1 4, and-part of the substrate 12 are removed. An opening 20 is formed. In addition, this etching process is divided into three etching processes, namely the etching process of the nitride layer 16, the oxide layer 丨 4, and the substrate 1 2. The focus is on the required depth in the substrate 丨 2 to form the opening. φ port 20, for example, the opening 20 is used as a shallow trench. This etching process is mainly to make the depth of the opening 20 less than or equal to one micron. Referring to the second figure, an insulating substance is formed on the nitride layer 16 and within the opening 20, and then a part of the insulating substance and the nitride layer are sequentially removed. Here, the insulator is different from the nitride layer 16 in that when the nitride layer 16 is completely removed, the insulator at the opening 20 position is not removed. This insulating substance becomes an insulating plug 30 on the substrate 12, and this insulating plug 30 can be used as a trench.

知參,第四圖,移除氧化層14,移除氧化層可用一藉使 用氟化氫的濕蝕刻法。如圖所示,蝕刻程序也會移除部分 絕緣插,3 0。不同於氮化層1 6和以往常見的絕緣物質如氮 化物或氧化物,蝕刻程序時會使插塞3 〇邊緣凹陷低於底材 1 2得上表面1 5。間隙4 3產生在絕緣插塞3 〇和下表面丨5間。Known parameter, the fourth figure, the oxide layer 14 is removed. The oxide layer can be removed by a wet etching method using hydrogen fluoride. As shown in the figure, the etching process will also remove some of the insulation plugs, 30. Unlike the nitride layer 16 and the conventional insulating materials such as nitrides or oxides, the edge of the plug 30 is lower than the substrate 12 and the upper surface 15 during the etching process. A gap 43 is generated between the insulating plug 30 and the lower surface 5.

第5頁 511225 五、發明說明(3) 更特別地,絕緣插塞30包含周圍側壁44部分42延伸於上表 面15下而部分44高於上表面15。部分42包含低區段45和上 區段4 6 ’其中低區段4 5係緊鄰底材丨2而高區段4 6則藉間p家 4 3與底材1 2分離。 參照第五圖,長出附加絕緣層5丨在上表面丨5上,例如 以熱氧化法。接著再形成多晶矽層5 2在附加絕緣層5丨上。 夕晶石夕層5 2可最後被形成入字元線,係包含電晶體區域緊 鄰絕緣插塞3 0,則然後絕緣插塞係可用作渠溝隔離區域。 時降 件下 元壓 生電。 寄始程 成啟製 形的的 件件後 元元隨 體體礙 晶晶妨 電電會 鄰成也 3 緊造4 再後隙 ,最間 式且, 方生外 種產之 何易此 以容除 3 論4 〇 不隙響 間影 ,的 直到現在’有一些方法揭露用以降低間隙4 3,如美國 專利案號6, 0 9 3, 6 5 2號。如第六圖所示,其中一減少間隙 43方法是藉由在形成附加絕緣層等之前,先降低底材丨2的 表面至第一新上表面61,此第一新上表面61係低於上表面 1 5 ’故間隙4 3會消失。如第七圖所示,另一減少間隙4 3方 法是藉由移除部分在底材1 2上的絕緣插塞3 〇,在間隙4 3形 成後使剩餘的絕緣插塞3 0完全與底材1 2相對,且與底材1 2 相鄰的上區段46也被移除,則底材1 2得上表面1 5變為第二 上表面71。Page 5 511225 V. Description of the invention (3) More specifically, the insulating plug 30 includes a peripheral wall 44 in which a portion 42 extends below the upper surface 15 and a portion 44 is higher than the upper surface 15. The portion 42 includes a lower section 45 and an upper section 4 6 ′, where the lower section 45 is adjacent to the substrate ② and the high section 4 6 is separated from the substrate 12 by the p'house 4 3. Referring to the fifth figure, an additional insulating layer 5 is grown on the upper surface 5, for example, by a thermal oxidation method. A polycrystalline silicon layer 52 is then formed on the additional insulating layer 5 丨. The spar stone slab layer 5 2 can be finally formed into the word line, which includes the transistor region immediately adjacent to the insulating plug 30, and then the insulating plug system can be used as a trench isolation region. When the time drops, the element generates voltage. Send the pieces that are in the shape of the starting process, and the elements will follow the body, hinder Jingjing, and the electricity will be adjacent to 3, and then 4 will be built, and the backlash will be the most interlaced. On the 40% non-gap interval, until now 'there are some methods to uncover the gap 4 3, such as US Patent No. 6, 0 9 3, 6 52. As shown in the sixth figure, one of the methods for reducing the gap 43 is to lower the surface of the substrate 2 to the first new upper surface 61 before forming an additional insulating layer, etc. The first new upper surface 61 is lower than The upper surface 1 5 'so the gap 4 3 will disappear. As shown in the seventh figure, another method of reducing the gap 4 3 is to remove a part of the insulating plug 3 0 on the substrate 12, and after the gap 4 3 is formed, make the remaining insulating plug 30 completely with the bottom. The substrate 12 is opposite, and the upper section 46 adjacent to the substrate 12 is also removed, so that the substrate 12 becomes the upper surface 15 and becomes the second upper surface 71.

第6頁 511225Page 6 511225

五、發明說明(4) 總言之,習知用來減少間隙4 3的方法都伴隨签_ ^ 點’因此仍須發展減少間隙4 3更完備的方法。 —、 5 - 3發明目的及概述: 本發明的目的至少包含形成絕緣渠溝而不會有間隙& 生在底材和絕緣渠溝間的缺點。 本發明的目的更包含防止形成間隙在形成渠溝程#日寺 整體而言,本發明的一方法至少包含下列基本步驟。 首先’形成一絕緣插塞在一底材的一開口内,其中絕緣插 塞係有一最外表面的表面延伸在底材的一最近表面。然後 ’移除一部份絕緣插塞在一水平方向直到殘餘的絕緣插夷 僅位於底材的内部。 土 本發明的另一方法至少包含下列步驟。首先,形成一 遮罩層覆蓋底材,此遮罩層係包含暴露出一部份底= 開口。接著,移除暴露部分的底材以形成一開口延進I 底材。然後’形成-絕緣物質在底材内的開口以一 π 緣插塞。之後,進行一移除^± f、私序以同日守移除遮罩層和一邱 】、路出底材的一上方表面且暴露出 知、、、巴緣插塞使的不止是暴露屮矻士 ,V. Description of the Invention (4) In summary, the methods used to reduce the gap 4 3 are accompanied by the sign ^ ^ ', so it is necessary to develop a more complete method to reduce the gap 4 3. —, 5-3 Object and Summary of the Invention: The object of the present invention at least includes the disadvantage of forming an insulation trench without a gap & born between the substrate and the insulation trench. The object of the present invention further includes preventing the formation of a gap in the formation of the trenches # 日 寺 Overall, a method of the present invention includes at least the following basic steps. First, an insulating plug is formed in an opening of a substrate, wherein the insulating plug has a surface with an outermost surface extending on a nearest surface of the substrate. Then ‘remove a part of the insulation plug in a horizontal direction until the remaining insulation plug is only inside the substrate. Another method of the present invention comprises at least the following steps. First, a masking layer is formed to cover the substrate, and the masking layer includes exposing a part of the bottom = opening. Next, the exposed portion of the substrate is removed to form an opening extending into the I substrate. Then the 'formation-insulating material's opening in the substrate is plugged with a π edge. After that, perform a removal ^ ± f, remove the mask layer and a Qiu on the same day, and exit the upper surface of the substrate and expose the Zhi, Ba, and the edge plugs to make more than just exposure. Sergeant,

第7頁 511225 五、發明說明(5) 僅位於底材内殘留的絕緣插塞。 5 - 4發明詳細說明: 本發明的半導體設計可被廣泛地應用到許多半導體設 計中,並且可利用許多不同的半導體材料製作,當本發明 以一較佳實施例來說明本發明方法時,習知此領域的人士 應有的認知是許多的步驟可以改變,材料及雜質也可替換 ,這些一般的替換無疑地亦不脫離本發明的精神及範疇。 間之然,而製是 少隙。隙溝體不 減間隙間渠導就 於有間的緣半改 過沒成在絕當修 好而形存成但以 成溝會少形,加 形渠不減法程程 的緣時何方製製 隙絕同如的的的 間成的於新溝關 免形溝重個渠相 避新渠著一成對 是個成都,形針 的一形法然改, 調,於方當修時 強說重的。須同 明是著知在必的 發就須已存生步 本也必有然產進 ,。法所仍的斷。 先成方乎隙隙不了 首形的幾間間術難 的點,是有技困 隙缺而但沒程太Page 7 511225 V. Description of the invention (5) Only the insulation plug remaining in the substrate. 5-4 Detailed description of the invention: The semiconductor design of the present invention can be widely applied to many semiconductor designs, and can be made of many different semiconductor materials. When the present invention is described by a preferred embodiment, Those skilled in the art should recognize that many steps can be changed, materials and impurities can be replaced, and these general replacements undoubtedly do not depart from the spirit and scope of the present invention. Between them, and the system is less gap. The gap channel does not reduce the gap between the channels. The gap between the gaps is not changed. When it is repaired, it is formed but it will be less shaped. When the shape of the channel is not reduced, the method of making gaps is not necessary. Yuxingou Guan is free from the same ditch, and the new ditch is avoided. The pair is Chengdu, the shape of the needle is changed, and the tone is emphasized by Yu Fangdangxiu. It must be clearly understood that the necessary steps must be in place and the production must be made. The law still breaks. First of all, the difficult point of the first shape is that there are technical difficulties, gaps, but no way

I 本發明的一較佳實施例是有關於一種形成一絕緣渠溝 的方法。參照第八圖,本方法至少包含兩個基本步驟。首 先,如區塊8 1所示,形成一絕緣插塞在一底材的一開口内 ,其中絕緣插塞係有一最外表面延伸在底材的一最近表面A preferred embodiment of the present invention relates to a method for forming an insulating trench. Referring to the eighth figure, the method includes at least two basic steps. First, as shown in block 81, an insulating plug is formed in an opening in a substrate, wherein the insulating plug has an outermost surface extending on a nearest surface of the substrate.

厶z:> 五 、發明說明(6) 的外表上 份的絕 接著’如區塊82所示’在一水平方向移除 後一 含一 、緣插塞直到殘留的絕緣插塞僅位於底材的内π 7 、、、邑緣渠溝就形成了。在完成移除程序後,絕緣插 周園表面和底材緊鄰。 插塞 部 然 包 此外, 罩層在底材 而成。接著 填滿此開口 底材的最 側壁在開 的一部份 此外,係 通常更包 部份絕緣 向 且 絕緣插塞可 上,且此遮 ,形成一開 ,絕緣物質 近表面就是 口内且緊鄰 絕緣插塞前 使用化學機 含一濕I虫刻 插塞的程序 以下列步驟形成。首先 罩層係以一氧化層和一 口在遮罩層和底材内並 係形成在遮罩層上及開 底材的最外表面,而絕 底材。在進行移除程序 ,可先移除在遮罩層上 械研磨程序移除一部份 程序處理最近的表面以 後所產生在底材上或底 ,形成—遮 氮化層堆疊 以絕緣物質 口内。另外 緣插塞係有 移除水平方 的絕緣物質 絕緣插塞, 修補在移除 材内的刮痕 顯然地,本方法使用先進效能的方式, 械研磨程序,移除一些物質而使在底材上的 如一部份的絕緣插塞,可直接被移除。 特別是化學機 其他物質,例厶 z: > V. The description of the invention (6) must be followed by the 'as shown in block 82' after removing it in a horizontal direction, including the edge plug until the remaining insulation plug is only at the bottom. The inner pi 7 ditch of the material was formed. After the removal procedure is completed, the surface of the insulation insert is immediately adjacent to the substrate. The plug part is naturally covered. In addition, the cover layer is formed on the substrate. Then fill the opening with the most side wall of the substrate in the open part. In addition, it usually contains a part of the insulation direction and the insulating plug can be put on, and this cover forms an opening. The near surface of the insulating material is in the mouth and immediately adjacent to the insulation The procedure using a chemical machine containing a wet I-embedded plug before plugging is formed in the following steps. First, the mask layer is formed by an oxide layer and a mouth in the mask layer and the substrate, and is formed on the mask layer and the outermost surface of the substrate, and the substrate is insulated. During the removal process, the mask layer can be removed first. The mechanical grinding process removes a part of the process. The nearest surface is then processed on the substrate or the bottom to form a stack of nitride layers with an insulating substance in the mouth. The other edge plug is an insulating plug that removes the horizontal insulating material, and repairs the scratches in the removed material. Obviously, this method uses advanced performance methods, mechanical grinding procedures, and removes some substances to make the substrate A part of the insulating plug can be directly removed. Especially chemical machines

本發明的另一實施例如 圖和第十圖的圖示中,會使 圖相似的編號,不同之處會 第九圖和第十圖所示。在第九 用如前習知技術第一圖至第七 以一附加符號”a”所示或使用In another embodiment of the present invention, the figures of the drawings and the tenth figure are similarly numbered, and the differences are shown in the ninth and tenth figures. In the ninth, as shown in the prior art, the first to seventh figures are shown or used with an additional symbol "a".

511225 五、發明說明(7) 新的編號。 參照第九圖,此圖係為接續著習知技術第三圖的步驟 ,其中部分的絕緣插塞3a係位於底材1 2a内。雖然,第所 表示的程序步驟相似於第四圖,但有一明顯不同在第九圖 和第三圖的是絕緣插塞3 0是位於底材1 2内及底材1 2上,且 間隙4 3會存在於底材1 2和殘留的絕緣插塞3 0間。然而,絕 緣插塞3 0 a係僅位於底材1 2 a内且底材1 2 a和殘留的絕緣插 塞3 0 a間沒有間隙存在。然而,值得注意的是上方表面1 5 a 係獨立於上方表面1 5。進一步參照第十圖,依序形成附加 絕緣層5 1 a和多晶矽層5 2 a在上方表面1 5 a後,因為沒有間 隙存在故不會有寄生元件產生。 在本方法中,以一平坦化程序同時移除一部份的絕緣 插塞3 0和氧化層1 4,較佳的效果是使用化學機械研磨程序 ,係可同時移除不同的物質而無蝕刻選擇性的問題,係習 知方法產生間隙4 3的來源。另一方面,習知方法使用蝕刻 技術來移除氧化層1 4,特別是濕蝕刻程序,然後氧化層1 4 和絕緣插塞3 0的蝕刻選擇性導致間隙4 3的產生。然而,本 實施例使用其他方式同時移除氧化層1 4和部分絕緣插塞3 0 ,然後氧化層1 4和絕緣插塞3 0的蝕刻選擇性就不會導致間 隙4 3的產生。由於平坦化程序不可避免會產生一些刮痕在 上表面1 5 a上,本實施例更包含隨意選擇的一步驟處理上 表面1 5 a,係為藉一濕蝕刻程序修補所有的刮痕。511225 5. Description of the invention (7) New number. Referring to the ninth figure, this figure is a step following the third figure of the conventional technology, in which a part of the insulating plug 3a is located in the substrate 12a. Although the procedure shown in the figure is similar to the fourth figure, there is a significant difference. In the ninth and third figures, the insulating plug 30 is located in the substrate 12 and the substrate 12 and the gap 4 3 will exist between the substrate 12 and the remaining insulating plug 30. However, the insulating plug 3 0 a is located only in the substrate 12 a and there is no gap between the substrate 12 a and the remaining insulating plug 30 a. However, it is worth noting that the upper surface 15 a is independent of the upper surface 15. Further referring to the tenth figure, after the additional insulating layer 5 1 a and the polycrystalline silicon layer 5 2 a are sequentially formed on the upper surface 15 a, no parasitic element is generated because there is no gap. In this method, a part of the insulating plugs 30 and the oxide layer 14 are removed at the same time by a planarization process. A better effect is to use a chemical mechanical polishing process, which can remove different substances at the same time without etching. The question of selectivity is the source of the gap 4 3 in conventional methods. On the other hand, the conventional method uses an etching technique to remove the oxide layer 14, especially a wet etching process, and then the etching selectivity of the oxide layer 14 and the insulating plug 30 causes a gap 43. However, in this embodiment, the oxide layer 14 and part of the insulating plugs 30 are simultaneously removed by other methods, and then the etching selectivity of the oxide layer 14 and the insulating plugs 30 will not cause the gap 43 to be generated. Since the planarization process will inevitably generate some scratches on the upper surface 15a, this embodiment further includes a step of arbitrarily selecting the upper surface 15a to repair all the scratches by a wet etching process.

第10頁 511225 五、發明說明(8) 進一步地,在本實施例的實際應用中,氧化層1 4的厚 度範圍約為1 0 0倒5 0 0埃,氮化層1 6的厚度範圍約為1 0 0 0到 3 0 0 0埃。另外,絕緣層的材質係為二氧化矽,氮化層1 6係 以一化學機械研磨程序移除,而移除程序係為一化學機械 研磨程序。 最後,與其他習知技術如第六圖和第七圖所示比較, 本發明的優點至少包含不需移除部分的底材再形成結構在 底材内,例如摻雜區域將不會被損壞,且亦不需要使用兩 p 個步驟去移除氧化層和部分的絕緣插塞。 以上所述僅為本發明之較佳實施例而已,並非用以限 定本發明之申請專利範圍;凡其它未脫離本發明所揭示之 精神下所完成之等效改變或修飾,均應包含在下述之申請 專利範圍内。Page 10 511225 V. Description of the invention (8) Further, in the practical application of this embodiment, the thickness range of the oxide layer 14 is approximately 100 to 50 angstroms, and the thickness range of the nitride layer 16 is approximately It is 1 0 0 0 to 3 0 0 0 Angstroms. In addition, the material of the insulating layer is silicon dioxide, the nitride layer 16 is removed by a chemical mechanical polishing process, and the removal process is a chemical mechanical polishing process. Finally, compared with other conventional technologies, as shown in Figures 6 and 7, the advantages of the present invention include at least the substrate that does not need to be removed, and the structure is formed in the substrate. For example, the doped regions will not be damaged. , And also does not need to use two p steps to remove the oxide layer and part of the insulating plug. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

511225 圖式簡單說明 第一圖到第五圖係為一平常形成絕緣渠溝之方法的連 續剖面示意圖。 第六圖和第七圖係為兩種平常減少鄰接絕緣渠溝間隙 之方法的剖面示意圖。 第八圖係為本發明之一實施例的流程圖。 第九圖和第十圖係為本發明另一實施例的剖面示意 圖。 主要部分之代表符號·· 1 0半導體晶片 12底材 1 4氧化層 1 5底材的上表面 1 6氮化層 18圖案化光阻層 2 0開口 3 0絕緣插塞 4 1絕緣插塞的側壁 4 2絕緣插塞側壁下部分 4 3間隙 44絕緣插塞側壁上部分511225 Brief description of the drawings The first to fifth drawings are successive cross-sectional schematic diagrams of a method for generally forming an insulation trench. Figures 6 and 7 are schematic cross-sectional views of two methods of usually reducing the gap between adjacent insulating trenches. The eighth diagram is a flowchart of an embodiment of the present invention. The ninth and tenth figures are schematic sectional views of another embodiment of the present invention. Symbols of the main parts ... 1 0 semiconductor wafer 12 substrate 1 4 oxide layer 1 5 upper surface of the substrate 1 6 nitride layer 18 patterned photoresist layer 2 0 opening 3 0 insulating plug 4 1 Side wall 4 2 Insulating plug lower side wall 4 3 Gap 44 Insulating plug upper side wall

第12頁 511225 圖式簡單說明 4 5絕緣插塞側壁下部分低區段 4 6絕緣插塞側壁下部分上區段 5 1附加絕緣層 6 1多晶矽層 7 1底材的第二上表面 81區塊 8 2區塊 1 2 a底材 1 5 a上表面 3 0 a絕緣插塞 0 5 1 a附加絕緣層 52a多晶矽層Page 12 511225 Brief description of the diagram 4 5 Lower section of the lower part of the side wall of the insulating plug 4 6 Upper section of the lower part of the side wall of the insulating plug 5 1 Additional insulating layer 6 1 Polycrystalline silicon layer 7 1 The second upper surface of the substrate 81 Block 8 2 Block 1 2 a Substrate 1 5 a Upper surface 3 0 a Insulating plug 0 5 1 a Additional insulating layer 52a Polycrystalline silicon layer

第13頁Page 13

Claims (1)

叫225 m.':Called 225 m. ': 1 · 一種形成一絕緣渠溝在一底材的方法至少勺人 形成一遮罩層覆蓋該底材,該遮罩屏二^含: 部份該底材的一開口; ㈢你包含暴露出一 矛夕除4暴路部分的該底材以形成一聞 材; 延伸進入該底 形成一絕緣物質在該底材内的該開口/ 塞;以及 形成一絕緣插 運仃 - 秒除程序以同日守π卜丁、热题皁芦去 插塞的不止是暴露出該底材的一上方表二2份該絕緣 ,底材:殘”該絕緣插塞,其中在該移除程:二=: 省的该絕緣插塞係至少包含一外圍侧壁緊鄰該底材。 2·如申請專利範圍第丨項之方法,其中上述之遮罩層係以 一氧化層和一氮化層堆疊而成。 3·如申請專利範圍第1項之方法,其中上述之絕緣物質係 同時形成在該開口内部和該遮罩層上。 4 ·=申請專利範圍第丨項之方法,更包含在進行該移除裎 序前從該遮罩層上移除該絕緣物質。 5·如申請專利範圍第1項之方法,其中上述之遮罩層係以 一化學機械研磨程序移除。1 · A method of forming an insulating trench and a substrate At least a person forms a masking layer to cover the substrate, the mask screen 2 contains: part of an opening of the substrate; ㈢ you include an exposed one Remove the substrate of the 4 storm road parts to form a smelling material; extend into the bottom to form the opening / plug of an insulating substance in the substrate; and form an insulating plug-in-second division procedure to keep on the same day π Buding, the hot plug to remove the plug is not only to expose the top of the substrate, two copies of the insulation, substrate: residual "the insulation plug, in which the removal process: two =: province The insulating plug includes at least one peripheral side wall adjacent to the substrate. 2. The method according to item 丨 of the patent application, wherein the above-mentioned mask layer is formed by stacking an oxide layer and a nitride layer. 3 · The method according to item 1 of the patent application, wherein the above-mentioned insulating substance is simultaneously formed on the inside of the opening and the masking layer. 4 · = The method according to item 1 of the patent application, further includes performing the removal. Remove the insulating material from the masking layer before the procedure. Scope of the methods, Paragraph 1, wherein said line of the mask layer removed to a chemical mechanical polishing process. 第14頁 511225 銮號 89124590Page 14 511225 No. 89124590 六、申請專利範圍 如申請專利靶圍第1項之方法,i中卜十、 L ^ T上述之移除程序 一化學機械研磨程序 々 7 · —種形成一隔離的方法至少包含: 提供一底材, 形成一氧化層在該底材上; 以及該底材以形成 形成一氮化層在該氧化層上; 轉移圖案至該氮化層,該氧化層 一開口延伸貫穿該底材; 形成一絕緣層在該開口内以形成一絕緣插塞 移除該氮化層;以及 ' 二行-移⑨程序以同時移除該氧化層矛口 一部份該絕緣 插f在一水平的方向直到殘餘的該絕緣插塞僅位於該底材 内部’其中在該移除程序完成後殘留的該絕緣插塞係至少 包含一外圍側壁緊鄰該底材。 夕 其中上述之底材係為一 8.如申請專利範圍第7項之方法 矽半導體底材。 9·如申請專利範圍第7項之方法,其中上述之氧化層 厚度範圍約為1 〇 〇到5 〇 〇埃。 曰 1 0·如申請專利範圍第7項之方法,其中上述之氮化声 一厚度範圍約為1 〇 〇 〇到3 0 0 0埃。 9 89124590 六、申請專利範圍 多月曰 ^二如氧申Λ專層利範圍第7項之方法,其中上述之絕緣層係為 述之氮化層係以 13.如申請專利範圍第7項之方法,其中上述之 為一化學機械研磨程序。 移除程序係 1 4·如申請專利範圍第7項之方法,在完成該_ @ ^ a依序在邊底材上和該殘留的該絕緣插塞上 氧化層和一閘極。 移除程序後更 成一閘極6. Scope of patent application. For the method of applying for the target range of the patent application, the removal procedure described in i.10, L ^ T, a chemical mechanical polishing procedure, and a method of forming an isolation include at least: Material, forming an oxide layer on the substrate; and the substrate to form a nitride layer on the oxide layer; transferring a pattern to the nitride layer, an opening of the oxide layer extending through the substrate; forming a An insulating layer is formed in the opening to form an insulating plug to remove the nitride layer; and a 'two-row-migration procedure to simultaneously remove a portion of the oxide layer spear, the insulating plug f is in a horizontal direction until the residual The insulating plug is located only inside the substrate, and the insulating plug remaining after the removal process is completed includes at least one peripheral sidewall immediately adjacent to the substrate. The above-mentioned substrate is a silicon semiconductor substrate according to the method in the seventh item of the patent application scope. 9. The method according to item 7 of the scope of patent application, wherein the thickness of the above-mentioned oxide layer ranges from about 1000 to 5000 angstroms. The method according to item 7 of the scope of patent application, wherein the thickness of the nitrided sound is in the range of about 1000 to 300 angstroms. 9 89124590 VI. The method of applying for a patent for more than one month ^ 2 The method of item 7 of the scope of patent application, such as the above-mentioned insulating layer is the nitrided layer described in 13. The method of item 7 of the scope of patent application Method, wherein the above is a chemical mechanical polishing procedure. Removal procedures are as follows: 4. According to the method of claim 7 in the scope of patent application, after completing the _ @ ^ a on the side substrate and the remaining insulating plug in order, an oxide layer and a gate electrode. After removing the program, it becomes a gate 第16頁Page 16
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