508783 A7 B7 五、發明說明（） 發明领域：_ 本發明與一種熔絲結構有關，特別是與形成薄熔絲結 構之方法有關。 發明背景：_ $目前的積體電路而言，單一的晶片是由數百萬個， 甚至是更多的元件所共同構成的，其中任何一個元件的瑕 疵或是缺陷，都會導致晶片電路功能的失效。然而，在元 件數目如此多的情況下，要達成完全無缺陷的要求，在製 程上有其實際的困難。並且，若是將這些失效的晶片於品 管檢測的過程中淘汰，則生產的成本將會增加。 因此在積體電路的設計上，常會在晶片上製造備用之 元件’如電容記憶胞（memory cell )等。此備份之目的在於 當積體電路晶片於生產過程中’若產生一些瑕疵缺陷的元件 時’如某一電容記憶胞損壞，此時即可使用此備份元件，用 來取代已損壞之電容記憶胞。一般在積體電路晶片完成製造 之後’會進行檢測，以找出晶片上有瑕疵缺陷的電路元件； 再以備份元件取代之，以修補積體電路晶片在生產過程中所 產生的瑕症缺陷。而備份的取代方式則是利用重新定義晶片 上導線的連接方式，將原先的瑕疵缺陷元件切斷。 一般而言，有數種方式可用來重新定義晶片上導線的 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ▼裝-----— II 訂·--- # 經濟部智慧財產局員工消費合作社印製 /83508783 A7 B7 V. Description of the invention () Field of the invention: The present invention relates to a fuse structure, and particularly to a method for forming a thin fuse structure. Background of the invention: As far as integrated circuits are concerned, a single chip is composed of millions or even more components. Defects or defects in any one of these components will cause the chip circuit to function. Failure. However, with such a large number of components, there are practical difficulties in achieving the completely defect-free requirements. Moreover, if these failed wafers are eliminated in the process of quality control inspection, the cost of production will increase. Therefore, in the design of integrated circuits, spare components such as a capacitor memory cell are often manufactured on a chip. The purpose of this backup is to use the backup component to replace the damaged capacitor memory cell when the integrated circuit chip is 'if some defective components are produced' if a certain capacitor memory cell is damaged. . Generally, after the integrated circuit wafer is manufactured, it is inspected to find defective circuit elements on the wafer; it is then replaced with a backup component to repair the defective defects generated by the integrated circuit wafer in the production process. The replacement method of backup is to redefine the connection method of the wires on the chip to cut the original defective components. Generally speaking, there are several ways to redefine the paper size of the wires on the chip. This paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the precautions on the back before filling this page). -----— II Order · --- # Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs / 83
五、 發明說明（ 經濟部智慧財產局員工消費合作社印製 的方； 重要的一種應用方式’即是使用銅'熔絲御) =式，精由燒斷來切斷原來晶片上已經具有的特定位址銅 =即可改變電流的路徑，而使備份用的元件替換有瑕蘇 =:。如此一來’原本失效的晶片即可經過此一燒斷銅熔 、=程加以修復。較常見的應用是以雷射的能量，透過晶 熔絲窗(fuse window)，來燒斷晶片上代表特定位址 缺r，：：再藉由修補的過程’可以減少晶片成品中的瑕疵 、^ 增加良率、減少成本的浪費。 =第-圖所示，即為一晶片上綱溶絲窗1〇的示意 炼絲窗1〇通常是藉去除介電層12、14和保護層μ 的方式，以形成開口於銅熔絲18之上，在修補過程之中， 2的能量即可經由銅熔絲窗1〇將位於介電層 =燒斷。傳統上用於金屬導線22間之介電層材質是以 材質為主，然而其介電常數通常高於3 〇以上 入深次微米領域時，需使用介電常數更低之材f來配合:件 尺寸之縮小，以達到所要求之性能。 但是當使用低介電常數的介電材質時，由於其本 機械強度與熱傳導比傳統之抓劣化許多。使得再進行燒 。 、枉T極易因為散熱效果不佳，造成周圍元件之 拍害，甚至造成晶圓之斷裂。且於傳統上，若以n層鋼金屬 層所構成之結構為例，銅熔絲通常是形成於第n_2層，亦即 T以最頂層銅金屬層所在之介電層為第4，則銅熔絲一般 是形成在往基板方向數之第三層銅金屬層所在之介電層 本紙張尺度ϋ財目 mtm (CNSiA^' ciio X 297 r-------#裝--------訂------ (請先閱讀背面之注意事項再填寫本頁)V. Description of the invention (printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs; an important application method is the use of copper 'fuses) = type, and the specific The address copper = can change the current path, and replace the defective components with backup = :. In this way, the originally failed wafer can be repaired through this copper melting process. A more common application is to use the energy of laser to blow through the fuse window to represent a specific address on the wafer, and then use the repair process to reduce defects in the finished wafer, ^ Increase yield and reduce cost waste. = As shown in Figure -1, it is a schematic illustration of a smelting window 10 on a wafer. Generally, the window 10 is formed by removing the dielectric layers 12, 14 and the protective layer μ to form an opening in the copper fuse 18. Above, during the repair process, the energy of 2 can be located at the dielectric layer = blown through the copper fuse window 10. Traditionally, the material of the dielectric layer used between the metal wires 22 is mainly based on materials. However, when the dielectric constant is usually higher than 30 or more, it needs to use a material with a lower dielectric constant f to match: Reduce the size of the parts to achieve the required performance. However, when a dielectric material with a low dielectric constant is used, due to its inherent mechanical strength and thermal conductivity, it is much worse than the conventional one. Make it burn again.枉 T is very easy to cause damage to surrounding components due to poor heat dissipation, and even cause wafer breakage. And traditionally, if the structure composed of n steel metal layers is taken as an example, copper fuses are usually formed on the n_2 layer, that is, T is the fourth dielectric layer where the top copper metal layer is located, then copper The fuse is generally formed on the dielectric layer of the paper layer where the third copper metal layer is counted toward the substrate. The paper size is mtm (CNSiA ^ 'ciio X 297 r ------- # 装 ---- ---- Order ------ (Please read the notes on the back before filling this page)
ϋ ϋ I #! 508783 五、發明說明（ 中。如第一圖所示，楚η鼠® 指介電層一要進：疋指介電層12,則第W層是 Μ層，會增加_困難性。*之_ ’由於需㈣至第 a、在“ ’已有將銅熔絲形成於第"人雷厚中Γ爭s 層）之趨勢，因為位於此層之銅金屬導嗖電（最頂 可避免傳統上，因銅熔；Γ在材由：通常亦為—。雖然如此 所造成之缺點，但是這1:在遭= 、，糸通吞疋與该層之銅金屬導線 塔 導線疋做為電源線，因此厚 幻 綷，铜饺絲路+ Α ^ $最厚，此時若欲燒斷銅熔 綠銅溶絲所需的能量勢必輕古 纷 ^ , # e M . . Α 呵。對於積體電路製造廠商而 擦⑶h ^ 士 1 將會使效率降低。並且此燒 斷銅溶絲時間的控制必須怜 ^ ^ ^ ^ , 田，若控制不當，時間過短將會 k成銅炼絲未燒斷而導致晶 H ifi具交且度 片的良率降低或是漏電流，若時 間過長又易傷及熔絲周圍的 — 疋件。若是更換雷射裝置， 則額外的支出將不符合經濟 # ι。因此發展一種新的銅炼碎 結構以解決上述問題是有必要的。 j塔4 發明目的及概述： 鑒於上述的發明背畢φ ^ , 成厅、中當銅熔絲轉換至最頂層時合 过遇到若干問題，例如時間的 命μ驶番、/ β ^ J〜徑制、雷射裝置必須更新孳 題’因此本發明在此据中—# σ 種新的銅熔絲結構及其形成方 本紙張&度細巾關家標準（CNS)A4規格(21Q x 297^5" 經濟部智慧財產局員工消費合作社印製 508783 A7508 ϋ I #! 508783 V. Description of the invention (In. As shown in the first figure, Chu n mouse ® refers to the dielectric layer to enter: 疋 refers to the dielectric layer 12, then the W layer is the M layer, which will increase _ Difficulty. * 之 _ 'Because of the need to go to a, there has been a tendency to "form copper fuses in the" three layers "of the thunderstorm), because the copper metal in this layer conducts electricity. (The top can avoid traditionally because of copper melting; Γ is made of: usually also-. Although the shortcomings caused by this, but this: in the end =,, the copper metal wire tower that is connected with this layer The wire 疋 is used as a power line, so the thick 綷 is thick, and the copper dumpling wire + Α ^ $ is the thickest. At this time, if you want to burn the copper-melting copper-melting copper melting wire, the energy will be different, # e M.. Α Oh. For integrated circuit manufacturers, erasing CDh ^ 1 will reduce the efficiency. And the control of the time of burning copper dissolving wire must be pity ^ ^ ^ ^ If the control is not proper, the time will be too short. Copper smelting wire has not been blown out, which causes the crystal H ifi to be intersected and the yield of the chip to be reduced or leakage current. If the time is too long, it will easily damage the fuses around the fuse — parts. If it is replaced Shooting device, the additional expenditure will not be in line with the economy. Therefore, it is necessary to develop a new copper smelting structure to solve the above problems. Tower 4 The purpose and summary of the invention: In view of the above invention, φ ^, becomes When the copper fuse was switched to the topmost level, several problems were encountered, such as the time μ μfan, / β ^ J ~ diameter, the laser device must be updated. Therefore, the present invention is hereby based on this — # Σ New copper fuse structure and its forming paper & degree of fine towels (CNS) A4 specification (21Q x 297 ^ 5 " Printed by Employee Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs 508783 A7
-~~----E 五、發明說明（） 法’以解決上述問題。 本發明的主要目的為提供一種可形成薄銅熔絲結構的 方法。 ' 本發明中另一目的為提供一種薄銅熔絲結構，來減低 燒斷銅溶絲所需之雷射能量，以降低製程成本。 本發明中形成薄熔絲結構的方法可包含以下步驟：提 供一半導體基材。於半導體基材上沈積第一介電層，並於第 一介電層埋設導體區域，此導體區域上表面與第一介電層上 表面共平面。形成第一氮化矽層於導體區域及第一介電層 上。依序於第一氮化矽層上形成第二介電層，第二氮化矽層 與第三介電層。形成第一光阻圖案於第三介電層上以定義介 層洞與銅熔絲開口。實施非等向性蝕刻以轉移第一光阻圖案 於第三介電層。再移除第一光阻圖案以形成介層洞與銅熔絲 結構’形成第二光阻圖案於第三介電層上，利用光阻將銅熔 絲開口填滿，並暴露出介層洞。實施第二氮化矽層蝕刻以暴 露出第二介電層。移除第二光阻圖案。形成第三光阻圖案於 第三介電層上以定義溝渠並填滿銅熔絲開口。實施非等向性 蚀刻以轉移第三光阻圖案於第三介電層上。實施第一氮化矽 層蝕刻以暴露出第一介電層所埋設導體區域。及移除該第三 介電層上之第三光阻圖案。 圖式簡單說明： 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------裝------丨—訂------ (請先閱讀背面之注意事項再填寫本頁) A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 、本發明中較佳具體實施例之細節#、+、 發明之目的、貝卽描述，可以對本 明之圖式加以說明： 的了解Μ參考下列本發 =一圖顯=傳統之熔絲窗結構的截面示意圖； 今方；^ Γ至第I圖所7為以傳統之雙讓嵌技術形成銅熔 、、、糸方法的流程剖面圖； 第六圖至第十圖，盆 _ 方法的流程剖面圖；’、斤不為以本發明之技術形成銅溶絲 同樣時第:具择圖顯不為在相同鋼熔絲寬度（〇.7um )下’進行 丨J银日f間長度之雷射嬙姻 田耵麂斷1程所顯示之SEM圖。 圖號對照說明： (請先閱讀背面之注意事項再填寫本頁) 10 16 22 32 37 銅溶絲窗 保護層 金屬導線 金屬導線 42 : 光阻圖案 40 : 銅熔絲開口 43:銅熔絲 61、64、όό : 介電層 63、65 : 氮化矽層 12、14、20: 介電層 1 8 :銅熔絲 31 、 34 、 36 : 介電層 3 3、3 5 :氮化矽層 3 9 ：溝渠 41:介層洞 44:導線連接 62 :金屬導線 6 7: 介層洞 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 29Γ^ 508783 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 68: 銅熔絲結構 69、70、71: 光阻圖案 72 、 73 :溝渠 發明詳細說明·· 在不限制本發明之精神及應用範圍之下，以下即以一實 施例’介紹本發明之實施。熟悉此領域技藝者，在瞭解本發 明之精神後，當可應用此種銅熔絲結構形成方法於各種不同 之積體電路的設計上，來將傳統形成於低介電常數介電層 (n-2)中之銅熔絲，改形成於Si〇x層中，以減低於燒斷 過程中’低介電常氣介電層所帶來之如散熱性差與機械強度 差等缺點，同時亦可減低所需蝕刻之困難性。並以一新的方 法，形成厚度薄之銅熔絲，來減低燒斷銅熔絲所需之雷射能 量，以降低製程成本。本發明之應用當不僅限於以下所述之 實施例。 第二圖至第五圖所示為一以傳統之雙鑲嵌技術形成銅 熔絲的方法流程剖面圖。參閱第二圖，若以n層銅金屬層所 構成之結構為例，其中介電層31為第n-1層，鋼& 32位於介電層31中。接著氮化石夕層33、介 η 4層34、氮化矽-~~ ---- E V. Description of the invention () Method 'to solve the above problems. The main object of the present invention is to provide a method capable of forming a thin copper fuse structure. '' Another object of the present invention is to provide a thin copper fuse structure to reduce the laser energy required to blow out the molten copper wire, thereby reducing the process cost. The method for forming a thin fuse structure in the present invention may include the following steps: providing a semiconductor substrate. A first dielectric layer is deposited on a semiconductor substrate, and a conductor region is buried in the first dielectric layer. The upper surface of the conductor region is coplanar with the upper surface of the first dielectric layer. A first silicon nitride layer is formed on the conductor region and the first dielectric layer. A second dielectric layer, a second silicon nitride layer and a third dielectric layer are sequentially formed on the first silicon nitride layer. A first photoresist pattern is formed on the third dielectric layer to define a dielectric hole and a copper fuse opening. An anisotropic etch is performed to transfer the first photoresist pattern to the third dielectric layer. Then remove the first photoresist pattern to form a via hole and a copper fuse structure. 'Form a second photoresist pattern on the third dielectric layer. Use the photoresist to fill the copper fuse opening and expose the via hole. . A second silicon nitride layer is etched to expose the second dielectric layer. Remove the second photoresist pattern. A third photoresist pattern is formed on the third dielectric layer to define a trench and fill the copper fuse opening. An anisotropic etch is performed to transfer the third photoresist pattern on the third dielectric layer. The first silicon nitride layer is etched to expose the conductor region buried in the first dielectric layer. And removing the third photoresist pattern on the third dielectric layer. Schematic description: This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) -------------- Installation ------ 丨 --Order ----- -(Please read the notes on the back before filling out this page) A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (, details of the preferred embodiments of the present invention #, +, the purpose of the invention, The description of Betty can be used to explain the diagram of Ben Ming: To understand M, please refer to the following book: a picture = a cross-sectional schematic diagram of the traditional fuse window structure; today; ^ Γ to Figure I 7 is a traditional double Let the embedding technology form a flow sectional view of the copper melting method. Figures 6 to 10 show the flow sectional view of the basin method. ', Do not use the same technique to form copper dissolving wire at the same time: The selective image display is not the SEM image displayed in the same process of the same laser fuse width (0. 7um) as the one performed by the laser 嫱 耵 田田 耵 耵 for the length of the interval between f and f. (Please read the precautions on the back before filling out this page) 10 16 22 32 37 Pattern 40: Copper fuse openings 43: Copper fuses 61, 64, 6: Dielectric layers 63, 65: Silicon nitride layers 12, 14, 20: Dielectric layer 1 8: Copper fuses 31, 34, 36: Dielectric layer 3 3, 3 5: Silicon nitride layer 3 9: Ditch 41: Intermediate hole 44: Wire connection 62: Metal wire 6 7: Intermediate hole This paper applies Chinese National Standard (CNS) A4 specification (210 X 29Γ ^ 508783 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () 68: Copper fuse structure 69, 70, 71: Photoresist pattern 72, 73: Detailed description of the trench invention ... Under the spirit and application scope of the present invention, the following describes the implementation of the present invention with an embodiment. Those skilled in the art can understand the spirit of the present invention and can apply this copper fuse structure forming method in various ways. In the design of different integrated circuits, the copper fuse traditionally formed in the low-k dielectric layer (n-2) was re-formed in the Si0x layer, so as to reduce the temperature during the blowout process. Disadvantages such as poor heat dissipation and poor mechanical strength brought by the dielectric constant gas dielectric layer can also reduce the need Difficulty of etching. A new method is used to form a thin copper fuse to reduce the laser energy required to blow out the copper fuse to reduce the process cost. The application of the present invention is not limited to the following Embodiments. The second to fifth figures show cross-sectional views of a method for forming a copper fuse by a conventional dual damascene technique. Referring to the second figure, if a structure composed of n copper metal layers is taken as an example, The dielectric layer 31 is the n-1th layer, and the steel & 32 is located in the dielectric layer 31. Next, the nitride nitride layer 33, the η 4 layer 34, and the silicon nitride
層35和介電層36(此為第11層）依序沉 I 阻圖安37於人Φ u 償上去。接著形成光 阻圖案37於介電層36上用以定義介層 藤錄之镱旗„ 〇。计、隹—人 做為後續金屬 導線之鑲嵌開口並進仃介電層36、氮化矽屉 34之蝕刻，最後移除光阻層37。 曰 與介電層 本紙張尺度適用中國國家標準（CNS)A4規格<21^7^7公釐） ----------— 裝--------訂--------- S (請先閱讀背面之注意事項再填寫本頁) 508783 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 參閲第三圖，接著形成一光阻圖案42用以定義溝渠 39，和銅熔絲開口 40。接著以氮化矽層35為停止層來進行 介電層3 6之餘刻。 參考第四圖’當介電層36蝕刻完成後，接著使用熱碟 酸進行氮化矽層33與35之蝕刻，其中金屬導線32可當作 一 #刻停止層。因此當蝕刻至金屬導線32表面時蝕刻即停 止，但其他部分會繼續被蝕刻，造成銅熔絲開口 4〇與溝渠 39會有過蝕刻情形發生，最後移除光阻圖案42。 參閱第五圖，回填銅層並對表面施以平坦化製程，即完 成以雙鑲嵌技術來同時形成金屬導線44與銅熔絲43。但是 以此傳統金屬鑲嵌技術所形成之銅熔絲43厚度太厚，對於 在成本考量與後續熔斷控制上會有不利之影響，因此本發明 提出一種新方法，用以降低其後之製成成本，並增加控制方 便性。 曰 工 參閱第六圖至第十圖，其所示為以本發明之技術形成 銅熔絲方法。以n層銅金屬層所構成之結構為例，其中介電 層61為第n-丨層，其蓋住完成部分積體電路之基板（圖中未 顯示出）。埋入該介電層61的是一金屬導線62且其上平面和 介電層61之上平面係共平面的。氮化矽層63先沉積於介電 層61和金屬導線62之上表面，接著介電層64和氮化矽層 依序沉積於氮化矽層63上，介電層66(此為第n層）再覆 蓋上去。此層通常為最頂層，且位於此層之銅金屬導線一般 疋作為電源線（power line )，因此其介電層材質通常為 --------------------^---------^9. (請先閱讀背面之注意事項再填寫本頁) A7The layer 35 and the dielectric layer 36 (this is the eleventh layer) are sequentially deposited in a resistive mode to compensate the person Φ u. Next, a photoresist pattern 37 is formed on the dielectric layer 36 to define the flag of the dielectric layer vine. 〇. The meter, the man-made as the inlay opening of the subsequent metal wire, and enter the dielectric layer 36 and the silicon nitride drawer 34 The photoresist layer 37 is removed at the end of the etching. The dimensions of the paper and the dielectric layer are in accordance with the Chinese National Standard (CNS) A4 specifications < 21 ^ 7 ^ 7 mm). -------- Order --------- S (Please read the notes on the back before filling out this page) 508783 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Referring to the third figure, a photoresist pattern 42 is then formed to define the trench 39 and the copper fuse opening 40. Then, the dielectric layer 36 is performed with the silicon nitride layer 35 as a stop layer. Refer to the fourth figure 'When the dielectric layer 36 is etched, the silicon nitride layers 33 and 35 are then etched using hot-disk acid. The metal wire 32 can be used as a #etch stop layer. Therefore, when the surface of the metal wire 32 is etched, the etching is Stop, but other parts will continue to be etched, causing over-etching of copper fuse opening 40 and trench 39, and finally removing the photoresist pattern 42. Referring to the fifth figure, the copper layer is backfilled and the surface is flattened, that is, the dual damascene technology is used to form the metal wire 44 and the copper fuse 43 at the same time. However, the copper fuse formed by this traditional metal damascene technology 43 The thickness is too thick, which will have an adverse impact on cost considerations and subsequent fusing control. Therefore, the present invention proposes a new method to reduce the subsequent manufacturing cost and increase the control convenience. To the tenth figure, which shows the method for forming a copper fuse by using the technology of the present invention. Taking the structure composed of n copper metal layers as an example, the dielectric layer 61 is the n-th layer, which covers the completed part. The substrate of the integrated circuit (not shown in the figure). The dielectric layer 61 is buried with a metal wire 62 and its upper plane is coplanar with the plane above the dielectric layer 61. The silicon nitride layer 63 is deposited first On the upper surface of the dielectric layer 61 and the metal wire 62, a dielectric layer 64 and a silicon nitride layer are sequentially deposited on the silicon nitride layer 63, and a dielectric layer 66 (this is the nth layer) is covered. The layer is usually the topmost layer, and the copper metal wires on this layer are generally疋 As a power line, the material of the dielectric layer is usually -------------------- ^ --------- ^ 9. (Please read the notes on the back before filling this page) A7
------------—----— --------- {請先閱讀背面之注意事項再填寫本頁) 508783 經濟部智慧財產局員工消費合作社印製 A7 Β7 五、發明說明（） 形發生。接著將覆蓋於介電層66上之光阻71移除。參閱第 十圖，回填以鋼層，並對銅層施以平坦化製程，即完成本發 明之銅熔絲製程。圖中可明顯看出，銅熔絲80厚度小於溝 渠82之厚度。 應用本發明之方法進行銅熔絲製程最大之優點是在 於，本發明之方法不像傳統以雙鑲嵌方式形成鋼熔絲之製 程，由於傳統上是以形成溝渠之同時形成銅熔絲開口，因此 所形成之銅熔絲開口深度會與溝渠一般深淺。而在本發明 中，雖然銅熔絲開口與介層洞蝕刻亦於同一製程中完成。但 是本發明於後續製程中，會利用光阻來保護鋼熔絲開口，因 而可減少銅熔絲開口受蝕刻之影響。應用本發明之製程可形 成較淺之銅、溶、絲肖口，，亦即可形成較薄之銅溶、絲，因此可降 低後續雷射燒斷製程所需之成本。 參閱第十一圖所示，為在相同銅熔絲寬度（〇 下， 進行同樣時間長度之雷射燒斷製程所顯示之sem圖。於圖 中可明顯看出，在銅熔絲厚度越薄之情況下，使用相同之雷 射能量，所達成之燒斷銅溶絲結構程度會愈好。例如，於雷 射能量纟0.6uJ的情況下，應用在銅溶絲厚度為〇62um所: 成，燒斷程度，明顯優於銅熔絲厚度為0 90um所造成之燒 度。因此’很明顯的，降低銅炫絲厚度對於減少雷射燒 斷I程所須之成本有很大之助益。 本發明以一較佳實施例說明如上，而熟悉此領域技鼓 者，在不脫離本發明之精神範圍内，當可作些許更動或潤錦y 10 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297公釐） —-----—--------^----—1!^9 (請先閲讀背面之注意事項再填寫本頁) 508783 A7 B7 五、發明說明（ 而 域 領 同 等 其 及 圍 範 利 專 請 申 之 附 後 視 當 圍 範 護 保 利 專。 其定 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）-------------------- --------- {Please read the notes on the back before filling this page) 508783 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Making A7 B7 V. Description of the invention () Shape occurrence. Then, the photoresist 71 covering the dielectric layer 66 is removed. Referring to the tenth figure, the steel layer is backfilled and the copper layer is subjected to a flattening process to complete the copper fuse process of the present invention. It is apparent from the figure that the thickness of the copper fuse 80 is smaller than the thickness of the trench 82. The biggest advantage of applying the method of the present invention to the copper fuse process is that the method of the present invention is not the traditional process of forming a steel fuse in a dual damascene method. Since the copper fuse opening is traditionally formed at the same time as the trench is formed, The opening depth of the formed copper fuse will be as shallow as the trench. In the present invention, although the copper fuse opening and the via hole etching are also completed in the same process. However, in the subsequent process, the present invention uses a photoresist to protect the opening of the steel fuse, thereby reducing the influence of the opening of the copper fuse by etching. The application of the process of the present invention can form a shallower copper, molten, silk wire, and can also form a thinner copper molten, silk, so that the cost required for the subsequent laser burnout process can be reduced. Please refer to the eleventh figure, which is the sem diagram shown by the same length of time for the laser fuse process with the same copper fuse width (0 °. It can be clearly seen in the figure that the thinner the thickness of the copper fuse In the case of using the same laser energy, the degree of structure of the burned copper melting wire will be better. For example, when the laser energy is 0.6uJ, it is applied to the thickness of copper melting wire of 〇62um: The degree of burnout is significantly better than the burnout caused by the thickness of the copper fuse of 0 to 90um. Therefore, 'obviously, reducing the thickness of the copper dazzle wire will greatly help reduce the cost of the laser burnout I process. The present invention has been described above with a preferred embodiment, and those skilled in the art can make some changes or polish without departing from the spirit of the present invention. 10 This paper size applies the Chinese National Standard (CNS). A4 specifications (21〇χ 297 mm) —-----—-------- ^ ----— 1! ^ 9 (Please read the notes on the back before filling this page) 508783 A7 B7 V. Description of the invention Specifically its set (please read the note and then fill in the back of this page) Ministry of Economic Affairs Intellectual Property Office employees consumer cooperatives printed in this paper scale applicable Chinese National Standard (CNS) A4 size (210 X 297 mm)