TW544699B - Method of forming a fuse - Google Patents

Abstract

A surface of a semiconductor substrate defined with at least one fuse area and at least one bonding pad area. A conductive layer with a thickness of 12kA and a protective layer are sequentially formed on the surface of the semiconductor substrate. Then portions of the protective layer and portions of the conductive layer in the fuse area are etched to make the thickness for the remaining conductive layer in the fuse area be approximately 5kA. Finally a dielectric layer is formed on the surface of the semiconductor substrate, and portions of the first dielectric layer and portions of the protective layer in the bonding pad area are etched until reaching the top surface of the conductive layer.

Description

544699 V. Description of the invention (1) Field of the invention The present invention provides a method for making hot-melt silk, in particular-a method that uses two different yellow light and etching processes to fen n M. ^ And the method of making fuse and boruilng pad of the same layer of aluminum metal. Background note: In the early stage of the development of integrated circuits, aluminum metal combined with silicon dioxide dielectric material = a standard material used by the industry in the design of metal inter connect (7). Such a combination of materials has always been popular because of its proven etching technology. However, in recent years, with the line width of the process = 'integrated circuit technology has evolved to deep sub-micron (micron) 彳,' plus the realistic factors such as the speed requirements of the product, traditional aluminum / dioxygen = internal The connection system (Ai / Si〇2 interconnect system) has been gradually: hemp ^ 3 new private requirements and product specifications. Therefore, the copper process technology exhibition in recent years? Z low-dielectric constant material as an insulating layer between metals is also flourishing in power generation. Copper metal has a resistivity that is about 40% lower than aluminum metal. Digital materials can reduce the capacitive effect between metal wires. Generally speaking, del can effectively reduce the RC delay (RC Υ) generated during the transmission of electronic signals and greatly increase the performance of the product (perf0rmance). Or 3 In the structure of the integrated circuit, after each transistor (transist0r) unit cell (c e 1 1) is completed, it must be electrically connected to the

544699 V. Description of the invention (2) Metal wires of different metal layers are electrically connected to the solder pads through the metal wires. After the packaging is completed, the integrated circuit can be electrically connected to the solder pads through the solder pads. The terminal is electrically connected to an external circuit. In the structure of the memory (memory), some structures called fuses are often made at the top layer of the structure. Its function is that when some of the memory cells and words are contained in the memory, When there is a problem with the function of the word line or wire, you can replace it with other redundant memory cells, word lines, or wires. The method is to first cut the thermal fuse by a laser cutting (1 aserzip) step, and then by a laser repair step including cutting, linking, etc. To cut off the original electrical connections of bad memory cells, word lines, or wires, or to make some new electrical connections to compensate for scrapped memory cells, word lines, or wires. Please refer to FIGS. 1 to 4. FIGS. 1 to 4 are schematic diagrams of a method for manufacturing a thermal fuse 26 on a semi-conductor wafer in the conventional technology. As shown in FIG. 1, the conventional technique is to form at least one memory cell (not shown) or at least one transistor (not shown) on a silicon substrate 11 of a semiconductor wafer 10, and then on a stone evening substrate 1 1. Each of the wires 12 is formed thereon, and the different wires 12 are isolated by a first dielectric layer 14 (is ο 1 ate). Among them, the material of the lead 12 is inscription or copper. For the former, it is made by a continuous deposition, photolithography, and etching process; for the latter, a pair is usually used.

544699 V. Description of the invention (3) Production by dual damascence. The reason is that Ming is usually formed by using DG base plating method (DC megnetron sputtering), which is characterized by poor step coverage. Therefore, after the generation of 0.13 / zm, the line width (1 inewidth) When it becomes smaller, the aspect ratio (aspect rati 〇) is relatively increased, and the insufficient step coverage of aluminum becomes a serious problem. Although the so-called high-temperature aluminum technology (> 400) has been developed, aluminum's surface migration (sudaCe migration) rate is faster at high temperatures to improve its step coverage, but it still cannot reach the order To a satisfactory degree, although aluminum is easy to deposit and etch, and it is very cheap, it is still widely used by semiconductor factories. With copper as the wire, although there are various electrical advantages, the compounds formed by chlorine and copper have poor volatility. Copper cannot be etched by chemical reactions. It is necessary to use copper ions in the plasma to sputter the copper. It can be removed by physical momentum conversion, so it is more suitable for the dual damascene process to omit the copper metal etching step. As shown in FIG. 1, a second dielectric layer 16 is formed on the first dielectric layer 14 and the conductive line 12, and at least one via hole 18 is formed in the second dielectric layer 16. The via hole 18 passes from the top of the conductive line 12 to the top surface of the second dielectric layer 16. Subsequently, a metal layer 22 is formed on the surface of the semiconductor wafer 10, and the metal layer 22 fills the channel holes 18. It is worth noting that after the formation of the channel hole 18, a conductive plug can also be formed first by depositing and etching to form a metallic plug. A yellow light process is then performed using a photoresist layer (not shown) on

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5. Description of the invention (4) The positions of the pad 24 and the fuse 2 6 are defined in the metal layer 22 respectively. Finally, an anisotropic dry etching is used to form a solder pad 24 and a thermal fuse 26 in the metal layer 22, respectively. 7 As shown in FIG. 3, a second dielectric layer 28 is formed on the second dielectric layer 16, the bonding pad 24 and the thermal fuse 26, and the third dielectric layer 28 is also referred to as a passivation layer. ), And the third dielectric layer 28 completely covers the second dielectric layer 16, the bonding pad 24, and the thermal fuse 26. Then, an etching back process is performed, and the top of the third dielectric layer 28 is etched downward. It is worth mentioning that the third dielectric layer 28 must be made of a light-transmitting material so that the laser light can penetrate and cut the thermal fuse 26 when the laser is cut by laser (1 a s e r z i p). As shown in Figure 4, a yellow light-etching-process (PEP) is performed to remove the second " electrical layer 28, which is located above the glow pad 24, so that the metal material is exposed, so as to facilitate the final Component testing and packaging. Similarly, when selecting the material of the metal layer, aluminum or copper is usually selected. That is, the final thermal fuse 26 will be composed of aluminum or copper metal. If it is made of copper metal, it is usually made by electroplating (e 1 ectr ο p 1 ating), but copper is easy to evaporate due to its high melting point during laser cutting, which causes splash (splash). ) Phenomenon, 544699 V. Description of the invention (5) Finally, a serious problem of reliability (re 1 i ab i 1 ity) is caused. For example, it is composed of aluminum metal. Due to its unique electromigration phenomenon, the thickness of the process generation above 0 · 13 // m often increases its thickness to avoid the occurrence of metal open circuit. Causes difficulties in the process, and it is difficult to cut off the laser during subsequent laser cutting. Although the current technology can adjust the laser light energy by adjusting the laser spot size, The greater the energy of the light, the higher the chance of damage to the underlying structure. At the same time, when the channel holes are also made of aluminum, the lack of step coverage can easily cause problems. Therefore, how to develop a new process using aluminum metal as the material of the thermal fuse without causing difficulties in the subsequent laser cutting process has become a very important issue. Summary of the invention == 丄 The main purpose of the present invention is to provide a method for making hot fuses. 二 2: Ϊ: The method of using the same layer of aluminum metal and two different yellow light and etching to install the king wire and materials to solve The above problem. In the preferred embodiment of the present invention,-the hot-spun area and a pad area: to? -It means that the surface of the conductor substrate sequentially forms a thick = conductor substrate, #contacting the protective layer and the V layer on the upper part of the silk region, so that the thickness of the conductive layer on the hot-wired region remains. About 5kA,

544699 Invention description (6) 5 is used as a thermal fuse for a circuit in the semiconductor substrate. Finally, a dielectric layer is formed on the surface of the semiconductor substrate, and the "electrical layer" and the protective layer on the upper part of the pad area are etched to the surface of the conductive layer. Due to the method for making a thermal fuse according to the present invention, a hot-wire cover is first used.

Curtain (fuse mask) and an added photo-etching-process (pep) to remove the first " electrical layer, which is located above the thermal fuse, into a thermally-wired opening (juse 〇pening) Then, an anisotropic dry etching process is used to remove a part of the metal layer under the opening of the thermal fuse, and then an oxide layer is formed on the surface of the semiconductor substrate. A pad mask and another A yellow light and etching process forms a passivating opening. In this way, without the need to increase any metal deposition process, the thickness of the thermal fuse will be effectively reduced due to the added yellow light and etching process and the subsequent anisotropic dry etching process. Therefore, during laser cutting of thermal fuses, it is too rare to cause the shao layer to be too thick to be cut off, and because the oxide layer at the end of the thermal wire is formed by the deposition method, and the traditional Compared with the method, the thickness of the oxide layer itself is better. In addition, the thickness of the alloy is still maintained at the original metal layer thickness, so it can be used for bQndabillty. ^ Good

Detailed description of the invention Please refer to FIGS. 5 to 9, which are the flat conductors according to the present invention.

Page 10 544699 V. Description of the invention (7) A schematic diagram of a method for making a thermal fuse π 6 on a wafer · 100. As shown in FIG. 5, the semiconductor chip 100 includes a silicon substrate 100, and at least one memory cell (not shown) or at least one transistor (not shown) has been formed on the silicon substrate 100. The method of the present invention is to form individual wires 102 on a silicon substrate 100, and different wires 102 are isolated by a first dielectric layer 104. The 'wire 102' may be a metal interconductor or a dual damascence structure conductor electrically connected to a conductive plug, and the conductor 102 The material is aluminum or copper. For the former, it is made by a continuous deposition, photolithography, and etching process; for the latter, it is usually made by a dual damascene process. As mentioned earlier, in the current semiconductor manufacturing process, aluminum is usually formed by DC sputtering (DC megnetron sputtering), which is characterized by poor step coverage capability. For more than one generation, the line width (1 inewidth) becomes smaller and the aspect ratio (relatively higher), and the lack of aluminum step coverage capability becomes a serious problem. At present, although the so-called high temperature aluminum technology 40 (Tc) has been developed, which improves the step coverage ability of I Lu by a faster surface migration rate at high temperatures, it still cannot reach Satisfactory, but it has the characteristics of easy deposition, etching and cheap, so it is still widely used by various semiconductor factories. And using copper as the wire, although there are various electrical advantages, the compounds formed by chlorine and copper are volatilized. The difference in force between steel and steel cannot be carried out by chemical reaction.

544699 V. Description of the invention (8) The copper ion can be removed by physical momentum conversion when it is splashed with copper ions. Therefore, it is more suitable for the dual-damascene process to omit copper metal. As shown, a second dielectric layer 106 is then formed on the first dielectric layer 104 and the wire 102, and at least one via hole 108 is formed within the second dielectric layer 106, and The via hole 108 passes from the top of the conductive line 102 to the top of the second dielectric layer 106. Subsequently, an aluminum metal layer U2 with a thickness of about 12KA was formed on the surface of the semiconductor wafer J 〇, and the metal layer 112 filled the channel hole 108. Then, a yellow light process is performed, and a resist layer (not shown) is used in the metal layer 112 to define the positions of the pad n4 and the fuse wire 1 1 6 respectively. Finally, a first anisotropic dry etching (811 丨 30 " ^? 丨 0 (1161 :(: 11 丨 1 ^)) process is used to define a pad 1 1 4 and a thermal pad in the metal layer 112. Dissolving wire 1 1 6. It is worth noting that after forming the channel hole 108, a deposition and coining process can also be used to form a conductive plug first, and then form a metal layer 112. As shown in FIG. As shown in FIG. 7, a third dielectric layer 118 is formed on the second dielectric layer 106, the pad π 4 and the thermal fuse 116, and is used as a passivation layer. The electrical layer 118 completely covers the second dielectric layer 106, the bonding pads 1 1 4 and the thermal fuse 1 丨 6. Then, a first yellow light cum #etching process (PEP) is performed, using a Fuse mask (not shown), removed above thermal fuse 1 丨 6

544699 V. Description of the Invention (9) --- The third dielectric layer 118 forms a fuse opening 122. As shown in FIG. 8, the second non-isotropic dry money engraving process is then performed to remove a part of the metal layer 112 having a thickness below the thermal fuse opening 1 22 until the thickness of the remaining thermal fuse 116 is about 5 ka. Subsequently, an oxide layer 124 is formed on the surface of the semiconductor wafer 100 to a thickness of about 1 κ. The oxide layer 124 is made of a light-transmitting material ^, so that the laser light can penetrate and cut off the thermal fuse 1 6 when laser zip is performed subsequently. As shown in FIG. 9, a second yellow light and etching process is performed, and a pad mask (not shown) is used to remove the oxide layer 124 and the third dielectric layer Π8 above the solder pad 114. In order to form a passivation opening 126, and expose the metal material of the pads 14 to 14 to be used as pad openings, in order to facilitate the final component testing and packaging. Due to the method for making a thermal fuse according to the present invention, a thermal fuse cover and a yellow light and etching process are first used to remove the third dielectric layer 'above the thermal fuse to form a thermal fuse opening, and then An anisotropic dry etching process is used to remove a part of the metal layer under the thermal fuse opening, and an oxide layer is formed on the surface of the semiconductor substrate. Finally, a solder mask and another yellow light and etching process are used. A pad opening is formed in the protective layer. In this way, the present invention can greatly reduce the thickness of the heat-emitting wire without increasing the metal deposition process. So in the follow-up

Page 13 544699 V. Description of the invention (ίο) During laser cutting, there will not be a situation where the oxide layer on the top of the thermal fuse is too thick and cannot be cut off, and the etchback method is compared. The method is formed, so the uniformity with the traditional degree is better. In addition, the thickness of the oxide layer on the surface of the thermal fuse is ^ t, so the thickness of the ^ can still be maintained at the original metal layer (b0ndabillty) at the time of construction, compared to the conventional method. Method for making hot-dazzle wire, and-Huang Guang and etching process use of the earth-the use of thermal fuses to remove part of the thickness of the metal I, melting: fuse opening, and go without adding any metal deposition structure ... Invention: Ming welding cymbals and thinner hot wire, in order to avoid G ,,, and 糸 during the laser cutting and cutting, the aluminum layer is too thick and the helmet is free ..., and the thickness of the welding pad is still maintained at the original metal Layer, thick; good bondability when broken structure. The description of X effective edge is only the preferred embodiment of the present invention, and all equivalent changes and modifications made according to the spine of the patent of the present application cover the scope of π. Bai Ying belongs to the patent of the present invention. Page 14 544699 Brief description of the diagrams Brief description of the diagrams Figures 1 to 4 are schematic diagrams of a conventional method for making a thermal fuse on a semiconductor wafer. 5 to 9 are schematic diagrams of a method for fabricating a thermal fuse on a semiconductor wafer in the present invention. Symbols shown in the figure 10 '100 semiconductor wafer 101 silicon substrate 12 to 102 wires 14, 104 first dielectric layer 16 ^ 106 second dielectric layer 18> 108 channel holes 22 to 112 metal layer 24> 114 pads 26 ^ 116 Soluble wire 28> 118 Second dielectric layer 122 Fuse open V 124 Oxide layer 126 Protective layer open π

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Claims (1)

544699 6. Scope of patent application 1. A method for fabricating a conductive layer on a substrate. The surface of the substrate defines a first region and a second region. The method includes the following steps: In the first region And forming at least one conductive layer on each of the second regions; forming a first dielectric layer on the surface of the substrate and covering each of the conductive layers; removing the first dielectric located inside the first region Layer and part of the conductive layer so that the conductive layer in the first region remains to a predetermined thickness; and removing the first dielectric layer located in the interior of the second region until the surface of the conductive layer . 2. The method of claim 1 in which the substrate is a semi-conductive substrate. 3. The method of claim 1, wherein the surface of the substrate further comprises at least a first dielectric layer and at least a conductor disposed in the second dielectric layer. 4. The method of claim 3, wherein the conductive object includes a conductive plug, a metal line, a metal interconnection, or a dual damascence structure) Conductor 544699 VI. Application for Patent Scope 5. The method of the third scope of application for patent, where the material constituting the conductive object includes Tungsten (W), copper (copper), aluminum (Aluminum), copper alloy (aluminum- copper-alloy), or other conductive materials. 6. The method according to item 1 of the patent application scope, wherein the first dielectric layer and a part of the conductive layer located inside the first region are removed so that the conductive layer in the first region remains to The method of the predetermined thickness includes the following steps: performing a first yellow light and etching process to form at least one first opening in the first dielectric layer in the first region that reaches the surface of the conductive layer; (open); and etching the conductive layer under the first opening so that the conductive layer in the first region remains to the predetermined thickness. 7. The method of claim 1, wherein before the first dielectric layer located in the second region is removed, a method is further included for forming a third dielectric layer on the surface of the substrate. To cover the first dielectric layer and the conductive layer in the first region. 8. The method according to item 7 of the patent application, wherein the method of removing the first dielectric layer located inside the second region includes the following steps: A second yellow light and etching process is performed, so that Part of the second zone Page 17 544699 6. Scope of patent application At least one second opening is formed in the third dielectric layer and the first dielectric layer to reach the surface of the conductive layer. 9. The method according to item 7 of the patent application, wherein the third dielectric layer is a light transmitting layer. 10. The method according to item 1 of the scope of patent application, wherein the thickness of the conductive layer is about 12 kA, and the predetermined thickness is about 5 kA. 1 1. The method according to item 1 of the scope of patent application, wherein the material constituting the conductive layer includes tungsten (tungsten, W), copper (copper), aluminum (Aluminum),! Lu copper alloy (aluminum-copper-alloy), or other conductive materials. 1 2. The method according to item 1 of the scope of patent application, wherein the first region is a thermal fuse region, and the conductive layer provided in the first region is used as a thermal fuse, and The second region is a bonding pad region, and the conductive layer provided in the second region is used as a bonding pad. 1 3. The method according to item 1 of the scope of patent application, wherein the first area is a core circuit area, and the second area is a peripheral circuit area, and is provided in the first area Both the region and the conductive layer in the second region are used as wires. 544699 VI. Application for patent scope 1 4. A method for manufacturing a fuse, the method includes the following steps: providing a semiconductor substrate 'and a surface of the semiconductor substrate defining a first region and a second region; Forming a first dielectric layer on the surface of the semiconductor substrate; and forming at least a first conductive layer and at least a second conductive layer each on the first dielectric layer in the first region and the second region; Forming a second dielectric layer on the surface of the first dielectric layer and covering each of the conductive layers; performing a first yellow light engraving process to the second dielectric in the first region At least one first opening is formed in the layer to reach the surface of the first conductive layer; removing the first conductive layer located below the first opening, and leaving the first conductive layer to a predetermined level Thickness for use as the thermal fuse; forming a third dielectric layer on the surface of the semiconductor substrate; and performing a second yellow light and etching process within the second dielectric layer in the second region A second opening is etched at least up to the surface of the second conductive layer. 15. The method according to item 14 of the scope of patent application, wherein the semiconductor substrate is a substrate. 16. The method according to item 14 of the scope of patent application, wherein the semiconductor substrate table Page 19 544699 The surface further includes at least one fourth dielectric layer, and the fourth dielectric layer includes at least one conductive object. 17. The method of claim 6 in claim 1, wherein the conductive object includes a conductive plug, a metal line, a metal interconnection, or a dual inlay structure. damascence structure) Conductor ° 1 8 · For example, the method described in item 14 of the patent, wherein the first dielectric layer further includes a plurality of conductive plugs. 19 · The method of claim 18 in the scope of patent application, wherein the method of forming each of the conductive plugs further includes the following steps: A first # engraving process is performed to form a plurality of dielectrics in the first dielectric layer. Via holes (viah ο 1 e); and a metal layer is formed within each of the via holes, and the metal layer fills each of the via holes. 20 · The method according to item 14 of the scope of patent application, wherein each of the conductive layers is an aluminum layer formed by a DC magnetron sputtering process and an etching process, and the third dielectric The electrical layer is a silicon oxide layer with a thickness of about 1 kA.