五 經濟部中央標準局員工消費合作社印製 508667 7854twf.doc/009 A7 B7 發明説明（/ ) 本發明是有關於一種使元件縮小的方法，更特別的是 有關於一種利用減少汲極植入範圍而縮小元件尺寸的方 法。 爲得到短、小、輕、薄的元件或應用系統，埋入式結 構的形成顯得相當重要，例如是埋入式汲極，其形成於各 種不同的記憶體元件中。然而，隨著系統或元件一再地縮 小，相對地也產生了一些製程上的問題，而導致元件的可 靠度降低，最常見的就是有效通道(Channel)的縮短。 第1圖繪不出利用傳統之方法所形成之一埋入式汲極 (Buried Drain，BD)，在基底1〇〇上，形成並定義一氧化層 /氮化層/氧化層(ΟΝΟ)堆疊102及一導電層104，以暴露出 部分的基底1〇〇，接著，對暴露的基底100實施一離子植 入製程，以形成一埋入式汲極106。由於埋入式汲極106 的離子濃度遠大於周邊的基底100,再加上在離子植入步 驟之後，通當會對埋入式汲極106進行回火，以重組埋入 式汲極106的晶格排列，如此，更強化了埋入式汲極106 內部摻質的向外擴散。而此一擴散的作用，使得通道區有 效長度變短。 除了形成埋入式汲極的離子植入步驟之外，通常還會 實施一口袋摻雜區以防止擊穿（Punch-through)，而理想的 口袋摻雜區（Pocket Doped Region)應該包覆住所有的埋入 式汲極區。第2A圖及第2B圖繪示出一種傳統的口袋摻 雜區及一種傳統的埋入式汲極。 第2A圖提供了一基底200，接著，形成並定義一堆疊 3 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲翁背面之注意事項再填寫本頁) 訂' 83. 3. 10,000 經濟部中央標準局員工消費合作社印製 508667 7 854twf. doc/009 A7 B7 五、發明説明（>) 層202及一導電層204。然後，再利用大角度離子植入208， 在基底200中形成一口袋摻雜區210。由於該口袋摻雜區 210是利用大角度離子植入所形成的，其輪廓如第2A所 示。在形成埋入式汲極206之後，如第2B圖所示，此一 口袋離子植入區210無法將埋入式汲極206完全包覆，而 使其效不佳，影響元件的可靠度。 因此，本發明提供了一種利用減少汲極植入範圍而縮 小元件尺寸的方法，首先，提供一基底，並在該基底上形 成一第一氧化層，一氮化層，以及一第二氧化層的堆疊層， 以及位於該第二氧化層上方之一導電層。利用形成一光阻 層於導電層的上方，以微影蝕刻法定義該導電層^並在其 中形成開口，以暴露出部分的第二氧化層。其中，暴露的 第二氧化層正下方的基底部分，即是欲形成口袋摻雜區的 預定部分。 接著，以已定義的導電層爲罩幕層，先對暴露的基底 進行口袋離子植入，以形成一口袋摻雜區。由於其摻雜濃 度不高，因此，不致於過度擴散至第一氧化層的下方以影 響閘極下方的通道長度。在形成口袋摻雜區之後，於已定 義之導電層的側壁上形成一間隙壁。此一間隙壁的形成使 得開口的寬度減小，也就是減少了暴露的基底部分，接著， 再去除暴露的第二氧化層及氮化層，以暴露出部分的第一 氧化層，再進行汲極離子植入，以在暴露的第一氧化層下 方之基底中形成一汲極。由於間隙壁的形成，被汲極離子 植入的基底完全被包覆在口袋摻雜區之內。此外，即使汲 4 ------------— (請先閲讀背面之注意事項再填寫本頁} -訂- 本紙張尺度適用中國國家標準（CNS ) A4洗格（210X297公釐） 83. 3. 10,000 508667 7854twf.doc/009 A7 B7 經濟部中央標準局貝工消費合作社印製 發明説明（5) 極離子會向濃度較低的區域擴散，由於其形成範圍縮小， 因此，在擴散之後，通道長度仍不致於被縮小，因此，有 利於元件尺寸的縮小，以得到產品的高積集度。 接著，利用熱氧化法，在暴露的基底上，也就是汲極 上方形成一埋入式汲極氧化層，再於基底上形成一字元線 (Word Line)。 在以上的實施例中，其中暴露之第二氧化層及其下方 的氮化層亦可以在形成間隙壁之前去除，如此，間隙壁不 但覆蓋了導電層的側壁，亦覆蓋了第二氧化層以及氮化層 的側壁，而不會影響本案所欲達成之主要目的。 在本發明之一實施例中，以上的方法可以用來形成一 NROM元件，又或者在另一實施中，在形成埋入式汲極區 以作爲埋入式位元線之後，可以該定義的導電層去除，在 埋入式位元線上形成一位元線氧化層，然後·再於基底上 形成一字元線，以形成一 SONOS元件。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1圖係一剖面圖，繪示出一種傳統埋入式汲極的 結構。 第2A圖係一剖面圖，繪示出一種傳統口袋離子植入 區的結構。 第2B圖係一剖面圖，係繪示出一種傳統之埋入式汲 5 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） 83. 3. 10,000 經濟部中央標準局員工消費合作社印裝 508667 7854twf.doc/009 A7 B7 五、發明説明（/V ) 極以及口袋離子植入區的結構。 弟3A圖至弟3D圖一*剖面圖’其繪不出基於本發明 之一較佳實施例中，一種埋入式汲極的形成方法，以及一 種包括此一埋入式汲極的記憶元件。 弟4圖係一'剖面圖5其繪75出基於本發明之另—^較佳 實施例中，一種埋入式汲極的形成方法，以及一種包括此 一埋入式汲極的元件。 圖式之標記說明： 100 :基底 102 :氧化層/氮化層/氧化層之堆疊層 104·:導電層 ’ 106 :埋入式汲極區 200 :基底 202 :氧化層/氮化層/氧化層之堆疊層 204 :導電層 2〇6 :埋入式汲極區 208: 口袋離子植入 21〇 : 口袋離子植入區 212 :汲極離子植入 300 :基底 302 :氧化層 3〇4 :氮化層 3〇6 :氧化層 308 :導電層 6 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐 ) 83. 3. 10,000 ——U—一—-----------Aw (請先閲讀背面之注意事項再填寫本頁) 508667 A7 B7 7 854twf. doc/009 五、發明說明（6) 310 : 口袋離子植入 312 : 口袋摻雜區 314 :間隙壁 316 :汲極離子植入 318 :埋入式汲極區 320 :汲極氧化層 322 :字元線 實施例 本發明將參考附圖，於以下詳細敘述之，其中本發明 之一較佳實施如以下所述，其中相似元件將使用一致之標 號。 第3A-3D圖繪示出依據本發明之一較佳實施例，請參 考第3A圖，首先，提供一基底300，例如是一個含有P-型或N-型摻雜的矽基底。在基底300形成一氧化層302， 一氮化層304以及一氧化層306而成爲一所謂的氧化層/ 氮化層/氧化層堆疊，在此，氧化層302之作用包括介於 浮置閘及基底之間的閘氧化層，氮化層304因具有載子捕 獲（Carrier Trapping)的功能，可以取代傳統的導體或複晶 矽浮置閘，針對其特殊的功能，在此又稱爲捕捉層(Trapping Layer)，而氧化層306則可用作爲控制閘和浮置閘之間的 氧化層，因此，氧化層302，氮化層304，及氧化層306 的厚度必需控制得當以達到其所應用的功能。接著，在氧 化層306的上方形成一導電層308,其最好是一複晶矽層， 以作爲元件之控制閘。 7 本紙張尺度適用中國國家標準（CNS)A4規恪（210 X 297公釐) " ' (請先閱讀背面之注意事項再填寫本頁) ---1--丨訂------ ——線泰 經濟部智慧財產局員工消費合作社印製 508667 7854twf·d〇c/009 Λ7 B7 五、發明說明（u) (請先閱讀背面之注意事項再填寫本頁) 利用微影蝕刻製程，導電層308被定義而暴露出部分 的氧化層306 ’利用被定義的導電層308爲罩幕層，對暴 露的氧化層306下方的基底300進行一 口袋離子植入310， 以在相鄰的兩個導電層308之間的基底300中形成一口袋 摻雜區312。 接著’請參考第3B圖，在被定義導電層308的側壁 上形成一間隙壁314，然後再去除暴露的氧化層306及氮 化層304,以暴露出部分的氧化層3〇2。·移除暴露氧化層3〇6 及其下方之氮化層304的步驟亦可以在形成間隙壁314之 前進行’如此，間隙壁314的形成不但覆蓋了導電層308 的側壁’亦覆蓋了氧化層306及氮化層304的側壁。以上 兩種形成皆不會影響本案縮小元件且保持元件之可靠度的 目的。形成間隙壁314的步驟包括先在該基底300上形成 一間隙壁材料，例如是一介電材料，再利用回蝕步驟去除 部分的間隙壁材料，以形成該間隙壁3 14。 經濟部智慧財產局員工消費合作社印製 接著，如第3C圖所示，對暴露的氧化層302下方， 口袋摻雜區312內的基底300進行汲極離子植入316，以 形成埋入式汲極區3 18。在此，間隙壁3 14的形成覆蓋了 暴露之氧化層302的邊緣部分，使得汲極離子植入316的 範圍變小’導致埋入式汲極區318的形成可以侷限於口袋 離子植入區312的範圍之內，即使因其高濃度載子的擴散 特性或後續高溫度而造成汲極區離子的向外擴散，其所擴 散的範圍也不會影響到通道的長度。此外，間隙壁314的 厚度可以調整，以針對不同元件對通道長度的要求控制埋 8 本紙張尺度適用中國國家標準（CNS)A4規恪（210 X 297公餐） 508667 A7 7854twf.doc/009 五、發明說明（、） 入式汲極區318的範圍。 (請先閱讀背面之注意事項再填寫本頁) 如第3D圖所示，在形成埋入式汲極區318之後，可 利用熱氧化法，在埋入式汲極318上方形成一汲極氧化層 320。然後，在於基底300上形成一導電層322以作爲字 元線。第3A-3D圖中所示之實施例可應用作爲一 NR〇m 元件，其中，該埋入式汲極區318即爲NROM元件之埋 入式位元線。 在本發明的另一個實施例中，是在形成被口袋摻雜區 312包覆之埋入式汲極區318，以及其上方之汲極氧化層 320之後，將導電層308予以去除。接著，.如第4圖所示， 先在埋入式汲極區318表面形成一汲極氧化層320，再於 基底300上形成一字元線322。此一方法可應用作爲一 SONOS元件之形成方法。其中，埋入式汲318即爲埋入 式位元線，而其表面之氧化層320則作爲位元線氧化層。 經濟部智慧財產局員工消費合作社印製 雖然本發明已以較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發 明之精神和範圍內，當可作各種之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者 爲準。 9 本纸張尺度適用中國國家標準（CNS)A4規烙（210 x 297公釐）Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 508667 7854twf.doc / 009 A7 B7 Description of the Invention (/) The present invention relates to a method for reducing the size of the component, and more particularly to a method for reducing the range of sinker implantation. And the method of reducing the component size. In order to obtain short, small, light, and thin components or application systems, the formation of embedded structures is very important, such as embedded drains, which are formed in various memory elements. However, as the system or component has been shrinking again and again, some process problems have also occurred, resulting in a decrease in the reliability of the component. The most common is the shortening of the effective channel. Figure 1 does not show a buried drain (BD) formed by traditional methods. On the substrate 100, an oxide layer / nitride layer / oxide layer (NO) stack is formed and defined. 102 and a conductive layer 104 to expose a part of the substrate 100. Then, an ion implantation process is performed on the exposed substrate 100 to form a buried drain electrode 106. Because the ion concentration of the buried drain 106 is much higher than that of the surrounding substrate 100, and after the ion implantation step, Tongdang tempers the buried drain 106 to reorganize the buried drain 106. The lattice arrangement, in this way, further enhances the out-diffusion of the dopants inside the buried drain 106. The diffusion effect shortens the effective length of the channel area. In addition to the ion implantation step to form a buried drain, a pocket doped region is usually implemented to prevent punch-through, and the ideal pocket doped region should be covered All buried drain regions. Figures 2A and 2B illustrate a conventional pocket doped region and a conventional buried drain. Figure 2A provides a substrate 200, and then a stack of 3 is formed and defined. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back of Weng before filling this page). 83. 3. 10,000 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 508667 7 854twf. Doc / 009 A7 B7 V. Description of the invention (>) Layer 202 and a conductive layer 204. Then, a large-angle ion implantation 208 is used to form a pocket doped region 210 in the substrate 200. Since the pocket doped region 210 is formed by high-angle ion implantation, its profile is as shown in Fig. 2A. After the buried drain 206 is formed, as shown in FIG. 2B, the pocket ion implantation region 210 cannot completely cover the buried drain 206, which makes it ineffective and affects the reliability of the device. Therefore, the present invention provides a method for reducing the size of a device by reducing the implantation range of a drain electrode. First, a substrate is provided, and a first oxide layer, a nitride layer, and a second oxide layer are formed on the substrate. A stacked layer, and a conductive layer over the second oxide layer. A photoresist layer is formed on the conductive layer, and the conductive layer is defined by lithography and an opening is formed in the conductive layer to expose a part of the second oxide layer. Among them, the portion of the substrate directly below the exposed second oxide layer is a predetermined portion where a pocket doped region is to be formed. Next, using the defined conductive layer as a mask layer, pocket ion implantation is performed on the exposed substrate to form a pocket doped region. Because its doping concentration is not high, it does not cause excessive diffusion below the first oxide layer to affect the channel length below the gate. After forming the pocket doped region, a spacer is formed on the sidewall of the defined conductive layer. The formation of this gap wall reduces the width of the opening, that is, reduces the exposed base portion. Then, the exposed second oxide layer and the nitride layer are removed to expose a portion of the first oxide layer, and then drained. The polar ion is implanted to form a drain in the substrate under the exposed first oxide layer. Due to the formation of the spacer, the substrate implanted by the drain ion is completely enclosed within the pocket doped region. In addition, even if you draw 4 ------------— (Please read the precautions on the back before filling in this page} -Order-This paper size is applicable to China National Standard (CNS) A4 Washing (210X297) 83. 3. 10,000 508 667 7854twf.doc / 009 A7 B7 Description of invention printed by Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs (5) Polar ions will diffuse to areas with lower concentrations. Due to their reduced formation range, After diffusion, the channel length is still not reduced, so it is beneficial to reduce the size of the component to obtain a high degree of product integration. Next, a thermal oxidation method is used to form a layer on the exposed substrate, that is, above the drain. A buried drain oxide layer is formed on the substrate to form a word line. In the above embodiment, the exposed second oxide layer and the nitride layer below it may also be formed before forming the barrier wall. In this way, the spacer not only covers the side walls of the conductive layer, but also covers the side walls of the second oxide layer and the nitride layer, without affecting the main purpose of the present invention. In one embodiment of the present invention, the above The method can Used to form an NROM device, or in another implementation, after forming a buried drain region as a buried bit line, the defined conductive layer can be removed to form a buried bit line. The bit line is oxidized, and then a word line is formed on the substrate to form a SONOS device. In order to make the above and other objects, features, and advantages of the present invention more obvious and easier to understand, the following specific implementation is preferred. The example and the accompanying drawings are described in detail as follows: Brief description of the drawings: Fig. 1 is a cross-sectional view showing the structure of a traditional buried drain. Fig. 2A is a cross-sectional view. Figure 2B shows the structure of a conventional pocket ion implantation area. Figure 2B is a cross-sectional view showing a traditional embedded type 5 (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) 83. 3. 10,000 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 508667 7854twf.doc / 009 A7 B7 V. Description of the invention (/ V) pole and pocket ion implantation The structure of the district. 3D picture 1 * cross-sectional view, which can not draw a method for forming an embedded drain and a memory device including the embedded drain in a preferred embodiment of the present invention. FIG. 5 is a cross-sectional view of FIG. 5 showing another method based on the present invention, a method for forming a buried drain, and a component including the buried drain in a preferred embodiment. Description: 100: substrate 102: stacked layer of oxide layer / nitride layer / oxide layer 104 ·: conductive layer 106: buried drain region 200: substrate 202: stacked layer of oxide layer / nitride layer / oxide layer 204: conductive layer 206: buried drain region 208: pocket ion implantation region 21: pocket ion implantation region 212: drain ion implantation 300: substrate 302: oxide layer 304: nitride layer 3 〇6: Oxide layer 308: Conductive layer 6 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 83. 3. 10,000 ——U— 一 ——------------ -Aw (Please read the notes on the back before filling this page) 508667 A7 B7 7 854twf. Doc / 009 V. Description of the Invention (6) 310: Pocket ion implantation 312: Pocket Doped region 314: spacer 316: drain ion implantation 318: buried drain region 320: drain oxide layer 322: word line embodiments The present invention will be described in detail below with reference to the drawings, of which One preferred embodiment of the invention is described below, in which similar elements will be given the same reference numerals. 3A-3D illustrate a preferred embodiment according to the present invention. Please refer to FIG. 3A. First, a substrate 300 is provided, such as a silicon substrate containing P-type or N-type doping. An oxide layer 302, a nitride layer 304, and an oxide layer 306 are formed on the substrate 300 to form a so-called oxide layer / nitride layer / oxide layer stack. Here, the role of the oxide layer 302 includes floating gates and The gate oxide layer between the substrates and the nitride layer 304 can replace the traditional conductor or polycrystalline silicon floating gate because of its carrier trapping function. For its special function, it is also referred to as the trap layer here. (Trapping Layer), and the oxide layer 306 can be used as an oxide layer between the control gate and the floating gate. Therefore, the thickness of the oxide layer 302, the nitride layer 304, and the oxide layer 306 must be properly controlled to achieve its application. Features. Next, a conductive layer 308 is formed over the oxide layer 306, which is preferably a polycrystalline silicon layer as a control gate of the device. 7 This paper size applies the Chinese National Standard (CNS) A4 (210 X 297 mm) " '(Please read the precautions on the back before filling this page) --- 1-- 丨 Order ----- -——Printed by 508667 7854twf · doc / 009 Λ7 B7, Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs of Line Thai. 5. Description of the invention (u) (Please read the precautions on the back before filling this page) Use photolithography etching process The conductive layer 308 is defined to expose a part of the oxide layer 306. Using the defined conductive layer 308 as a mask layer, a pocket ion implantation 310 is performed on the substrate 300 below the exposed oxide layer 306 to adjacently A pocket doped region 312 is formed in the substrate 300 between the two conductive layers 308. Next, please refer to FIG. 3B, a spacer 314 is formed on the sidewall of the conductive layer 308 defined, and then the exposed oxide layer 306 and the nitride layer 304 are removed to expose a part of the oxide layer 302. · The step of removing the exposed oxide layer 306 and the nitride layer 304 below it can also be performed before the formation of the spacer 314 'so that the formation of the spacer 314 covers not only the sidewalls of the conductive layer 308' but also the oxide layer 306 and the sidewalls of the nitride layer 304. The above two formations will not affect the purpose of reducing the components and maintaining the reliability of the components. The step of forming the spacer 314 includes forming a spacer material, such as a dielectric material, on the substrate 300, and then removing a part of the spacer material by using an etch-back step to form the spacer 314. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Then, as shown in FIG. 3C, the substrate 300 in the pocket doped region 312 under the exposed oxide layer 302 is subjected to a drain ion implantation 316 to form a buried drain. Polar region 3 18. Here, the formation of the spacers 31 and 14 covers the edge portion of the exposed oxide layer 302, so that the range of the drain ion implantation 316 becomes smaller. As a result, the formation of the buried drain region 318 can be limited to the pocket ion implantation region. Within the range of 312, even if the diffusion of the ions in the drain region is caused by the diffusion characteristics of the high-concentration carriers or the subsequent high temperature, the diffusion range does not affect the channel length. In addition, the thickness of the partition wall 314 can be adjusted to control the buried length according to the requirements of different components on the channel length. 8 The paper size applies the Chinese National Standard (CNS) A4 (210 X 297 meals). 508667 A7 7854twf.doc / 009 5 Description of the invention (,) The range of the in-drain region 318. (Please read the notes on the back before filling this page) As shown in Figure 3D, after forming the buried drain region 318, a thermal oxidation method can be used to form a drain oxidation over the buried drain 318. Layer 320. Then, a conductive layer 322 is formed on the substrate 300 as a word line. The embodiment shown in Figs. 3A-3D can be applied as a NR0m device, in which the buried drain region 318 is a buried bit line of the NROM device. In another embodiment of the present invention, the conductive layer 308 is removed after forming the buried drain region 318 covered by the pocket doped region 312 and the drain oxide layer 320 thereon. Next, as shown in FIG. 4, a drain oxide layer 320 is formed on the surface of the buried drain region 318, and then a word line 322 is formed on the substrate 300. This method can be applied as a method for forming a SONOS element. Among them, the buried drain 318 is a buried bit line, and the oxide layer 320 on the surface is used as the bit line oxide layer. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Various modifications and retouchings are made, so the protection scope of the present invention shall be determined by the scope of the appended patent application. 9 This paper size applies Chinese National Standard (CNS) A4 (210 x 297 mm)