TW507376B - Manufacturing process of heterojunction bipolar transistor - Google Patents

Abstract

A manufacturing process of heterojunction bipolar transistor (HBT) is disclosed, which comprises: providing a GaAs semi-insulating substrate; form the sub-collector layer, collector layer, base layer, InGaP layer and emitter layer; etch part of the emitter layer till the InGaP layer is exposed; utilize CMSI mask to etch the InGaP layer between etching the emitter layer and the base; then etch the base layer and the collector layer sequentially to fabricate HBT. The problem that the metal connection is broken in the postprocessing caused by the overhang effect in the well-known manufacturing method can be effectively solved by using CMSI mask to etch the InGaP layer. And thereby the yield rate and reliability of the product are enhanced.

Description

A7

507376 V. Description of the invention () Field of the invention: The present invention relates to a mass production process of a heterojunction bipolar transistor (Hetero_Junction Bipolar Transistor; hBT), and particularly to an improved arsenic in the integrated circuit manufacturing process. Mass production process for the performance of GaAs heterojunction bipolar transistors. BACKGROUND OF THE INVENTION: The application of 'heterojunction bipolar transistors' in the fabrication of integrated circuits is very wide. The NPN gallium arsenide heterojunction bipolar transistor system uses N-type gallium arsenide as the collector, P-type gallium arsenide as the base, and N-type gallium and aluminum gallium arsenide (AlGaAs) or phosphating. Indium gallium (IriGaP) is an emitter structure. Due to the difference in energy gap between the N-type indium gallium phosphide emitter and the p-type gallium arsenide base, the NPN gallium arsenide heterojunction bipolar transistor still maintains high current gain at high frequency operation, so HBT is An integrated circuit plays an important role. (Please read the notes on the back before filling this page)

Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs or Gallium-Aluminum-AlGaAs Arsenic is used for this purpose, and β and -JJ 1-a small number is a barrier factor. Gallium indium is radiated as a gallium indium hole base and because of its high energy efficiency, the gallium polarized arsenic is emitted at a higher rate than the & To the flowable heteropolar doped base electrode \) / This paper size applies the Chinese national standard (cns) a4 specification (210 X 297 mm) / b

It will not sacrifice the effect of the emitter. Therefore, the base resistance will be less, so the gain will greatly improve the frequency response. However, when HBT is used to form an integrated circuit, the size of the electron hole compound current will rapidly increase. The addition of the center between the emitter and the base causes the base current to increase and the current gain is greatly reduced. Therefore, in general, HB diodes need to add a layer of protection parity (Passivation Ledge) between the emitter and the base to protect Exposed base region. At present, there are generally two types of HBT-containing processes, one is aluminum gallium arsenide / gallium arsenide hbt, which uses aluminum gallium arsenide as a protection platform, and the other is indium gallium phosphide / galvanized hb. (Please read the precautions on the back before filling out this page.) Because InGaP / GaAs HBT uses indium gallium phosphide as a protection platform, indium gallium phosphide / gallium arsenide HBT is better than aluminum gallium arsenide / GaAs hbt has better current gain and collector current characteristics and better product life. However, in the process of indium gallium phosphide / gallium arsenide YBT, the overhang effect and the lack of installation with different etching rates in different directions often occur. -Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to Figures 1A to ic, which are cross-sectional diagrams showing the manufacturing process of the conventional ΗΒΤ. As shown in FIG. 1A, the conventional process of indium gallium phosphide / gallium arsenide HBT is: providing a gallium arsenide semi-insulating substrate 100; sequentially forming a sub-collector layer 1 on the gallium arsenide semi-insulating substrate 100 20. The collector layer 140, the base layer 160, the indium gallium phosphide layer 180, and the emitter layer 200. This paper size applies to China National Standard (CNS) A4 (210 X 297)

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention () Then, as shown in Figure 1B, the emitter layer 200 is etched with phosphoric acid and the required part is reserved. Gallium layer up to 80. Then, as shown in FIG. 1C, before etching the base layer, the indium gallium phosphide layer 180 is first etched with concentrated hydrochloric acid, and then the collector layer is etched with phosphoric acid 140 until the secondary collector layer 12 is completely exposed. . However, because concentrated hydrochloric acid only engraved a portion of the indium gallium phosphide layer 180 'and the pot acid which etched the collector layer 140 did not etch the scaled indium thallium layer 180', thus making the indium gallium phosphide layer 18 °. An overhang effect 220 is formed as shown in FIG. Please refer to Figure 2, which is a schematic diagram of the HBT cross-section when metal wires are made using the HBT produced by the conventional HBT process. Due to the effect of the roofing effect ', this eaves 3 1 0 will cause the metal connection 3 3 0 of the subsequent process to break the line 350 when it crosses the eaves 310, thus affecting the yield and reliability of the product. In addition to this shortcoming, the etching rate in the process is also affected to some extent because of the effect of the eaves effect. If the standard cell of the HBT is octagonal, please refer to FIG. 3, which shows a schematic cross-sectional view of a conventional method for manufacturing an HBT with an octagonal shape. After forming a sub-collector layer 400, a collector layer 410, a base layer 420, an indium gallium phosphide layer 430, and an emitter layer 440 on the sintered gallium semi-insulating substrate in order, the photoresist mask is used to define And etching technology to etch the emitter layer 440, and use the indium gallium phosphide layer 430 as an etch stop layer to form an octagonal wood paper. Standards apply to Chinese National Standard (CNS) A4 (210 X 297 mm) — — — — — — -— — — III— ^ --------- (Please read the notes on the back before filling out this page) 507376 V. Peripheral of the description of the invention () and then sequentially remove the ministry layer 4 3 0, part of the base layer 420 and part of the collector acoustic layer 410 and then use the photoresist mask definition and etching technology to name the sub-collector layer 4rm, #, (Please read the precautions on the back before filling (This page) The layer 400 and the atheized gallium semi-insulating substrate 100 as an etch stop layer to form the perimeter of the octagonal outer circle y can be obtained as the structure shown in Figure 3 and Figure 4 shows the green as a furnace Sign 1 Ding Feng's top view according to the structure shown in Figure 3. In FIG. 3, since the etching rate of the collector layer 41o is changed by the effect of the house chip effect 45o, the edge of the emitter layer 44o with an octagonal periphery and the edge of the base layer 420 to the secondary collector are changed. The distance of each side of the octagonal periphery of the layer 400 is different, which affects the stray capacitance (Cbc) between the base layer 42 and the collector layer 41. Therefore, the base layer 42 and the collector layer The capacitance effect between 41 ° is different from expected, which will affect the high frequency characteristics of HBT. Purpose and summary of the invention:

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs_L In view of the above background of the invention, using the conventional manufacturing method of HBT, during the etching process, concentrated hydrochloric acid will only etch part of the indium gallium phosphide layer and the collector layer The phosphoric acid does not etch the indium gallium phosphide layer, so that the indium gallium layer forms an eaves effect. When metal wires are connected in subsequent processes, disconnection is easy to occur, which reduces the product yield. Moreover, the appearance of the eaves effect affects the stray capacitance (Cbc) between the base and the collector, which in turn affects the high-frequency characteristics of the HBT. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 507376

(Please read the precautions on the back before filling out this page) Therefore, the main purpose of the present invention is to provide a heteropolar junction bipolar electricity production process. In the integrated circuit manufacturing process, between the step of removing the emitter layer and the step of removing the base layer, the present invention operates a cmsi mask to define a phosphorous oxide gallium layer to solve the problem of eaves effect. According to the above object, the present invention provides a method for mass production of a heterojunction bipolar transistor. First, a semi-insulating substrate is provided; a sub-collector layer, a collector layer, a base layer, an indium gallium phosphide layer, and an emitter layer are sequentially formed on the semi-insulating substrate; a part of the emitter layer is removed until the phosphor is completely exposed. Indium gallium layer; provides a CMSI mask to define part of the indium gallium phosphide layer until the base layer is exposed; remove part of the base layer until the collector layer is fully exposed and remove part of the Collector layer until the sub-collector layer is exposed. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In the HBT process, between the step of removing the emitter layer and the step of removing the base layer, a CMSI mask is used to define the indium gallium phosphide layer and the indium gallium phosphide layer. The eaves effect no longer occurs, eliminating the possibility of disconnection during subsequent metal connections in the subsequent process, thereby improving product yield and reliability. And because the eaves effect no longer occurs, the stray capacitance (C be) between the base and the collector can be calculated and predicted, thereby increasing the high-frequency characteristics of the HBT. Brief description of the drawing: This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 507376 A7 B7 V. Description of the invention (The preferred embodiment of the present invention will be supplemented by the following explanatory text The graphics are explained in more detail, in which: Figures 1A to 1C printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs are not intended to illustrate the cross-section of the manufacturing process of the conventional HBT. Figure 2 shows the conventional use of HBT. The HBT cross-section schematic diagram of the HBT produced by the HBT manufacturing process when the metal connection is made. Figure 3 is a schematic diagram showing the cross-section of a conventional method for manufacturing an HBT with an octagon. Figure 4 is a diagram showing the structure according to the structure shown in Figure 3. Top view. Figure 5 is a schematic cross-sectional view of the manufacturing process using η b T according to an embodiment of the present invention. Figure 6 is a schematic cross-sectional view of the manufacturing process using η βτ according to an embodiment of the present invention. Fig. 7 is a schematic cross-sectional view of a ΗΒτ manufacturing process using an embodiment provided by the present invention. Fig. 8 is a cross-sectional view of a ΗΒτ manufacturing process using an embodiment provided by the present invention. FIG. 9 is a schematic cross-sectional view of an octagonal ΗBT manufacturing process using an embodiment provided by the present invention. FIG. 10 is a schematic view of a octagonal ΗBT manufacturing process using an embodiment provided by the present invention. Cross-section schematic diagram. Figure 11 shows the octagonal paper size of an embodiment provided by the present invention. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love (please read the precautions on the back before filling in) (This page)-»-------- Order-— 丨 丨 — ^ _ wi 507376 A7 B7 V. Description of the invention () A schematic cross-sectional view of the HBT manufacturing process. Figures 1 and 2 show the use of the present invention to provide A schematic cross-sectional view of an octagonal HBT manufacturing process according to an embodiment. Figure 1 J is a top view showing the structure shown in Figure 12. Figure No. Comparative Description: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 100 gallium arsenide semi-insulating substrate 120 secondary collector layer 140 collector layer 160 base layer 180 indium phosphide layer 200 emitter layer 220 eaves effect 3 10 eaves 330 metal connection 350 disconnection 400 secondary collector layer 410 set Electrode layer 420 base layer 430 Chemical layer 440 emitter layer 450 eave effect 520 gallium arsenide semi-insulating substrate 540 secondary collector layer 560 collector layer 580 base layer 600 indium gallium phosphide layer 620 emitter layer 700 secondary collector layer 710 collector layer 720 base layer 730 indium gallium phosphide layer 740 emitter layer invention Detailed description: This paper size applies to Chinese National Standard (CNS) A4 specification (210 X 297 public love) (Please read the precautions on the back before filling this page) · Nnnnn! In one eJ · t ϋ ntl II-507376

Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs _L A7 V. Description of Invention () 凊 Refer to Figure 5, which shows a schematic cross-sectional view of the HBT manufacturing process using an embodiment provided by the present invention. A semi-insulating substrate 520, and then a secondary collector layer 540 is formed on the Shishenhua gallium semi-insulating substrate 52, and then a collector layer 56, a base layer layer, a structured indium gallium layer 600, and a semiconductor layer are sequentially formed thereon. Polar layer 62. The above secondary collector layer 54 is an N-type gallium arsenide layer, the collector layer 56 is a low-concentration N-type gallium arsenide layer, the base layer 580 is a p-type gallium arsenide layer, and the emitter layer 62 is N-type marrying and filling marriage layer. Next, please refer to FIG. 6 ', which is a schematic diagram showing a surface of an HBT manufacturing process using an embodiment provided by the present invention. After the emitter layer is formed, a part of the emitter layer 620 is removed, for example, a mask is used to define the required range of the emitter layer. Please refer to FIG. 7, which illustrates a schematic cross-sectional view of an HBT manufacturing process using an embodiment provided by the present invention. After removing part 2 of the emitter layer 620, use a CMSI mask (not shown) to determine: = indium gallium phosphide layer 600, you can get the structure cross-section as shown in Figure 7. This CMSI Pattern of the mask and subsequent processes. The pattern of the photomask of the 580 base layer is the same. When making HBT's standard excision, 卞 I ~ horse octagon, each side of the mask of the CMSI is smaller than each side of the mask defining the base layer 58, which is about 0 · 4 μm to 1 · 2 μm, depending on the process. This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) #, installed -------- order --------- (Please read the precautions on the back before filling (This page) 507376 Α7

V. Description of the invention () Please refer to FIG. 8, which is a schematic cross-sectional view showing a manufacturing process of an HBT using an embodiment provided by the present invention. After the indium gallium phosphide layer 600 is defined by the CMSI mask, the base layer 5 80 is removed, and then the collector layer 560 is removed with acid filling until the sub-collector layer 540 is completely exposed. Through the above process steps, the eaves effect produced by the conventional HBT. Manufacturing method can be avoided, and the possibility of disconnection during the metal connection in the subsequent process is solved. Please refer to FIG. 9 ', which illustrates a schematic cross-sectional view of the manufacturing process of an octagonal Η B T using one embodiment of the present invention. A sub-collector layer 700, a collector layer 710, a base layer 720, an indium gallium phosphide layer 730, and an emitter layer 740 are sequentially formed on a gallium halide semi-insulating substrate 520, and the structure shown in FIG. 9 can be obtained. . Then use the photoresist mask definition and etching technology to etch the emitter layer 740, and use the indium gallium phosphide layer 73 0 as an etch stop layer to form an octagonal periphery. As shown in FIG. 10, it is shown as A schematic cross-sectional view of an octagonal QBT manufacturing process using an embodiment provided by the present invention. (Please read the precautions on the back before filling out this page) · I n I 1 ϋ d I one ot · mm ϋ in — 印 I A schematic cross-sectional view of an octagonal HBT manufacturing process using an embodiment provided by the present invention is shown. Then use the mask of CMSI to define the indium gallium phosphide layer 730 ° This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) 507376

V. Description of the invention () Remove part of the base layer 72 and part of the collector layer 71 in order, until the sub-collector layer 700 is completely exposed, and use the photoresist mask definition and surname engraving technology. The last collector layer 700 is engraved, and a gallium arsenide semi-insulating substrate 52 is used as an etching stop layer to form an octagonal periphery. As shown in FIG. 12, it is shown as one of the advantages provided by the present invention. A schematic cross-sectional view of the manufacturing process of the octagonal ΗΒτ in the embodiment, and FIG. 13 is a top view showing the structure shown in FIG. I 2. When an embodiment of the present invention is used to manufacture an HBT with a standard shape, the 720I is defined using the CMSI mask after removing the emitter layer 740 and the removed base layer 720 ′. The indium gallium iron layer 730 can avoid the eaves effect. Therefore, when the base layer 720 is etched in the subsequent process, the etch rate of each side of the octagon is isotropic, so that the sides of the emitter layer 740 and the emitter layer 740 can be maintained. The distance from each side of the base layer 720 to each side of the sub-collector layer 7 0 with an octagon is equal, so that the capacitive effect between the base layer 7 2 0 and the collector layer 7 1 0 is maintained in a stable range. , Which in turn makes the high-frequency characteristics of hbT easier for designers to control. (Please read the notes on the back before filling this page)

· Ϋ nnn · ϋ -ϋ * ϋ · One bit, I i 1_1 I— nn ϋ n I Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs The advantage of the present invention is to provide a mass production process for a heterojunction bipolar transistor, The mass production process uses a CM SI mask to define a canned indium-rhenium layer between the step of removing the emitter layer and the step of removing the base layer, in order to solve the conventional process method, because of the removal of arsenic Phosphoric acid in the collector layer of gallium will not remove the scaled indium gallium layer, which will cause the problem of eaves effect, so the subsequent processes are exempted. The paper size applies the Chinese National Standard (CNS) A4 (210 X 297 mm) A7 Explain that the metal wire in () may be disconnected, which will increase Γ + and reliability. Still another advantage of the present invention is to provide a heterogeneous mass production process method, the amount of I1 @ * bipolar transistor and earning pole ..., between the step of removing the emitter layer / the step of multiple removing the base layer, using ㈣ The photomask defines the indium hafnium solution. In the conventional manufacturing process, the etching rate of the collector layer due to the eaves effect is as large as the factor that affects the etching rate of the collector layer-the eaves effect has been resolved. When manufacturing a polygonal HBT (such as an octagonal HBT), the engraved rate of each side of the octagon when the surname is the base layer is an isotropic surname, so the sides of the emitter layer and the sides of the base layer to the sides of the octagon can be maintained. The distances are all equal 'so that the capacitive effect between the base and the collector is maintained in a stable range, which further makes the high-frequency characteristics of the HBT easier for the designer to control. As will be understood by those familiar with this technology, the above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention, and all others completed without departing from the spirit disclosed by the present invention, etc. Effective changes or modifications should be included in the scope of patent application described below. n II nnnnn afla * 1 · nninnnn tr --------- Aw. (Please read the precautions on the back before filling out this page) Printed on paper standards of the Ministry of Economic Affairs, Intellectual Property Bureau, Employees' Cooperatives, Chinese paper standards apply (CNS) A4 size (210 x 297 mm)

Claims (1)

507376 A8 B8 C8 D8 VI. Application for Patent Scope Printed clothing for employees' cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1. A mass production process of a heterojunction bipolar transistor, including at least: providing half of the insulating substrate; Forming a primary collector layer, a collector layer, a base layer, an indium hafnium layer, and an emitter layer on the substrate; removing part of the emitter layer until the indium gallium phosphide layer is completely exposed; Provide a photomask to define a portion of the indium gallium phosphide layer until the base layer is exposed; remove a portion of the base layer until the collector layer is fully exposed; and remove a portion of The collector layer is exposed until about the secondary collector layer. 2. The mass production process as described in item 1 of the scope of patent application, wherein the semi-insulating substrate is a gallium arsenide semi-insulating substrate. 3. The mass production process as described in item 1 of the scope of patent application, wherein the above secondary collector layer is an N-type gallium arsenide layer. 4. The mass production process as described in item 1 of the scope of patent application, wherein the collector layer is a low-concentration N-type deified graft layer. 5. The mass production process described in item 1 of the scope of patent application, in which the above (please read the precautions on the back before filling this page) Binding — Order --------- 13 This paper size applies to China Standard (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 507376 A8 B8 C8 D8 t. The base layer for patent application is a P-type gallium arsenide layer. 6. The mass production process as described in item 1 of the scope of patent application, wherein the above emitter layer is an N-type deified sacrificial layer. 7. The mass production process as described in item 1 of the scope of the patent application, wherein the emitter layer is an N-type gallium arsenide and indium gallium phosphide layer. 8. The mass production process as described in item 1 of the scope of patent application, wherein the above-mentioned photomask is a CMSI photomask. 9. A mass production process of a heterojunction bipolar transistor, wherein the heterojunction bipolar transistor has an octagonal shape, and the mass production process includes at least: providing a half of an insulating substrate; sequentially on the semiinsulating substrate Forming a primary collector layer, a collector layer, a base layer, a structured indium gallium layer, and an emitter layer; defining and removing the emitter layer until the indium gallium phosphide layer is completely exposed, and The emitter layer has an octagonal periphery; a photomask is provided to define a portion of the indium gallium phosphide layer until approximately the base layer is exposed; remove a portion of the base layer until the base layer is fully exposed A collector layer; and a portion of the collector layer is removed so that the secondary collector has an octagonal periphery. 14 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ------------- installation -------- order ----------- -(Please read the precautions on the back before filling this page) 507376 A8 B8 C8 D8t, printed by the consumer property cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the consumer cooperative 10 · The mass production process as described in item 9 of the scope of patent application The semi-insulating substrate is a gallium arsenide semi-insulating substrate. 11. The mass production process as described in item 9 of the scope of the patent application, wherein the secondary collector layer is an N-type gallium arsenide layer. 1 2. The mass production process according to item 9 of the scope of patent application, wherein the collector layer is a low-concentration N-type gallium arsenide layer. 13. The mass production process as described in item 9 of the scope of the patent application, wherein the base layer is a P-type gallium arsenide layer. 14. The mass production process as described in item 9 of the scope of patent application, wherein the emitter layer is an N-type gallium arsenide layer. 15. The mass production process as described in item 9 of the scope of the patent application, wherein the above emitter layer is an N-type ytterbium and structured indium gallium layer. 16. The mass production process as described in item 9 of the scope of patent application, wherein the photomask is a CMSI photomask. (Please read the precautions on the back before filling this page) -Packing ----- Order ---------. This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm)