TWI747565B - Heterojunction bipolar transistor - Google Patents

Abstract

A heterojunction bi-carrier transistor includes: a substrate with a first surface and a second surface on the opposite side; a sub-emitter layer located on the first surface of the substrate; and a composite emitter layer, It is located on the sub-emitter layer, so that the sub-emitter layer and the composite emitter layer form an emitter layer; a base layer is located on the composite emitter layer; a collector protrudes from the edge layer and is located on the base layer ; A collector layer, located on the edge layer of the collector protruding; a lateral oxidation zone, set in the first area of the composite emitter layer to form a current blocking area, and the first area of the composite emitter layer surrounds the composite emitter layer The second area makes the second area of the composite emitter layer form a current aperture.

Description

Heterojunction bi-carrier transistor

The present invention relates to a heterojunction bi-carrier transistor, especially a heterojunction bi-carrier transistor with the collector at the top and the emitter at the bottom.

Press, Heterojunction Bipolar Transistor (HBT) has an emitter, a base and a collector. Usually the emitter is located above. By applying Vce voltage and Vbe voltage, electrons are first injected from the emitter to the collector. Before the electrode, it is transported through the base layer, and electrons are injected from the base to the collector, and heat is generated during the flow of electrons from the emitter to the collector. However, the gain, maximum oscillation frequency and bandwidth are also highly dependent on the base-collector capacitance. How to reduce the base-collector capacitance is also the subject to be solved by the present invention.

The reason is that the main purpose of the present invention is to provide a heterojunction bi-carrier transistor, which reduces the collector-base capacitance and improves the large-signal radio frequency (RF) performance. RF transistors and power amplifiers have better gain, maximum oscillation frequency (fmax) and bandwidth.

Another object of the present invention is to provide a heterojunction bi-carrier transistor, which improves thermal performance, and also has better reliability and large-signal radio frequency performance due to reduced thermal energy.

Another object of the present invention is to provide a heterojunction bi-carrier transistor with reduced power amplifier size and reduced manufacturing cost of discrete radio frequency equipment and integrated circuits.

To achieve the above objective, the technical means adopted in the present invention include: a substrate with a first surface and a second surface on the opposite side; a sub-emitter layer located on the first surface of the substrate; and a composite emitter The layer is located on the sub-emitter layer, so that the sub-emitter layer and the composite emitter layer form an emitter layer; a base layer is located on the composite emitter layer; a collector protrudes from the edge layer, Is located on the base layer; a collector layer is located on the protruding edge layer of the collector; and a lateral oxidation zone is provided on a part of the composite emitter layer to form a current blocking area, and the composite emitter layer The first area surrounds the second area of the composite emitter layer, so that the second area of the composite emitter layer forms a current aperture.

According to the aforementioned features, the composite emitter layer is composed of a first emitter layer and a second emitter layer, and the second emitter layer is located on the first emitter layer.

According to the features disclosed above, the first emitter layer includes a first transition layer, an intermediate layer, and a second transition layer, and the material of the first transition layer is N ^- GaAs, and the material of the second transition layer is N ^- and material of GaAs of the intermediate layer is aluminum high content comprises _{Al x Ga 1-x as (} 0.80 ≦ x ≦ 0.98), and the lateral oxidation regions provided in the intermediate layer and the lateral oxidation zone of N ^- Al _x Ga _{1 -x} As.

According to the features disclosed above, a first selection layer is provided between the first transition layer and the intermediate layer, a second selection layer is provided between the intermediate layer and the second transition layer, and the material of the first selection layer is N ^- AlGaAs, the material of the second selection layer is N ^- AlGaAs.

According to the aforementioned features, the thickness of the first transition layer is 20-100nm, the doping species is Si, and the Si doping concentration is reduced from 4e18 to 3e17cm ^-3 ; the thickness of the lateral oxide region is 0.4-2.5nm, doped The species is Si and the Si doping concentration is 0-6e18 cm ^-3 ; the thickness of the second transition layer is 20-100 nm, the doping species is Si, and the Si doping concentration is 5e16-5e17 cm ^-3 .

According to the aforementioned features, the N ^- InGaP material of the protruding edge layer of the collector is ordered and has a band gap of approximately 18.5 eV.

According to the features disclosed above, the thickness of the first transition layer is 50nm, the doping species is Si and the Si doping concentration is reduced from 4e18 to 3e17cm ^-3 ; the thickness of the lateral oxide region is 1nm, the doping species is Si and the The Si doping concentration is 4e18cm ^-3 ; the thickness of the second transition layer is 50nm, the doping species is Si, and the Si doping concentration is 3e17cm ^-3 .

According to the aforementioned features, it further includes a base metal, the base metal is located on the collector protruding edge layer, and the base metal diffuses downward in the collector protruding edge layer and enters the base layer.

According to the aforementioned features, it further includes a base metal. The base metal is etched through the collector protruding edge layer to the base layer, and the base metal is deposited into the etching area and connected to the base layer.

According to the aforementioned features, the material of the base layer is P ⁺ GaAs, P ⁺ InGaAs, or a combination thereof.

According to the aforementioned features, a collector cap layer is further included, and the collector cap layer is located on the collector layer.

According to the features disclosed above, the material of the substrate is semi-insulating GaAs; the material of the sub-emitter layer is N ⁺ GaAs; the material of the second emitter layer is N ^- InGaP; the material of the base layer is P ⁺ GaAs; The material of the collector protruding edge layer is N ^- InGaP; the material of the collector layer is N ^- GaAs; the material of the collector cap layer is N ⁺ GaAs or N ⁺ InGaAs.

According to the features disclosed above, the thickness of the sub-emitter layer is 500~1000nm, the doping species is Si and the Si doping concentration is 1e18~2e19cm ^-3 ; the thickness of the second emitter layer is 30~60nm, doped The species is Si and the Si doping concentration is 5e16~5e17cm ^-3 ; the thickness of the base layer is 40~120nm, the doping species is C and the C doping concentration is 1e19~1e20cm ^-3 ; the collector protruding edge The thickness of the layer is 0.4~100nm, the doping species is Si and the Si doping concentration is 5e16~5e17cm ^-3 ; the collector layer is composed of a first collector layer and a second collector layer, the first The thickness of the collector layer is 300~1200nm, the doping species is Si and the Si doping concentration is 1e17~2e14cm ^-3 , the thickness of the second collector layer is 0~800nm, the doping species is Si and the Si doping The impurity concentration is 1e16~1e17cm ^-3 ; a collector transition layer, the collector transition layer extends to the second collector layer, the thickness of the collector transition layer is 20-100nm, the doping species is Si and the Si doped If the impurity concentration is greater than 1e19cm ^-3 , the collector cap layer extends to the collector transition layer, the collector cap layer has a thickness of 20-100 nm, the doping species is Si and the Si doping concentration is greater than 1e19 cm ^-3 .

According to the features disclosed above, the thickness of the sub-emitter layer is 800nm, the doping species is Si and the Si doping concentration is 4e18cm ^-3 ; the thickness of the second emitter layer is 50nm, the doping species are Si and the Si The doping concentration is 3e17cm ^-3 ; the thickness of the base layer is 80nm, the doping species is C and the C doping concentration is 3e19cm ^-3 ; the thickness of the collector protruding edge layer is 5nm, and the doping species is Si and The Si doping concentration is 3e17cm ^-3 ; the collector layer is composed of a first collector layer and a second collector layer, the thickness of the first collector layer is 900 nm, and the doping species is Si and the Si The doping concentration is 2e15cm ^-3 , the thickness of the second collector layer is 300nm, the doping species is Si and the Si doping concentration is 5e16cm ^-3 ; a collector transition layer, the collector transition layer extends to the first Two collector layers, the thickness of the collector transition layer is 50nm, the doping species is Si and the Si doping concentration is greater than 1e19cm ^-3 , the collector cap layer extends to the collector transition layer, the collector cap layer The thickness is 50nm, the doping species is Si and the Si doping concentration is greater than 1e19cm ^-3 .

According to the aforementioned features, at the junction of the base layer and the second emitter layer, the N ^- InGaP material of the second emitter layer is disordered or ordered.

According to the features disclosed above, it further includes an isolation implantation area, which is arranged on the sub-emitter layer and the substrate.

According to the aforementioned features, the material of the isolation implantation region is boron, argon, hydrogen, helium, aluminum or a combination thereof.

According to the aforementioned features, the collector cap layer and the collector layer form a first plateau, and the collector protruding edge layer, the base layer and the composite emitter layer form a second plateau, and the first plateau Smaller than the second plateau; an emitter metal located on the sub-emitter layer; a base metal located on the collector protruding edge layer, and the base metal diffuses downward on the collector protruding edge layer Enter the base layer; a collector metal is located on the collector cap layer; thereby, electrons flow from the emitter metal to the collector metal, and the current blocking region blocks the current, and only allows current to pass through the Current aperture.

According to the aforementioned features, it further includes a back metal located on the second surface of the substrate, and a back via hole is provided between the substrate and the sub-emitter layer, so that the back metal can be electrically connected through the back via hole Connect to the emitter metal.

According to the aforementioned features, it further includes an optional/optional under bump metal, which is directly connected to the collector metal; thereby, the heat flow from the heterojunction bi-carrier transistor passes through the under bump The bulk metal is conducted to a bump, which may be a solder bump, a flip chip bump or other bumps.

With the aid of the technical means, the present invention improves the effects of the prior art as follows: 1. The GaAs Vertical Cavity Surface Emitting Laser (VCSEL) technology can precisely control the distance of the lateral oxidation zone ( distance), uniformity (uniformity) and repeatability (repeatability), and the high content of aluminum including Al _x Ga _1-x As (0.80≦x≦0.98) in the lateral oxide zone has been greatly improved. Lateral oxidation technology can accurately control the current aperture to prevent electrons from being injected into the first plateau outside the region of the base metal, avoid electrons being recombined, trapped, and collected to the base metal, which will cause the performance of the transistor to decrease, and By reducing the base-to-collector capacitance, it produces better gain, maximum oscillation frequency, bandwidth, power and performance. 2. Making the base metal diffuse downwards and enter the base layer through the collector protruding edge layer to form a good ohmic contact. The base metal contacts the collector protruding edge layer to form a Schottky contact, so as to consume the power of the collector protruding edge layer and prevent its surface current to avoid degradation of the transistor performance. 3. Protect the base layer with the protruding edge layer of the collector, prevent the P ⁺ GaAs material of the base layer outside the current aperture area from being exposed, avoid recombination of electrons on the surface of the base layer, and improve the performance of the transistor. It is also necessary for the N ^- InGaP material of the protruding edge layer of the collector to be ordered to prevent any electron injection, and entry from the base layer to the collector layer is prevented, and the InGaP and GaAs lattices are matched in order, or if ^{When the N-} InGaP material of the collector protruding edge layer is disordered, there is a spike in the conduction band transition from the P ^{+ GaAs material of the base layer to the N-} InGaP material of the collector protruding edge layer It can also prevent electron injection and avoid degradation of transistor performance. The electrons that are reorganized, trapped, and collected outside the current aperture are blocked between the surge and the ordered N ^- InGaP and P ⁺ GaAs. The electrons will not be collected to the collector metal. Therefore, the transistor can be prevented Performance drops. 4. The collector protruding edge layer is an etch stop layer, so the collector layer and the collector cap layer can be etched on the collector protruding edge layer. Therefore, the N ^- InGaP material of the collector protruding edge layer is opposite The N ^- GaAs material in the collector layer and the N ⁺ InGaAs material in the collector cap layer have high etching selectivity.

First, please refer to FIGS. 1-14. A heterojunction bi-carrier transistor 10 of the present invention includes: a substrate 11 having a first surface 111 and a second surface 112 on the opposite side. In this embodiment In an example, the material of the substrate 11 is semi-insulating GaAs, and the thickness of the substrate 11 refers to the Semiconductor Equipment and Materials International (SEMI) standard, and the unit is nm.

A sub-emitter layer 12 is located on the first surface 111 of the substrate 11. In this embodiment, the material of the sub-emitter layer 12 is N ⁺ GaAs, and the thickness of the sub-emitter layer 12 is 500~ 1000nm, dopant species (doping concentration) doped Si, and the Si concentration of 1e18 ~ 2e19cm ^-3, or the sub-emission layer 12 of a thickness of 800nm, dopant species and the doping concentration of Si is Si 4e18cm ^{- 3} , but not limited to this.

A composite emitter layer F is located on the sub-emitter layer 12, so that the sub-emitter layer 12 and the composite emitter layer F form an emitter layer E. In this embodiment, the composite emitter layer F It is composed of a first emitter layer 13 and a second emitter layer 14, and the second emitter layer 14 is located on the first emitter layer 13, and the material of the second emitter layer 14 is disordered N ^- InGaP, the In composition is 49% , and the thickness of the second emitter layer 14 is 30-60nm, the doping species is Si and the Si doping concentration is 5e16~5e17cm ^-3 or the second emitter The thickness of the layer 14 is 50 nm, the doping species is Si and the Si doping concentration is 3e17 cm ^-3 , but it is not limited to this.

A base layer 15 is located on the composite emitter layer F. In this embodiment, the material of the base layer 15 is P ⁺ GaAs, P ⁺ InGaAs or a combination thereof, and the thickness of the base layer 15 is 40~120nm, the doping species is C and the C doping concentration is 1e19~1e20cm ^-3 , or the thickness of the base layer 15 is 80nm, the doping species is C and the C doping concentration is 3e19cm ^-3 , but Not limited to this.

A collector ledge layer 16 is located on the base layer 15. In this embodiment, the material of the collector ledge layer 16 is N ^- InGaP, and the N ^- InGaP material is ordered The composition with the In is 49%, and the thickness of the collector protruding edge layer 16 is 0.4~100nm, the doping species is Si and the Si doping concentration is 5e16~5e17cm ^-3 , or the collector protruding edge layer 16 The thickness is 5 nm, the doping species is Si and the Si doping concentration is 3e17 cm ^-3 , but it is not limited to this.

A collector layer 17 is located on the collector protruding edge layer 16. In this embodiment, the material of the collector layer 17 is N ^- GaAs, and the collector layer 17 has an optimized base-collector capacitance, The functions of the base-collector breakdown voltage, Kirk effect and the robustness of the transistor, but not limited to this.

A collector cap layer 18 is located on the collector layer 17. In this embodiment, the material of the collector cap layer 18 is N ⁺ GaAs or N ⁺ InGaAs, the In composition is greater than or equal to 50%, and the The collector cap layer 18 has the function of forming a low-resistance contact with the collector metal, but it is not limited thereto.

As shown in FIG. 1, the substrate 11, the sub-emitter layer 12, the composite emitter layer F, the base layer 15, the collector protruding edge layer 16, the collector layer 17 and the collector cap layer 18 A semiconductor structure S is formed, and the surface of the semiconductor structure S is coated with a first SiN insulating layer D ₁ .

2, which etches the cap layer 18 and the collector electrode of the collector layer 17 into the first insulating layer SiN D _1, and stops at the edge of the projecting electrode collector layer 16, so that the capping layer 18 and the collector electrode The collector layer 17 forms a first plateau M ₁ .

As shown in FIG. 3, it etches the collector protruding edge layer 16, the base layer 15 down to the composite emitter layer F, so that the collector protrudes from the edge layer 16, the base layer 15 and the composite emitter Layer F forms a second high platform M ₂ , and the first high platform M _{1 is} smaller than the second high platform M ₂ .

As shown in FIG. 4, a lateral oxidation (Lateral Oxidation) region 19 is provided in the first region R _{1 of} the composite emitter layer F to form a current blocking region B, and the first region R _{1 of the composite emitter layer F} surrounding the composite electrode layer emitting second region R ₂ of F, so that the composite electrode layer emitting second region R ₂ of the F forming a current aperture L, therefore, with a high aluminum content comprising _{Al x Ga 1-x As (} 0.80 ≦x≦0.98) lateral oxidation (Lateral Oxidation) forms the current aperture L.

5, a second deposited SiN protective insulating layer D ₂ of the semiconductor structure S and the lateral oxidation zone 19, and the second insulating layer SiN D ₂ etching a first via T _1.

Shown in Figure 6, which is deposited a metal 101 to the emitter of the first via T _1, so that the metallic emitter 101 impinges on the sub-electrode layer 12, and the emitter made of a metal alloy material to 101 The sub-emitter layer 12 is made of N ⁺ GaAs material, forming a good ohmic contact.

As shown in FIG. 7, an isolation implantation region 104 implants ions into the second SiN insulating layer D ₂ and the sub-emitter layer 12. The isolation implant area 104 extends into the sub-emitter layer 12 to the substrate 11. The isolation implant area 104 prevents current flow between adjacent devices. In this embodiment, the isolation implant area The material of 104 is Boron, Argon, Hydrogen, Helium, Aluminum, or a combination thereof, but is not limited thereto.

As shown in FIG. 8, it etches a second via hole T _{2 in the second SiN insulating layer D 2} and deposits a base metal 102 into the second via hole T ₂ so that the base metal 102 is located in the On the collector protruding edge layer 16, and fabricating the base metal 102 as an alloy material that diffuses downward on the collector protruding edge layer 16 as N ^- InGap material enters the base layer 15 as P ⁺ GaAs material, forming a good Ohmic contact, the base metal 102 and the collector protruding edge layer 16 will form a Schottky contact, or the base metal 102 will etch through the collector protruding edge layer 16 to the base layer 15, and the base metal 102 deposits into the etching area and connects the base layer 15.

As shown in FIG. 9, it etches a third via hole T _{3 in the second SiN insulating layer D 2} and deposits a collector metal 103 into the third via hole T ₃ so that the collector metal 103 is located in A good ohmic contact is formed on the collector cap layer 18, and the material of the collector cap layer 18 is N ⁺ InGaAs. In addition, since the N ⁺ InGaAs material is highly doped, it can also be non-alloy contact, but it is not limited to this.

As shown in FIG. 9, after the steps of FIGS. 1-9, a heterojunction bi-carrier transistor 10 is also completed. As shown in FIG. 10, the electron flow e is from the emitter metal 101 to the collector metal 103 , And the current blocking area B blocks current and only allows current to pass through the current aperture L, but the steps are not limited to this.

As shown in FIG. 11A, the first emitter layer 13 includes a first transition layer 131, an intermediate layer 132, and a second transition layer 133, and the second transition layer 133 has the function of ballast resistance to improve electrical resistance. Crystal radio frequency and thermal stability, and the material of the first transition layer 131 is N ^- GaAs, the material of the second transition layer 133 is N ^- GaAs, and the material of the intermediate layer 132 is high content aluminum including Al _x Ga _{1- x} As, and the material of the lateral oxide region 19 provided on the intermediate layer 132 and the lateral oxide region 19 is N ^- AlGaAs, and the Al content x is 0.80~0.98. In this embodiment, the first transition layer 131 The thickness is 20~100nm, the doping species is Si and the Si doping concentration is reduced from 4e18 to 3e17cm ^-3 ; the thickness of the lateral oxide region 19 is 0.4~2.5nm, the doping species is Si and the Si doping concentration is 0~6e18cm ^-3 ; the thickness of the second transition layer 133 is 20-100nm, the doping species is Si and the Si doping concentration is 5e16~5e17cm ^-3 , or the thickness of the first transition layer 131 is 50nm, doped The impurity species is Si and the Si doping concentration is reduced from 4e18 to 3e17 cm ^-3 ; the thickness of the lateral oxide region 19 is 1 nm, the doping species is Si and the Si doping concentration is 4e18 cm ^-3 ; the second transition layer 133 The thickness is 50nm, the doping species is Si, and the Si doping concentration is 3e17cm ^-3 , but it is not limited to this.

In addition, a first selection layer 134 is provided between the first transition layer 131 and the intermediate layer 132, and a second selection layer 135 is provided between the intermediate layer 132 and the second transition layer 133. The layer selection provides a ^{smoother conduction band transition from the N-} GaAs transition layer to the high aluminum content intermediate layer. The material of the first selection layer 134 is N ^— AlGaAs, and the material of the second selection layer 135 is N ^— AlGaAs, but it is not limited thereto.

To further illustrate, the material of the intermediate layer 132 is high-content aluminum including AlGaAs, which is also highly resistive. Therefore, the intermediate layer 132 needs to be thin and electrons can tunnel. The second emitter layer 14 is used to inject electrons into the base layer 15 and form a heterogeneity between the base layer 15 and the second emitter layer 14, but it is not limited to this.

As shown in FIG. 11B, the collector layer 17 is composed of a first collector layer 171 and a second collector layer 172. The thickness of the first collector layer 171 is 300 to 1200 nm, and the doping species is Si and The Si doping concentration is 1e17~2e14cm ^-3 , the thickness of the second collector layer 172 is 0~800nm, the doping species is Si and the Si doping concentration is 1e16~1e17cm ^-3 ; the collector cap layer 18 The thickness is 20-100nm, the doping species is Si and the Si doping concentration is greater than 1e19cm ^-3 ; a collector transition layer 181, the collector transition layer 181 extends to the second collector layer 172, the collector transition layer The thickness of 181 is 20-100nm, the doping species is Si and the Si doping concentration is greater than 1e19cm ^-3 , or the collector layer 17 is composed of a first collector layer 171 and a second collector layer 172, the The thickness of the first collector layer 171 is 900 nm, the doping species is Si and the Si doping concentration is 2e15 cm ^-3 , the thickness of the second collector layer 172 is 300 nm, the doping species is Si and the Si doping concentration the collector cap layer 18 extending in a collector transition 181, the transition layer 181 extends to the collector electrode of the second collector layer 172, the collector 181 of the transition layer of a thickness of 50 nm, for the dopant species; 5e16cm ^-3 to The doping concentration of Si and the Si is greater than 1e19 cm ⁻³ , the material of the collector transition layer 181 is N ⁺ InGaAs, and the In composition is 0.50, but it is not limited thereto. The material of the collector cap layer 18 is N ⁺ InGaAs, the In composition is 0.50~0.65, the thickness of the collector cap layer 18 is 50 nm, the doping species is Si and the Si doping concentration is greater than 1e19 cm ⁻³ .

As shown in FIG. 12, in another embodiment, a back-side metal (Back-side Metal) 20 is located on the second surface 112 of the substrate 11, and a back-side metal is provided on the substrate 11 and the sub-emitter layer 12 The back-side vias 21 enable the back-side vias 21 to be electrically connected to the emitter metal 101 through the back-side vias 21. As shown in FIGS. 13-14, in another embodiment, a dielectric passivation layer P is coated on the heterojunction bi-carrier transistor 10, and a via hole T is provided in the dielectric passivation layer P , And deposit a bump metal (under bump metal) 30 on the via hole T, which is directly connected to the collector metal 103; thereby, the heat flow from the heterojunction bi-carrier transistor 10 passes through the bottom The bump metal 30 is conducted to a bump 40. In this embodiment, the bump 40 is deposited on the dielectric passivation layer P and the lower bump metal 30, and the bump 40 can be used as a thermal bump. In order to pull out the heat more effectively to improve performance and reliability, or the bumps 40 can be used as flip chip bumps to be assembled on the circuit board, or together with other modules on the circuit board in the module , Or stacked on top of another die. Therefore, the lower bump metal 30 can additionally be matched with flip chip bumps, solder bumps or thermal bumps, but it is not limited thereto.

In addition, at the junction of the base layer 15 and the second emitter layer 14, the N ^- InGaP material of the second emitter layer 14 is disordered or ordered and its band gap is 1.85 to 1.90 eV Between; at the junction of the base layer 15 and the collector protruding edge layer 16, and the N ^- InGaP material of the collector protruding edge layer 16 is ordered and its band gap is about 1.85eV, but not limited to this.

Based on this structure, the collector is located above the design, and because the base-collector area is small, the base-collector capacitance is reduced, and the oxide emitter reduces the electron injection current outside the aperture, thereby improving the performance of the transistor , It also reduces the base-emitter area and base-emitter capacitance, and the base is also protected in the lateral oxide region 19. The collector protruding edge layer 16 covers the base layer 15 to protect the exposed base layer 15 and avoid trapping and electronic recombination from the surface of the base layer 15, thereby improving reliability. The base metal 102 diffuses downward through the collector protruding edge layer 16 into contact with the base layer 15, therefore, the collector protruding edge layer 16 can protect the base layer 15. ^{The N-} InGaP material of the collector-protruding edge layer 16 needs to grow in order so that there is no discontinuity in the conduction band, and it can also prevent electrons from the base to the collector.

In summary, the technical means disclosed in the present invention do have the requirements of invention patents such as "novelty", "progressiveness" and "available for industrial use". I hope that the Jun Bureau will grant patents to encourage creation without any responsibility. Sense of virtue.

However, the drawings and descriptions disclosed above are only the preferred embodiments of the present invention. Anyone familiar with the art should make modifications or equivalent changes based on the spirit of the case and should still be included in the scope of the patent application in this case.

10: Heterojunction bi-carrier transistor 101: Emitter metal 102: Base metal 103: Collector metal 104: Isolated implant area 11: Substrate 111: First surface 112: Second surface 12: Sub-emitter layer 13: First emitter layer 131: First transition layer 132: Intermediate layer 133: Second transition layer 134: First selection layer 135: Second selection layer 14: Second emitter layer 15: Base layer 16: Set Extremely protruding edge layer 17: collector layer 171: first collector layer 172: second collector layer 18: collector cap layer 181: collector transition layer 19: lateral oxide region 20: back metal 21: back via 30 : under bump metal 40: bump D _1: a first insulating layer D _2: the second insulating layer P: dielectric passivation layer R _1: a first region R _2: the second region B: the current blocking region E: emitter Layer F: composite emitter layer M ₁ : first high stage M ₂ : second high stage L: current aperture T: via hole T ₁ : first via hole T ₂ : second via hole T ₃ : third via hole e: electron flow

FIG. 1 is a schematic diagram of protecting the surface of a semiconductor structure with a first SiN insulating layer according to the present invention. Figure 2 is a schematic diagram of the etching of the first plateau of the present invention. Fig. 3 is a schematic diagram of etching the second plateau of the present invention. Fig. 4 is a schematic diagram of the lateral oxidation zone produced by the present invention. FIG. 5 is a schematic diagram of the present invention for making a second SiN insulating layer to protect and etching the first via hole. Figure 6 is a schematic diagram of the present invention for producing emitter metal. Fig. 7 is a schematic diagram of the isolation implantation area made by the present invention. Fig. 8 is a schematic diagram of the production of base metal according to the present invention. FIG. 9 is a schematic diagram of the present invention producing a collector metal and completing a heterojunction bi-carrier transistor. Fig. 10 is a schematic diagram of the electron flow from the emitter metal to the collector metal of the present invention. FIG. 11A is a schematic diagram of the first transition layer to the second transition layer of the present invention. FIG. 11B is a schematic diagram of the first collector layer to the collector cap layer of the present invention. Fig. 12 is a schematic diagram of the backside metal and backside via holes of the present invention. 13 is a schematic diagram of the dielectric passivation layer of the present invention coated on the heterojunction bi-carrier transistor. 14 is a schematic diagram of the heat flow emitted by the heterojunction bi-carrier transistor of the present invention is conducted to the bump through the lower bump metal.

10: Heterojunction bi-carrier transistor

101: Emitter Metal

102: base metal

103: Collector Metal

104: Isolate the implantation area

11: substrate

111: first surface

112: second surface

12: Sub-emitter layer

13: The first emitter layer

14: Second emitter layer

15: Base layer

16: Set extremely protruding edge layer

17: Collector layer

18: Collector cap layer

19: Lateral oxidation zone

D ₂ : second insulating layer

R ₁ : The first region

R ₂ : second area

B: Current blocking area

F: Composite emitter layer

M ₁ : The first high platform

M ₂ : The second highest platform

L: current aperture

T ₁ : first via

T ₂ : second via

T ₃ : third via

Claims (20)

A kind of heterojunction bi-carrier transistor, including: A substrate having a first surface and a second surface on the opposite side; A sub-emitter layer located on the first surface of the substrate; A composite emitter layer located on the sub-emitter layer, so that the sub-emitter layer and the composite emitter layer form an emitter layer; A base layer is located on the composite emitter layer; One set of pole protruding edge layer, located on the base layer; A collector layer located on the protruding edge layer of the collector; and A lateral oxidation zone is provided in a part of the composite emitter layer to form a current blocking area, and the first region of the composite emitter layer surrounds the second region of the composite emitter layer, making the second region of the composite emitter layer The area forms a current aperture. The heterojunction bi-carrier transistor according to claim 1, wherein the composite emitter layer is composed of a first emitter layer and a second emitter layer, and the second emitter layer is located in the On the first emitter layer. The heterojunction bi-carrier transistor according to claim 2, wherein the first emitter layer includes a first transition layer, an intermediate layer and a second transition layer, and the material of the first transition layer is N ^- GaAs, the material of the second transition layer is N ^- GaAs and the material of the intermediate layer is high-content aluminum including Al _x Ga _1-x As (0.80≦x≦0.98), and the lateral oxide region is located in the middle The layer and the lateral oxide region are N ^- AlGaAs. The heterojunction bicarrier transistor according to claim 3, wherein a first selection layer is provided between the first transition layer and the intermediate layer, and a first selection layer is provided between the intermediate layer and the second transition layer Two selection layers, and the material of the first selection layer is N ^- AlGaAs, and the material of the second selection layer is N ^- AlGaAs. The heterojunction bi-carrier transistor according to claim 3, wherein the thickness of the first transition layer is 20-100 nm, the doping species is Si, and the Si doping concentration is reduced from 4e18 to 3e17cm ^-3 ; The thickness of the lateral oxide region is 0.4~2.5nm, the doping species is Si and the Si doping concentration is 0~6e18cm ^-3 ; the thickness of the second transition layer is 20~100nm, the doping species is Si and the Si doping The impurity concentration is 5e16~5e17cm ^-3 . The heterojunction bi-carrier transistor according to claim 3, wherein the thickness of the first transition layer is 50 nm, the doping species is Si, and the Si doping concentration is reduced from 4e18 to 3e17cm ^-3 ; the lateral oxidation The thickness of the zone is 1 nm, the doping species is Si and the Si doping concentration is 4e18 cm ^-3 ; the thickness of the second transition layer is 50 nm, the doping species is Si and the Si doping concentration is 3e17 cm ^-3 . The heterojunction bi-carrier transistor according to claim 1, wherein the N ^- InGaP material of the collector protruding edge layer is ordered and has a band gap of approximately 18.5 eV. The heterojunction bi-carrier transistor according to claim 1, further comprising a base metal, the base metal is located on the edge layer of the collector protrusion, and the base metal diffuses downward on the collector protrusion The edge layer enters the base layer. The heterojunction bi-carrier transistor according to claim 1, further comprising a base metal, the base metal is etched through the collector protruding edge layer to the base layer, and the base metal is deposited into the etching area And connect the base layer. The heterojunction bi-carrier transistor according to claim 1, wherein the material of the base layer is P ⁺ GaAs, P ⁺ InGaAs or a combination thereof. The heterojunction bi-carrier transistor described in claim 2 further includes a collector cap layer, and the collector cap layer is located on the collector layer. The requested item heterojunction bipolar transistor of the 11, wherein the material of the substrate of the GaAs semi-insulating; the sub-electrode layers emitting material is N ⁺ GaAs; emitter layer of the second material is a N ^- InGaP; the material of the base layer is P ⁺ GaAs; the material of the collector protruding edge layer is N ^- InGaP; the material of the collector layer is N ^- GaAs; the material of the collector cap layer is N ⁺ GaAs or N ⁺ InGaAs. The heterojunction bi-carrier transistor according to claim 12, wherein the thickness of the sub-emitter layer is 500-1000 nm, the doping species is Si and the Si doping concentration is 1e18-2e19cm ^-3 ; The thickness of the second emitter layer is 30~60nm, the doping species is Si and the Si doping concentration is 5e16~5e17cm ^-3 ; the thickness of the base layer is 40~120nm, the doping species is C and the C doping The concentration is 1e19~1e20cm ^-3 ; the thickness of the collector protruding edge layer is 0.4~100nm, the doping species is Si and the Si doping concentration is 5e16~5e17cm ^-3 ; the collector layer consists of a first collector layer And a second collector layer, the thickness of the first collector layer is 300~1200nm, the doping species is Si and the Si doping concentration is 1e17~2e14cm ^-3 , the thickness of the second collector layer is 0~800nm, the doping species is Si and the Si doping concentration is 1e16~1e17cm ^-3 ; a collector transition layer, the collector transition layer extends to the second collector layer, the thickness of the collector transition layer is 20~100nm, the doping species is Si and the Si doping concentration is greater than 1e19cm ^-3 , the collector cap layer extends to the collector transition layer, the collector cap layer has a thickness of 20-100 nm, and the doping species is Si And the Si doping concentration is greater than 1e19cm ^-3 . The heterojunction bi-carrier transistor according to claim 12, wherein the thickness of the sub-emitter layer is 800 nm, the doping species is Si and the Si doping concentration is 4e18 cm ^-3 ; the second emitter layer The thickness is 50nm, the doping species is Si and the Si doping concentration is 3e17cm ^-3 ; the thickness of the base layer is 80nm, the doping species is C and the C doping concentration is 3e19cm ^-3 ; the collector is prominent The thickness of the edge layer is 5nm, the doping species is Si and the Si doping concentration is 3e17cm ^-3 ; the collector layer is composed of a first collector layer and a second collector layer, the first collector layer The thickness is 900nm, the doping species is Si and the Si doping concentration is 2e15cm ^-3 , the thickness of the second collector layer is 300nm, the doping species is Si and the Si doping concentration is 5e16cm ^-3 ; one set The collector transition layer extends to the second collector layer, the collector transition layer has a thickness of 50 nm, the doping species is Si and the Si doping concentration is greater than 1e19 cm ^-3 , and the collector cap layer extends To the collector transition layer, the collector cap layer has a thickness of 50 nm, the doping species is Si, and the Si doping concentration is greater than 1e19 cm ⁻³ . The heterojunction bi-carrier transistor according to claim 12, wherein the N ^- InGaP material of the second emitter layer is disordered at the junction of the base layer and the second emitter layer Or order. The heterojunction bi-carrier transistor as described in claim 1 further includes an isolation implantation region, which is arranged between the sub-emitter layer and the substrate. The heterojunction bi-carrier transistor according to claim 16, wherein the material of the isolation implantation region is boron, argon, hydrogen, helium, and aluminum or a combination thereof. The heterojunction bi-carrier transistor according to claim 11, wherein the collector cap layer and the collector layer form a first plateau, and the collector protruding edge layer, the base layer and the composite emitter The pole layer forms a second plateau, and the first plateau is smaller than the second plateau; an emitter metal is located on the sub-emitter layer; a base metal is located on the collector protruding edge layer, and the The base metal diffuses down the collector protruding edge layer and enters the base layer; a collector metal is located on the collector cap layer; thereby, electrons flow from the emitter metal to the collector metal, and The current blocking area blocks current, and only allows current to pass through the current aperture. The heterojunction bi-carrier transistor described in claim 18 further includes a back metal located on the second surface of the substrate, and a back via hole is provided between the substrate and the sub-emitter layer, so that the The back metal can be electrically connected to the emitter metal through the back via hole. The heterojunction bicarrier transistor described in claim 18 further includes a bump metal directly connected to the collector metal; thereby, the heat flow from the heterojunction bicarrier transistor passes through the The lower bump metal is conducted to a bump.

Images