TW503499B - Chip screening method for reducing the defectiveness rate by dynamic voltage stressing - Google Patents

Abstract

The present invention discloses a chip screening method for reducing the defectiveness rate by dynamic voltage stressing, which comprises the steps of: first, measuring the stand-by current on two contact points of a testing chip to obtain a first current value Isb1; then using a predefined voltage value larger than the normal operating voltage of the testing chip to apply a dynamic voltage stressing on the testing chip; and finally re-measuring the stand-by current on the contact points to obtain a second current value Isb2. If the difference ΔIsb between the first current value Isb1 and the second current value Isb2 is larger than predefined standard current value, the testing chip is eliminated; otherwise, the testing chip is a qualified one. Accordingly, it is able to surely increase the yield rate of the chip without spending extra time.

Description

503499

V. Description of the invention (1) nam 1 c The present invention relates to a wafer sieve method for reducing the defective rate by dynamic high voltage processing (Dy-Yim Voltage Stressing, DVS), and particularly relates to the method after dynamic high voltage processing A crystal selection method that determines the yield of a wafer by using a difference in standby current (Stand-by current 'Isb). In the semiconductor process, as the size of the unpackaged chip (die, or grain) of the integrated circuit decreases, the small defects on the surface of the chip, such as tiny aftermath, molecular particles, or bridging patterns Defects, etc. 'become the decisive factors for wafer yield and stability. In order to maintain the yield and stability of wafer products, in addition to the improvement of the wafer process, wafer testing is the key to product quality. In the conventional wafer test process, for example, a dynamic random access memory (SRAM) test process, a test process generally used includes wafer pin test (Ch i p

Probing (CP) and Final Testing (FT) stages, and use the results of these tests to classify wafers (sorting). However, 'the test work in CP or FT is mainly for large or obvious wafer defects. For some small defects, such as when the oxidized metal particles are covered by a natural oxide layer, Its quality may be poor, but it can still pass the CP or FT test, and the problem only occurs after a long time operation of the chip shipment. In other words, the actual sales of chips through CP or test does not necessarily guarantee their yield, especially under long-term use. Therefore, with regard to the position of the manufacturer of the wafer, if the customer purchases such a wafer with minor defects, it may greatly reduce the impression of the wafer manufacturer and the intermediary wafer supplier.

0503-6225TWF * TSMC2000-0885 * Calvin.ptd Page 4 503499

And affect the goodwill of manufacturers and suppliers. In addition, because Cp * FT may not be able to test for micro wafer defects, test methods such as pre-heating life test (pre burn_in) or test during burn test (Test during burn_in (TDBI)) can be used. The wafer is baked at a temperature and tested for electrical properties to screen defective wafers. This method is often used by chip suppliers to ensure the yield of wafers sold. However, both the pre-heating life test and the TDB 丨 are extremely expensive ^ The test process' for example, it may take nearly 12 hours to perform a TDBI test to screen out defective ones, so as to improve wafer yield. Therefore, The test method must cost extra time and economic cost. In view of this, the present invention proposes a wafer screening method to reduce the defective rate by dynamic high voltage processing, which can indeed improve the yield of the wafer without the need to spend additional The cost of time. The principle of high-voltage processing is to apply a voltage value of 冋 greater than the normal operating voltage of the wafer to the wafer in a fixed pattern, such as 20 times, 40 times, or 60 times of reading and writing, # When the wafer has the aforementioned small defects: the defects will be more prominent, and the wafers at the two ends of the defect may change the electromechanical grip (I sb). Therefore, after applying dynamic high voltage processing to the wafer, measure the standby current Whether it is changed or not can determine whether the small defect on the wafer affects the yield of the wafer, so whether the wafer is eliminated can be determined by the amount of change in the standby current. One object of the invention to disclose a process to reduce the high voltage wafer dynamic screening methods do not yield, mainly applicable to ⑶ manufacturing process, can be used to screen

V. Description of the invention (3) ^ Chip treatment 4 which cannot be measured by CPWT test 4..., ^ Make small defects and eliminate defective wafers in advance to improve yield. Another object of the present invention is that after applying this selection method, it is no longer necessary to perform wafer-to-wafer test methods on the wafer, so that the DBi or pre-heating life can be reduced and extra time and Economic costs. The test time of the Japanese film does not need the dynamic high-voltage process drop method of the present invention, which includes the following steps: first, * test = the normal operating electric threshold value of the wafer screening square chip; and then the test crystal is greater than the test crystal in the test The contacts of the chip; finally, = the current of the dynamic high voltage processor is added to obtain a re-measured value of the contacts to be -φ magic ancient τ um, if the first current value is 1 ton, If the difference Δ Isb of S 2 is greater than a predetermined standard current value 1st, the test wafer is eliminated, otherwise the test wafer is a qualified wafer. The wafer screening method of the present invention can screen out wafers with small defects and two defect rates, so the defect rate of wafer shipment can be reduced. Similarly, using the wafer screening method of the present invention can replace the original ^^ or pre-heating life test, so time can be saved without extra time cost. * In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with reference to the drawings. Brief description of the drawings: FIG. 1 shows a dynamic high voltage process in one embodiment of the present invention.

Wafer Screening to Reduce Defective Rates Figures 2a and 2b are graphs of dynamic high test results that are not used in conventional techniques. Flowchart of the method; showing the heating life using the wafer screening method and voltage treatment of the wafer according to the embodiment. Detailed description of the embodiment: Please refer to FIG. 1 with Q 6 ^ y & The 18-m Japanese-Japanese film is taken as an example to illustrate the throbbing heart of the present invention: the process of a method for screening wafers that reduces the defective rate. … At f Shi: The test chip tested is dynamic random access memory with a size of 0 · 18 / z m. In the process of wafer pin test, firstly, the standby current of two contacts on a test wafer is measured with a probe to obtain a first current value I sh (step s 11). Then, a dynamic high voltage is applied to the test wafer at a voltage value 1.4 times the normal operating voltage Vcc of the test wafer (step S1 20). At this time, if the wafer is a possible defective wafer, that is, if there is a small defect on the wafer, the characteristics of the defect will be amplified after dynamic high voltage processing. After the dynamic high-voltage process, the standby current of the chip contacts is re-measured again to obtain a second current value I s 1½ (step S1 3 0), so that the standby current difference before and after the dynamic high-voltage process can be obtained. Alsb (step S140): △ Isb = Isb2 -Isbjl) Then, according to a predetermined standard current value I st, for example, 6uA in this embodiment, compare with △ I Sb to determine the quality of the wafer (step S150 ); If Δΐ3ΐ) > 6 μA, the test wafer is a bad wafer (step S1 60), otherwise the test wafer is a qualified wafer (step s170). After the screening of the present invention, the CP or FT of the wafer can be continued.

V. Description of the invention (5) Other test procedures. The test wafer used in the example of mM, W # is 0.18. This special specification '?' Method is only limited to wafers, for example, wafers can be manufactured from 0. μ ~. In other specifications or other types or below ...). In addition, Tailu · A " 1 system private or more advanced (such as 0.13 // m 1.4 times positive ^ in the application of dynamic high voltage processing, the use to use greater than normal / electricity is not determined by this multiple relationship; only

Lm samples can be processed for dynamic high voltage. In addition, the predetermined value of the standard current that is most good or bad for the broken chip! St, 6uA in this document, this value is the result of the 0μ test, which is acceptable for the film, 隹. 乂: The actual measurement of the same specification wafer

Because the wafers of different specifications or materials have different yield requirements, they are not limited by this example. The grids that are selected by dynamic high-voltage processing are not limited to this example: 山 彳 # : 7 It is known that wafers that have not been screened by dynamic high-voltage processing can reduce the failure rate by about 20% to 70%. The human cooker was selected by the applicant in order to prove that it was processed by dynamic high voltage. The yield rate is indeed better than that of conventionally selected wafers that have been ordered by a high-voltage processor without a dynamic state, so the following experiments were performed. See Fig. 2a and Fig. 2b, which show the results of two test results of two batches of wafers using the present invention, the wafer j-selector, and the conventional technology without the use of dynamic high voltage processing. . Picked in the genus

0503-6225TW; TSMC2000-0885; Calvin.ptd page 8 5. Description of the invention (6) U In the examples. .18 ... Used for heating: The processing voltage is h4 times the normal operating voltage, and the horizontal coordinate is the current 7-life test time, and the vertical coordinate is the failure rate (defective rate). After that, you can see that * after 48 hours of heating life test ^ C11 high voltage processing wafer failure rate is less than 24 hours. At the same time, the failure rate of the conventional wafers has slowed down after its lifetime, but it has continued to decrease. The failure rate of wafers processed by pressing is still determined by the results of the first graph. In a short time, it seems that the method I can see the difference. However, the same is true for the 48-hour heating life. U = significant difference; The failure rate does not decrease. It is recognized that the habitual failure rate is still decreased, and the decrease is: low electricity:. The use of the invention increases the failure rate after heating and asking the stomach. After the operation of the invention, it may be apparent that it is reduced by dynamic high voltage treatment. Bad ^. Therefore, the present invention reduces the yield rate while not using: 2: The selection method can be implemented. Although the present invention has disclosed the cost in a preferred embodiment. = Limit the present invention, anyone skilled in this art can use the spirit and scope, but can still make a little departure from the scope of the present invention as the scope of patents attached;

Claims (1)

'Including the following measured current values; 的 Wafer screening method to test the standby current of the two contacts on the wafer by dynamic high voltage processing to reduce the defect rate of the step to obtain a first driving energy A t of the normal operating voltage of the test wafer A predetermined lightning resistance is dynamically applied to the voltage of the test chip, and the current value of the test chip is re-measured to the standby current of the contacts. If the value of 待机 ^^^ is passed to a second current value, the voltage is eliminated. Test the wafer. The difference is greater than the predetermined current. The chip screening method described in item 1 of the patent application range, wherein the U test chip is a dynamic random access memory. ', S 3 · The wafer screening method described in item 1 of the patent application range, wherein the predetermined voltage value is κ 4 times the normal operating voltage of the test wafer 4 · The wafer as described in item 1 of the patent application range A screening method, wherein the predetermined voltage value is 1.6 times the normal operating voltage of the test wafer.