07096twf2.doc/006 修正日期92.12.17 玖、發明說明： 本發明係有關於一種動態流程半導體晶片的測試方 法，且特別是有關於一種將測試項目（test item )區分爲必 要測試項目（essential item )與選擇測試項目（〇Pti〇nal item )，並以必要測試項目的結果挑選選擇測試項目進行 測試的測試方式。 一般積體電路（integrated circuit )在製造完成之後’都 必須經過一連串的測試，以確保所生產晶片的品質，甚至 可藉由這些測試的結果修正積體電路（1C )的製程。然而， 測試的涵蓋範圍（test coverage )與測試所需要的時間（test time )通常爲挑選各種測試項目的基本考量。晶圓上的各 個晶片所需進行測試的項目不下百項，故在各項測試進行 時自然就會佔去很多的時間。但是，若基於上述測試時間 過於冗長的考量上，有時我們會將部分的測試項目省略以 節省測試的時間，如此常會造成測試的涵蓋範圍出現瑕 疵，進而造成產品品質下降的問題。 習知的測試方式通常是設計一系列的測試項目，之後 再將每一個晶片直接依照此系列中的每個測試項目一一進 行測試，但若生產製程控制得宜，晶片在某些測試項目上 幾乎不會不合格，則這些測試項目便形同虛設 (redundant )，使得測試時間拖的很長。 此外，基於上述測試時間的考量’習知的測試方式通 常會將這些形同虛設的測試項目由一系列的測試項目中移 除，以減少測試的時間。但是’當每次的製程狀況（process 1220545 07096twf2.doc/006 修正日期92.12.17 condition)有所差異時，則測試的涵蓋範圍就會出現瑕疵， 造成產品品質下降的問題。 因此，本發明的目的在提出一種動態流程半導體晶片 的測試方法，可使測試時間與測試涵蓋範圍的最佳化。 爲達本發明之上述目的，提出一種測試方式係將所有 的測試項目區分爲一組必要測試項目與多組選擇測試項 目，這組必要測試項目中的多個測試項目係針對每一晶片 進行測試，接著再視必要項目測試的結果決定是否進行或 挑選之後的多組選擇測試項目。因本發明對每個晶片進行 必要測試項目，之後再視其結果選擇性進行之後的測試， 故本發明不但可以節省測試的時間，更可以在測試階段 中，藉由必要測試項目所反應出每一晶片的差異，即時挑 選每一個晶片之後的選擇測試項目，達到測試涵蓋範圍的 最佳化。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 第1圖〜第3圖繪示爲依照本發明一較佳實施例之動 態流程半導體晶片的測試方法的流程示意圖。 圖式之標示說明： 102 :測試項目分類 104 :必要測試項測試 106 :選擇測試項測試 1220545 07096twf2.doc/006 修正日期92.12.17 A:必要測試項目 B、C、D :選擇測試項目 A卜A2、A3 :必要測試項 B卜B2、B3 :選擇測試項 α、C2、C3 :選擇測試項 Dl、D2、D3 ··選擇測試項 較佳實施例 首先請參照第1圖，其繪示爲依照本發明一較佳實施 例測試方法的流程示意圖。首先將測試項目區分類（步驟 102)例如分類爲一組必要測試項目Α與多組選擇測試項目 B、C、D...等，其中，該組必要測試項目A包括複數個必 要測試項Al、A2、A3…等，而選擇測試項目包括多個選 擇測試項 Bl、B2、B3、Cl、C2、C3、Dl、D2、D3 等 。 接著提供一待測物，此待測物例如爲晶片，以必要測試項 目A測試(步驟104)該待測物，而得到一測試結果。之後 再以此測試結果爲依據，選擇是否進行之後選擇測試項 B卜B2、B3、Cl、C2、C3、D卜D2、D3等的測試項（步 驟106)。其中，必要測試項目例如爲短路/開路測試、直 流電性測試、基本功能測試等項目，而選擇測試項例如爲 留存時間測試(Retention Time)、高電壓測試等項目。 接著請參照第2圖，其繪示爲依照本發明一較佳實施 例測試方法的流程示意圖。首先將測試項目區分類（步驟 102)，例如分類爲一組必要測試項目A與多組選擇測試組 B、C、D等，其中，該組必要測試項目A包括複數個必要 6 07096twf2.doc/006 修正日期92.12.17 測試項A1、A2、A3···等，而選擇測試組B、C、D則分別 包括多個選擇測試項B卜B2、B3、Cl、C2、C3、D卜D2、 D3等。接著提供一待測物，此待測物例如爲晶片，以必 要測試項目A測試(步驟104)該待測物，而得到一測試結 果。之後再以此測試結果爲依據，挑選之後選擇測試組B、 C、D中至少一組進行測試(步驟106)。其中，必要測試項 目例如爲短路/開路測試、直流電性測試、基本功能測試等 項目，而選擇測試項例如爲留存時間測試(Retention Time)、 高電壓測試、可靠度測試等項目。 最後請參照第3圖，其繪示爲依照本發明一較佳實施 例測試方法的流程不意圖。首先將測試項目區分類（步驟 102)，例如分類爲一組必要測試項目A與多組選擇測試項 目B、C、D...等，其中，該組必要測試項目A包括複數個 必要測試項Al、A2、A3…等，而選擇測試項目包括多個 選擇測試項 Bl、B2、B3、a、C2、C3、D卜 D2、D3 等。 接著提供一待測物，此待測物例如爲晶片，以必要測試項 目Α測試(步驟1〇4)該待測物，而得到一第一測試結果。 之後再以此測試結果爲依據’挑選選擇測試組B、C、D 中至少一組測試項目進行一次測試，得到一第二結果。接 著再以上述兩次的測試結果（第一結果、第一結果）爲依 據，挑選之後選擇測試項目中至少一組選擇沏1試項目再進 行進一步的測試。其中’必要測試項目例如爲短路/開路測 試、直流電性測試、基本功能測試等項目’而選擇測試項 例如爲留存時間測試(Retention Time)、高電壓測試、可靠 07096twf2.doc/006 修正日期92.12.17 度測試等項目。 上述中，若進行必要測試項目A後所得到的測試結果 達到一定標準，則可省略成選取較簡單之後續選擇性測試 項的測試，以節省測試的時間（第1圖）。反之，若必要 測試項目A後所得到的測試結果未達標準，並無法完全確 定是否合格，則再由多組選擇測試項中挑選至少一組適合 之測試項目進行一次或多次不同之測試，達到所進行的每 一項測試都有其必要性的優點（第2圖、第3圖）。 在本發明之較佳實施例中，如熟悉此技藝者可以輕易 知曉，晶片之基本功能測試包括啓始電壓測試、阻値測試、 漏電流測試與電容測試等，但不以此爲限。 綜上所述，本發明之測試方式至少具有下列優點： 1 ·本發明之測試方式對每個晶片進彳了必要測試項目， 之後再視其結果選擇性進行之後的測試，故本發明可以節 省測試所花費的時間，使測試時間最佳化。 2·本發明之測試方式可以在測試階段中，藉由必要測 試項目所反應出每一晶片的差異，以即時變更每一個晶片 之後的選擇測試項目，使測試涵蓋範圍最佳化。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。07096twf2.doc / 006 Revised date 92.12.17 发明, description of the invention: The present invention relates to a method for testing semiconductor wafers with dynamic processes, and in particular to a method for distinguishing test items into essential test items. ) And select a test item (〇Pti〇nal item), and based on the results of the necessary test items to choose the test method to select the test item for testing. Generally, after an integrated circuit is manufactured, it must go through a series of tests to ensure the quality of the produced wafer, and even the process of the integrated circuit (1C) can be modified by the results of these tests. However, the test coverage and test time are usually the basic considerations for selecting various test items. There are no less than 100 items to be tested on each wafer on the wafer, so it will take a lot of time for each test to be performed. However, if the above test time is too long to consider, sometimes we will omit some test items to save the test time. This will often cause defects in the test coverage, which in turn will cause product quality problems. The conventional test method is usually to design a series of test items, and then test each chip directly according to each test item in this series. However, if the production process is properly controlled, the chip will be almost on some test items. If the test fails, then these test items are redundant, which makes the test time very long. In addition, based on the above consideration of test time, the conventional test method usually removes these dummy test items from a series of test items to reduce the test time. However, when the process conditions (process 1220545 07096twf2.doc / 006 revision date 92.12.17 condition) are different each time, there will be defects in the coverage of the test, which will cause the problem of product quality degradation. Therefore, the object of the present invention is to propose a method for testing semiconductor wafers with dynamic processes, which can optimize the test time and test coverage. In order to achieve the above object of the present invention, a test method is proposed that divides all test items into a set of necessary test items and multiple sets of selected test items. Multiple test items in this set of necessary test items are tested for each chip. , And then, depending on the results of the necessary item tests, decide whether to conduct or select multiple groups of selected test items. Because the present invention performs the necessary test items for each wafer, and then selectively conducts subsequent tests depending on the results, the present invention can not only save the test time, but also can reflect each of the necessary test items in the test phase. The difference of one chip, the selection test items after selecting each chip in real time, to achieve the optimization of the test coverage. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Brief description of the drawings: FIG. 1 ~ FIG. 3 is a schematic flowchart of a method for testing a semiconductor wafer according to a dynamic process according to a preferred embodiment of the present invention. Description of the diagrams: 102: Test item classification 104: Necessary test item test 106: Select test item test 1220545 07096twf2.doc / 006 Revision date 92.12.17 A: Necessary test item B, C, D: Select test item A A2, A3: necessary test items B, B2, B3: selection of test items α, C2, C3: selection of test items D1, D2, D3 ·· Selection of test items Preferred embodiment First please refer to Fig. 1, which is shown as A schematic flowchart of a test method according to a preferred embodiment of the present invention. First, the test item area is classified (step 102), for example, into a set of necessary test items A and multiple sets of selected test items B, C, D, etc., where the set of necessary test items A includes a plurality of necessary test items Al , A2, A3, etc., and the selection test items include multiple selection test items Bl, B2, B3, Cl, C2, C3, Dl, D2, D3, and so on. Next, a test object is provided. The test object is, for example, a wafer. The test object is tested (step 104) with a necessary test item A to obtain a test result. Then, based on the test results, choose whether to select the test items B2, B2, B3, Cl, C2, C3, D2, D2, D3, and so on (step 106). Among them, the necessary test items are items such as short circuit / open circuit test, DC electrical test, basic function test, and the selected test items are items such as retention time test, high voltage test, and so on. Please refer to FIG. 2, which is a schematic flowchart of a test method according to a preferred embodiment of the present invention. First, the test project area is classified (step 102), for example, it is classified into a set of necessary test items A and a plurality of selected test groups B, C, and D. Among them, the set of necessary test items A includes a plurality of necessary 6 07096twf2.doc / 006 Date of revision 92.12.17 Test items A1, A2, A3, etc., while the selection test groups B, C, D include multiple selection test items B2, B3, Cl, C2, C3, D2 and D2 , D3, etc. Next, a test object is provided. The test object is, for example, a wafer. The test object is tested (step 104) with the necessary test item A to obtain a test result. Then based on this test result, at least one of test groups B, C, and D is selected for testing after selection (step 106). Among them, the necessary test items are items such as short circuit / open circuit test, DC electrical property test, basic function test, and the selected test items are items such as Retention Time test, high voltage test, and reliability test. Finally, please refer to FIG. 3, which shows the flow of the test method according to a preferred embodiment of the present invention is not intended. First, the test item area is classified (step 102), for example, it is classified into a group of necessary test items A and multiple groups of selected test items B, C, D, etc., where the group of necessary test items A includes a plurality of necessary test items Al, A2, A3, etc., and the selection test items include multiple selection test items Bl, B2, B3, a, C2, C3, D2, D2, D3, and so on. Next, a test object is provided. The test object is, for example, a wafer, and the test object is tested with the necessary test item A (step 104) to obtain a first test result. Then, based on the test results, at least one test item in the test groups B, C, and D is selected and tested once to obtain a second result. Then based on the above two test results (the first result, the first result), select at least one of the test items after selection, and then select a test item for further testing. Among them, 'necessary test items are, for example, short circuit / open circuit test, DC test, basic function test, etc.', and the test items are selected, for example, Retention Time test, high voltage test, reliable 07096twf2.doc / 006 amendment date 92.12. 17 degree test and other items. In the above, if the test result obtained after performing the necessary test item A reaches a certain standard, it can be omitted to select a simpler subsequent selective test item to save testing time (Figure 1). Conversely, if the test results obtained after the necessary test item A fails to meet the standard and cannot be completely determined as eligible, then at least one set of suitable test items is selected from multiple sets of selected test items for one or more different tests. Reaching every test performed has its own advantages (Figures 2 and 3). In the preferred embodiment of the present invention, if those skilled in the art can easily know, the basic function test of the chip includes the initial voltage test, the resistance test, the leakage current test and the capacitance test, but it is not limited thereto. In summary, the test method of the present invention has at least the following advantages: 1 · The test method of the present invention includes necessary test items for each wafer, and then conducts subsequent tests selectively depending on the results, so the present invention can save Time spent testing to optimize test time. 2. The test method of the present invention can optimize the test coverage during the test phase by reflecting the differences of each wafer reflected by the necessary test items in real time to select the test items after each wafer. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.