502392502392
【發明領域】 本發明係有關於一種焊接凸塊 造方法，特別是有關於一種可分別S(^er bumP )的製 其底部接合區域的大小之凸塊勢上制焊接凸塊之體積和 良率的焊接凸塊。 、王，以得到高度均勻及高 【習知技術】 當晶圓上的各種元件和内連線 & 層形成銲墊（bonding pad)及護；，凡/後，會於最上 以保護所形成之元件和内連線，並 行封裝製私’ 並使疋件透過内遠绫、锃 墊、以及銲墊上的銲接凸塊而與^ " 、 。 /、尾路板做適當的電性通路 在封裝製程μ，常見的方法是利用覆曰曰曰（fiip_ 術，於銲墊上形成焊接凸塊後，將焊接凸塊連 接到電路板上。而形成焊接凸塊的方法主要有三種：植球 技咖（solder ball mounting)、模板印刷（stencn pnrmng )和電鍍法（eiectropUting )，常用的方法為 電鍍法。以下將配合第^圖至第11?圖，詳細說明傳統使用 電鍍法來形成焊接凸塊的製程。 首先請參照第1 A圖，在已形成銲墊丨2及護層i 4的晶圓 10上，全面性濺鍍（sputter ) —層晶種層16。之後，如《 第1B圖所示，於晶種層16上形成一層厚度相當厚的乾膜式 光阻圖案層2 0 ’並於其中形成開口 1 8暴露出將欲形成之焊 接凸塊的接合區域，而其厚度係與將形成之焊接凸塊的高 度相關。接著於開口 18中的晶種層16上方電鍍（eieCtro-[Field of the Invention] The present invention relates to a method for manufacturing a solder bump, and more particularly, to a volume and a yield of a solder bump that can be fabricated on a bump potential of the size of the bottom joint area of S (^ er bumP), respectively. Solder bumps. , Wang, to obtain a high degree of uniformity and high [knowledge technology] When the various components on the wafer and the interconnect & layer to form a bonding pad (bonding pad) and protection; where / after, will be on top to protect the formation The components and interconnects are packaged in parallel, and the components are connected with the inner and outer pads, pads, and solder bumps on the solder pads and ^ ". /. The tail circuit board does the proper electrical path in the packaging process μ. The common method is to use the fiip technology to form solder bumps on the pads, and then connect the solder bumps to the circuit board. There are three main methods for welding bumps: solder ball mounting, stencn pnrmng, and eiectropUting. The commonly used methods are electroplating. The following will be matched with Figures ^ to 11? The process of forming solder bumps by traditional electroplating method will be described in detail. First, please refer to FIG. 1A, on the wafer 10 on which the pads 2 and the protective layer i 4 have been formed, a full-sputter (layer)-layer crystal Seed layer 16. Then, as shown in FIG. 1B, a relatively thick dry film photoresist pattern layer 20 'is formed on the seed layer 16 and an opening 18 is formed therein to expose the welding to be formed. The bonding area of the bumps, whose thickness is related to the height of the solder bumps to be formed. Next, plating is performed on the seed layer 16 in the opening 18 (eieCtro-
0503-6718TWF;TSMC2001 -0620;Amy.p t d0503-6718TWF; TSMC2001 -0620; Amy.p t d
502392 五、發明說明（2) " ---- plating) ~層凸塊底層金屬層（under bump i^tallupgy ; UBM ) 22和銲錫24。所形成的銲錫“係填滿 ^個，口18。之後，如第1D圖所示，移除光阻圖案層2〇， ，以鲜錫24為蝕刻罩幕，將晶種層16蝕刻變成如第π圖之 =，層1 6a。最後進行迴焊（ref low )製程，使銲錫24的 表面張力而變成球狀，而形成如第1 F圖所示之焊接 凸塊2 4 a。 凸塊的高度影響著後續之封裝步驟的成功與否。 日Η ^ Ϊ封裝尺寸趨小化，如果焊接凸塊的高度太小，在 的接合過程度中’晶片和電路板之間的間隙 ΐ ίΐ個。®導入密封樹脂（Under f 111 )，因而於其中產 此、岛二，π者，焊接凸塊的間距亦非常小，因此接合區不 犯^ ，否則在焊接凸塊熔融接合時，會發生短路。 程的可^庚右月b製備較高的焊接凸塊，則可以提高覆晶製 =以宰;塊之高度的方法，係藉由 利用電鍍再進行電鍍製程來達成，或者 _ ^成4光阻圖案層20上方延伸（如俨觫沾 蕈狀：錫2巧達成，如第2圖所示。Η如仏號26處）的 度之㊁：存ΐΐ:成簟狀銲錫24來增加焊接凸塊24a的高 塊24a得到較均勻二的缺古點。其缺點在於此方法無法使焊接凸· 份的光阻Η宏V*9n Γ度，而且由於簟狀銲錫24會覆蓋部 ::九阻圖案層20 (如標號 J剝除；再者，相鄰之簟狀銲錫24之：===2 : 的部份（標號26處），易發生样接之^在水千方向延伸 匆心生倚接，而不適用於細微間距502392 V. Description of the invention (2) " ---- plating) ~ under bump i ^ tallupgy (UBM) 22 and solder 24. The formed solder is filled with ^, mouth 18. Then, as shown in FIG. 1D, the photoresist pattern layer 20 is removed, and the fresh tin 24 is used as an etching mask, and the seed layer 16 is etched into Figure π =, layer 16a. Finally, a reflow (ref low) process is performed to make the surface tension of the solder 24 into a spherical shape to form a solder bump 2 4a as shown in Figure 1F. The height of the package affects the success of subsequent packaging steps. Η ^ Ϊ Package size tends to become smaller. If the height of the solder bump is too small, the gap between the chip and the circuit board during the bonding process . ® introduces sealing resin (Under f 111), so if it is produced in this, island two, π, the distance between the welding bumps is also very small, so the joint area does not make ^, otherwise a short circuit will occur when the welding bumps are fusion-bonded The process can be used to prepare higher solder bumps, which can improve the flip-chip manufacturing method. The method of block height can be achieved by using electroplating and then the plating process, or _ ^ 4 Extends above the photoresist pattern layer 20 (Such as at No. 26): Degree of deposit: Depositing solder 24 to increase the height of the bump 24a of the solder bump 24a results in a more uniform defect. The disadvantage is that this method cannot make the solder bump. Part of the photoresist macro V * 9n Γ degree, and because the 簟 -shaped solder 24 will cover the part :: Nine resist pattern layer 20 (such as the number J is stripped; Moreover, the adjacent 簟 -shaped solder 24: === 2: The part (marked at 26), which is prone to splicing ^ Extends in a hurry direction, and is not suitable for fine spacing
502392 --- 五、發明說明（3) 之銲接凸塊製程。 若是藉由加厚光阻圖案声 米左右）來增加焊接凸塊的言片予又（约70微米至120微 此困難點在於不易得到厚戶沾亦會遭遇到一些困難， 而且對此光阻進行曝光時Γ合右，f態光阻或乾膜光阻， 響到圖案的解析度。 9 嚴重的光散射效應，而影 【發明之目的及概要】 有鑑於此，本發明之一目 缺點之焊接凸塊製程。 出一種可以避免上述 本發明之另一目的為提 的體積和其底部接合區域的大小焊㈣ 均勻的焊接凸塊。 鬼製私’以得到高度 為達成上述目的，本發明提出 法’其步驟如下所述。於已形成銲墊的造方 和護層上形成-層晶種層。接著，於=上；；π墊 層，並進行兩階段的曝光顯影程序。第一 2成負光阻 程序係使光阻層形成具有第一開一丄c影 位於第-開口中之未曝光光阻層。第=幕層以及 序係使未曝光光阻層圖案化出第二開口，二形二光顯影程 和第二開口之第二光阻罩幕層，1第一光阻罩孀 光阻罩幕層之一部份。繼續於第一和第二開口 1 “、、-物後，移除光阻罩幕層，以暴露出晶種層，並f合 案化。最後進行迴焊製程，使接合物轉為焊接凸=種曰圖 0503·6718TWF;TSMC2001 -0620;Amy.ptd 第7頁 五、發明說明（4) 本發明並提供一種焊接凸塊的製 ^:於已形成銲塾的晶圓上覆蓋驟如下 和ί:ΐ銲墊表面。接著於護層和銲墊上依序形成f層大 1之後’將第一光罩的圖案轉移至光阻i:種層 間後’以形成具有第-開口的第經 圖案轉移至未曝光光阻層中，以笛=第一光罩的 之第二光阻罩幕層，且第二^ ^和第二開口 阻罩幕層。接著，於第一和第二述之第一光 金屬層和接合物，且接人汗^電鍍凸塊底异 後，移除光阻罩幕層異第一和第二開口中= 仃^製权，使接合物轉為焊接 之後，進 為讓本發明之上逃 下文特舉-較佳實施例，计、特徵及優點能更明顯易懂 下·· 並配合所附圖式，作詳細說=如 【圖式簡單說明】 第1A圖至第1F圖係絡+德 意圖。 1不傳統之焊接凸塊製程的流程示 第2圖係繪示傳統用氺 *、 面圖。 朿製造焊接凸塊之孽狀銲錫的剖 第3A圖至第3G圖係絡一 Λ 種焊接凸塊製程的流程示：】據本發明-較佳實施例之— 【符號說明】 & ° ° 1 〇、1 0 0〜晶圓；502392 --- 5. The solder bump process of the invention description (3). If the thickness of the photoresist pattern is thickened to increase the thickness of the solder bumps (approximately 70 microns to 120 microns), the difficulty is that it is not easy to get thick households, and some difficulties are encountered, and the photoresist When exposure is performed, the F-state photoresist or dry film photoresist affects the resolution of the pattern. 9 Serious light scattering effects, and the purpose and summary of the invention In view of this, one of the shortcomings of the present invention is disadvantageous. Welding bump manufacturing process. A welding bump that can avoid the above-mentioned another purpose of the present invention is to increase the volume and the size of the joint area at the bottom of the welding joint. Uniform welding bumps. The method's steps are as follows. A-layer seed layer is formed on the substrate and the protective layer on which the pad has been formed. Then, on the top layer; the π pad layer, and a two-stage exposure and development process is performed. The first 2 The process of forming a negative photoresist causes the photoresist layer to form an unexposed photoresist layer having a first opening and a shadow in the first opening. The third = curtain layer and the sequence system pattern the unexposed photoresist layer into the second opening. , Two-shaped two-light development process and the second opening The second photoresist mask layer, 1 part of the first photoresist mask 孀 photoresist mask layer. Continue to the first and second openings 1 ",,-, remove the photoresist mask layer In order to expose the seed layer and combine it with f. Finally, a reflow process is performed to turn the joint into a solder bump = species picture 0503 · 6718TWF; TSMC2001 -0620; Amy.ptd Page 7 V. Description of the invention ( 4) The present invention also provides a method for manufacturing a solder bump: covering the wafer on which a solder pad has been formed as follows: ΐ the surface of the pad. Then, the f-layer is formed on the protective layer and the pad in order. The pattern of the first photomask is transferred to the photoresist i: after the seed layer to form a second pattern with a first opening and transferred to the unexposed photoresist layer. The curtain layer, and the second ^^ and the second opening block the curtain layer. Then, after the first photometal layer and the joint described in the first and the second, which are exposed to sweat ^ plating bumps, remove The first and second openings of the photoresist mask are different from each other in the first and second openings. After the joint is converted to welding, the following aspects of the present invention are escaped.-Preferred embodiments, measures, features And the advantages can be more obvious and easy to understand ... And in accordance with the attached drawings, make a detailed description = as [Simplified description of the drawings] Figure 1A to 1F Figures + German intention. 1 Unconventional welding bump process Flow chart No. 2 is a diagram showing traditional 氺 * and 图. 的 Cross-sections of manufacturing sinusoidal solders for manufacturing solder bumps. Figures 3A to 3G show a sequence of Λ solder bump manufacturing processes:] According to this Invention-the preferred embodiment-[Symbol Description] & ° ° 1 0, 1 0 0 ~ wafer;
I 0503-6718TWF;TSMC2001-0620;Amy.ptd 502392 五、發明說明（5) 1 2、1 02〜銲墊， 14、104〜護層； 16 '16a 、1〇6 、l〇6a〜晶種声. 1 8、11 8 a、11 8 b 〜開口； 曰， 20〜光阻圖案層； 120、120’〜光阻罩幕層，· 120a〜未曝光光阻層； 22、122〜凸塊底層金屬層· 24〜銲錫（或簟狀銲錫），· 26〜蕈狀銲錫之水平延伸處· 24a、124a〜焊接凸塊； 1 2 4〜接合物。 【實施例】 第3A圖至第3G圖係繪示根據本發 種可分別控制焊接凸塊的高度和農 f 一較佳實施例之一 示意圖。 八关3區的大小之製程的 :先請參照第3A圖，在已形成銲墊1〇2的晶圓ι〇〇上， 覆蓋一層護層1 〇4，此護層1 04的材質例如為聚亞醯胺 (polyimide)、或電漿增強型化學氣相沈積法所製成的 氮化石夕（簡稱PE nitride)，此護層104大致暴露出鲜塾< 102的表面。之後，於銲墊1〇2和護層1〇4上形成一層晶種 層1 0 6，其形成方法例如為濺鍍法。 曰阳 接著請參照第3B圖，於晶種層1 0 6上形成一層負光阻 層，例如是乾膜式光阻層，並利用第一光罩1 40進行第一 第9頁 0503-6718TWF;TSMC2001-0620;Amy.ptd 502392 五、發明說明（6) 52二光顯景》程序’使曝光處的光阻層硬化成具有開σ 口二、光阻罩幕層丨2〇，而未曝光的光阻層經控制顯影的 私又而於開口 1 18a中形成未曝光光阻層i2〇a。在控 ’可藉由控制顯影的時間來控制光阻罩幕層 120的表。面$和未曝光光阻層120a的表面之高度差距h。 接著請參照第3C圖，利用第二光罩丨42進行第二階段 的曝光顯影程序’使未曝光光阻層120a圖案化出開口118b 。經第一階段和第二階段曝光顯影程序後，形成光阻罩幕 曰 且/、有上方開口 118a和下方開口 118b，上方開口 118a的^寸較下方開口1181)的尺寸大。上方開口n8a的尺 寸控制著將形成之焊接凸塊的體積，而下方開口丨丨8b的 寸則控制著其底部接合區域的大小。 因此右製程上需要製造兩度較高的焊接凸塊，可以 在不牦加光阻層厚度的情況下，藉由增加上方開口 1 1 8 &的 尺寸來達成，因此擴大了固定厚度之乾膜式光阻層的應用 性。 〜 接著請參照第3 D圖，利用電鍍法於光阻罩幕層丨2 〇，中 之開口118a和118b中填入接合物丨24，其材質例如曰為錫鉛 (SnPb)、無錯接合物（lead free s〇lder)或其他種類 的接合物。在填入接合物124之前，更包括於其中電鏡一 _ 層凸塊底層金屬層122，例如為Ni/Cu或其他可幫助電1鍍f 程之進行的材質。 X、 接著請參照第3E圖，移除光阻罩幕層uo，，以暴露出 其下方的晶種層1 0 6的表面。 + $I 0503-6718TWF; TSMC2001-0620; Amy.ptd 502392 V. Description of the invention (5) 1 2, 1 02 ~ pads, 14, 104 ~ sheath; 16 '16a, 106, 106a ~ seed Acoustic. 1 8, 11 8 a, 11 8 b ~ opening; 20 ~ photoresist pattern layer; 120, 120 '~ photoresist cover curtain layer, · 120a ~ unexposed photoresist layer; 22, 122 ~ bump Bottom metal layer 24 ~ solder (or 簟 -shaped solder), 26 ~ horizontal extension of mushroom-shaped solder 24a, 124a ~ soldering bump; 1 2 4 ~ joint. [Embodiment] FIGS. 3A to 3G are schematic diagrams showing a preferred embodiment in which the height of the solder bump and the agricultural f can be controlled separately according to the present invention. The process of the size 3 of the eight gates: Please refer to FIG. 3A first. On the wafer ιoo where the pads 102 have been formed, cover a protective layer 104. The material of this protective layer 104 is, for example, Polyimide, or plasma-enhanced chemical vapor deposition (PE nitride) nitride nitride (PE nitride), the protective layer 104 substantially exposes the surface of the fresh 塾 < 102. After that, a seed layer 106 is formed on the pads 102 and the protective layer 104, and the formation method is, for example, a sputtering method. Yue Yang, please refer to FIG. 3B, and form a negative photoresist layer on the seed layer 106, such as a dry film photoresist layer, and use the first photomask 1 40 to perform the first page 0503-6718TWF ; TSMC2001-0620; Amy.ptd 502392 V. Description of the invention (6) 52 Two-light scene "program" to harden the photoresist layer at the exposure to have a σ opening II, the photoresist mask curtain layer 丨 2, but not The exposed photoresist layer is controlled to develop an unexposed photoresist layer i20a in the opening 118a. The surface of the photoresist mask layer 120 can be controlled by controlling the development time. The height difference h between the surface $ and the surface of the unexposed photoresist layer 120a. Next, referring to FIG. 3C, the second photomask 42 is used to perform the second-stage exposure and development process' to pattern the unexposed photoresist layer 120a out of the opening 118b. After the first-stage and second-stage exposure and development procedures, a photoresist mask is formed. The upper opening 118a and the lower opening 118b are formed. The size of the upper opening 118a is larger than that of the lower opening 1181). The size of the upper opening n8a controls the volume of the solder bump to be formed, while the size of the lower opening 丨 8b controls the size of the bottom joint area. Therefore, the right process needs to produce two-degree higher solder bumps, which can be achieved by increasing the size of the upper opening 1 1 8 & without increasing the thickness of the photoresist layer, thus increasing the dryness of the fixed thickness. Applicability of film photoresist layer. ~ Next, please refer to Fig. 3D, fill the photoresist mask curtain layer with electroplating method 丨 2 〇, fill in the opening 118a and 118b in the joint 丨 24, the material is, for example, tin-lead (SnPb), error-free joint (Lead free solder) or other kinds of conjugates. Prior to filling the bonding material 124, it further includes a bump metal layer 122 in the electron microscope, such as Ni / Cu or other materials that can help the electroplating process. X. Next, referring to FIG. 3E, remove the photoresist mask curtain layer uo to expose the surface of the seed layer 106 below it. + $
0503-6718TWF;TSMC2001-0620;Amy.ptd 第10頁 502392 五 發明說明（7) 接著請參照第3F圖，將多餘之晶種 合物124之間成電性斷路，其移除方法胃06移除，使接 以移除未被接合物124覆蓋的晶種芦1〇 "為濕式蝕刻法， 之晶種層l〇6a。 曰 ’而成為如圖所示 接著請參照第3G圖，進行迴焊制 外形因表面張力而變成球狀，轉心:/吏接合物124的 124a。 捋為如圖所示之焊接凸塊 第3 D圖至第3 G圖中所示之虛線係彳々本 成的接合物及焊接凸塊。在本發明中Ί ί統之製程所形 高度因接合物124的體積增加而得以辦、β接凸塊124a的 善控制上方開口 118a的尺寸及深度/即加可7此/只要妥| 域大小下控制焊接凸塊124&的高度。 不衫響接合區 【發明之特徵與效果】 綜上所述，本發明至少具有下列優點和特徵： 可分1別i:明ί焊接凸塊的體積和其底部接合區域的大小 j刀別控制，因此增加製程的可變性。 2·本發明利用兩階段的曝光顯影製 層中上方開口和下方開口的大小 =:先=罩幕 顯影時間長短來控制上方開口的深声由$制第-階段之 掄沾古危i 開的冰度，以分別控制焊拯Λ 、同又和接合區域，故此光阻圖案層 在可得到較佳解析度的範圍。军心度可以被控制彳 求段之曝光顯影步驟’以根據實際的要 辰備出不同兩度的焊接凸塊。 4·本發明之焊接凸塊的製程可適用於微細間距焊接凸 0503-6718TW;TSMC20〇i.〇62〇;Am, 丨y.ptd 第11頁 502392 五、發明說明（8) 塊之製備。 5.利用本發明所提供的方法，可以得到高度更高的焊 接凸塊。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限制本發明，任何熟習此項技藝者，在不脫離本發明之精 神和範圍内，當可做更動與潤飾，因此本發明之保護範圍 當事後附之申請專利範圍所界定者為準。0503-6718TWF; TSMC2001-0620; Amy.ptd Page 10 502392 Fifth invention description (7) Next, please refer to Figure 3F to electrically break the excess seed compound 124, and the removal method is stomach 06. In order to remove the seed crystal 10 which is not covered by the joint 124, the seed layer 106a is a wet etching method. It will become as shown in the figure, and then refer to Figure 3G for re-soldering. The shape becomes spherical due to surface tension.捋 is the solder bump as shown in Figures 3D to 3G. The dashed lines shown in Figure 3D are the joints and solder bumps. In the present invention, the height of the conventional manufacturing process can be achieved due to the increase in the volume of the joint 124, and the size and depth of the upper opening 118a of the β-bump 124a can be controlled. The lower controls the height of the solder bump 124 &. Non-scratch joint area [Features and effects of the invention] In summary, the present invention has at least the following advantages and characteristics: It can be divided into two categories: the volume of the welding bump and the size of the joint area at the bottom. , Therefore increasing process variability. 2. The present invention utilizes the size of the upper and lower openings in the two-stage exposure and development layer =: first = the length of the mask development time to control the deep sound of the upper opening. The degree of ice is used to control the welding life, the same, and the bonding area, respectively. Therefore, the photoresist pattern layer is in a range where a better resolution can be obtained. The military degree can be controlled. The exposure and development step of the seeking section 'can be used to prepare welding bumps of two different degrees according to actual conditions. 4. The welding bump manufacturing process of the present invention can be applied to fine-pitch welding bumps. 0503-6718TW; TSMC20i.〇62〇; Am, 丨 y.ptd Page 11 502392 5. Description of the invention (8) Block preparation. 5. By using the method provided by the present invention, a solder bump having a higher height can be obtained. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouches without departing from the spirit and scope of the present invention. The scope of protection shall be defined by the scope of the patent application.
0503-6718TWF;TSMC2001 -0620;Amy.p t d 第12頁0503-6718TWF; TSMC2001 -0620; Amy.p t d p. 12