CN112291940A - Circuit board structure and manufacturing method thereof - Google Patents
Circuit board structure and manufacturing method thereof Download PDFInfo
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- CN112291940A CN112291940A CN201910672259.3A CN201910672259A CN112291940A CN 112291940 A CN112291940 A CN 112291940A CN 201910672259 A CN201910672259 A CN 201910672259A CN 112291940 A CN112291940 A CN 112291940A
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- layer
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- opening
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The invention discloses a circuit board structure and a manufacturing method thereof. The manufacturing method of the circuit board structure comprises the steps of forming a sacrificial layer on a substrate; forming a metal layer on the side wall and the top surface of the sacrificial layer; forming a patterned photoresist layer with a second opening above the sacrificial layer, wherein the second opening is communicated with the first opening and exposes a part of the metal layer; forming a first circuit layer to fill in the second opening and the first opening and cover a part of the metal layer; forming a first dielectric layer on the sacrificial layer and covering the metal layer, wherein the first dielectric layer is provided with a third opening to expose the first circuit layer; forming a second circuit layer filled in the third opening and covering a part of the first dielectric layer; removing the substrate, thereby exposing the sacrificial layer, a portion of the metal layer and a portion of the first circuit layer; and removing the sacrificial layer and the metal layer. The method can improve the area utilization rate of the circuit board.
Description
Technical Field
The present invention relates to a circuit board structure and a method for fabricating the same, and more particularly, to a method for fabricating a circuit board structure without an additional step of forming a conductive bump.
Background
A conventional method for manufacturing a circuit board includes forming conductive bumps on a die side of the circuit board, which includes providing a mask having openings, forming a material of the conductive bumps in the openings of the mask, and removing the mask to obtain the conductive bumps. However, the conductive bump formed by the above method is prone to have a ring (annular ring) at the periphery, thereby reducing the area utilization rate of the chip connection side of the circuit board. In addition, since the conductive bump and the circuit layer directly contacting the conductive bump are formed in different manufacturing processes in the conventional manufacturing method, a cross section exists between the conductive bump and the circuit layer directly contacting the conductive bump. Therefore, a new method for manufacturing a circuit board is needed to solve the above problems.
Disclosure of Invention
In one aspect, a method of fabricating a circuit board structure is provided. The method comprises the following steps: forming a sacrificial layer on the substrate, wherein the sacrificial layer has a first opening exposing a portion of the substrate; forming a metal layer on the side wall and the top surface of the sacrificial layer; forming a patterned photoresist layer over the sacrificial layer, wherein the patterned photoresist layer has a second opening, the second opening is communicated with the first opening and exposes a portion of the metal layer; forming a first circuit layer to fill in the second opening and the first opening and cover a part of the metal layer; forming a first dielectric layer on the sacrificial layer and covering the metal layer, wherein the first dielectric layer is provided with a third opening to expose the first circuit layer; forming a second circuit layer filled in the third opening and covering a part of the first dielectric layer; removing the substrate, thereby exposing the sacrificial layer, a portion of the metal layer and a portion of the first circuit layer; and removing the sacrificial layer and the metal layer.
In an embodiment of the present invention, the first circuit layer has a first portion and a second portion. The first portion is located in the first opening and the second portion is located in the second opening. The first portion and the second portion are integrally formed.
In one embodiment of the present invention, the step of forming the metal layer on the sacrificial layer comprises conformally forming the metal layer on the sacrificial layer.
In one embodiment of the present invention, the step of forming the patterned photoresist layer over the sacrificial layer comprises: forming a photoresist layer over the sacrificial layer; exposing the photoresist layer by using a first exposure source, wherein the first exposure source and the sacrificial layer are arranged on two opposite sides of the substrate; exposing the photoresist layer by using a second exposure source, wherein the second exposure source is arranged on one side of the sacrificial layer on the substrate; and developing to form a patterned photoresist layer.
In one embodiment of the present invention, the photoresist layer comprises a positive photoresist material.
In one embodiment of the present invention, the substrate is made of a light-permeable material.
In an embodiment of the present invention, after the step of forming the second circuit layer and before the step of removing the substrate, the method further includes: forming a second dielectric layer on the first dielectric layer and covering the first dielectric layer and the second circuit layer, wherein the second dielectric layer has a fourth opening therein to expose the second circuit layer; and forming a third circuit layer filled in the fourth opening and covering a part of the second dielectric layer.
In an embodiment of the present invention, after the step of forming the second circuit layer and before the step of removing the substrate, the method further includes forming a solder mask layer on the first dielectric layer.
Another aspect of the present invention is to provide a circuit board structure. The circuit board structure comprises at least one dielectric layer, a first circuit layer and a second circuit layer. The first circuit layer has a first portion and a second portion. The first portion protrudes from a top surface of the dielectric layer. The second part is embedded in the dielectric layer and exposed out of the top surface. The first portion and the second portion are integrally formed. There is no cross-section between the first portion and the second portion. The second circuit layer is disposed above the dielectric layer and electrically connected to the first circuit layer.
In an embodiment of the invention, the at least one dielectric layer is a plurality of dielectric layers.
Drawings
In order to make the aforementioned and other objects, features, advantages and embodiments of the invention more comprehensible, the following description is given:
fig. 1 is a flow chart illustrating a method for manufacturing a circuit board structure according to an embodiment of the invention.
Fig. 2 to 17 are schematic cross-sectional views illustrating stages of manufacturing processes in the manufacturing method according to the embodiment of the invention.
Fig. 18 shows a bottom view of region R1 in fig. 17.
Fig. 19 is a perspective view of the first circuit layer 150 located in the region R1 in fig. 18.
[ description of main element symbols ]
100: circuit board structure 110: substrate
120: sacrificial material layer 122 a: first opening
122 b: side wall 122 c: top surface
122: sacrificial layer 130: metal layer
130 a: exposed portion 140: the photoresist layer
140 a: first exposure region 140 b: first unexposed region
142 a: second exposure region 144: patterning photoresist layer
144 a: second opening LS 1: first exposure source
LS 2: second exposure source D1: a first direction
D2: a second direction MS: second mask
150: first wiring layer 160(150 a): conductive bump (first part)
150 b: second portion 220: second precursor dielectric layer
222: first dielectric layer 222 a: third opening
222 b: top surface 250: second circuit layer
322: second dielectric layer 322 a: the fourth opening
350: third circuit layer 400: solder mask
R1: region(s)
Detailed Description
In order to make the disclosure more complete and complete, the following description is provided for illustrative purposes of implementing aspects and embodiments of the invention; it is not intended to be the only form in which the embodiments of the invention may be practiced or utilized. The various embodiments disclosed below may be combined with or substituted for one another where appropriate, and additional embodiments may be added to one embodiment without further recitation or description.
In the following description, numerous specific details are set forth to provide a thorough understanding of the following embodiments. However, embodiments of the invention may be practiced without these specific details. In other instances, well-known structures and devices are shown schematically in order to simplify the drawing.
In addition, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Furthermore, in the description that follows, one feature may be formed on, connected to, and/or coupled to another feature, including embodiments in which the features are in direct contact, and embodiments in which another feature may be formed and interposed between the features, such that the features may not be in direct contact.
Furthermore, spatially relative terms, such as "upper," "lower," "above," "below," and the like, may be used herein to describe one element or feature's relationship to another element or feature in the drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. Devices may also be translated in other orientations (rotated 90 degrees or other orientations) and thus the spatially relative descriptors used herein should be interpreted similarly.
In one aspect, a method of fabricating a circuit board structure is provided. The method can avoid the occurrence of annular rings (annular rings) at the periphery of the conductive bumps on the chip connecting side (die side) of the circuit board structure, thereby improving the area utilization rate of the chip connecting side of the circuit board. In addition, the conductive bump obtained by the method is integrally formed with the circuit layer directly contacted with the conductive bump, and a section does not exist between the conductive bump and the circuit layer. Fig. 1 is a flow chart illustrating a method for manufacturing a circuit board structure according to an embodiment of the invention. Fig. 2 to 17 are schematic cross-sectional views illustrating stages of manufacturing processes in the manufacturing method according to the embodiment of the invention. As shown in fig. 1, the method 10 includes steps S10 through S80.
In step S10, a sacrificial layer is formed on the substrate. Fig. 2 to 3 are detailed flows of implementing step S10 according to an embodiment of the invention. First, referring to fig. 2, a sacrificial material layer 120 is formed on a substrate 110. In one embodiment, the substrate is made of a light transmissive material, such as glass or other suitable material. In one embodiment, the material of the sacrificial material layer 120 includes, but is not limited to, phenolic resin, epoxy resin, polyimide resin, or polytetrafluoroethylene. In one embodiment, the method of forming the sacrificial material layer 120 may be, for example, lamination, coating, or other suitable manufacturing process. Next, referring to fig. 3, a plurality of first openings 122a are formed in the sacrificial material layer 120, thereby obtaining a sacrificial layer 122. In some embodiments, the method of forming the first opening 122a includes, but is not limited to, using laser ablation (laser ablation) or a conventional photolithography etching process. The first opening 122a exposes a portion of the substrate 110. Sacrificial layer 122 has sidewalls 122b and a top surface 122 c.
In step S20, a metal layer is formed on the sidewalls and the top surface of the sacrificial layer. Referring to fig. 4, in some embodiments, a metal layer 130 is conformally formed on sidewalls 122b and top surface 122c of sacrificial layer 122. In some embodiments, the material of the metal layer 130 includes, but is not limited to, copper, and the metal layer 130 is formed by a method including, but not limited to, an electroless copper (electroless copper) manufacturing process.
In step S30, a patterned photoresist layer is formed over the sacrificial layer. Fig. 5 to 8 are detailed flows for implementing step S30 according to an embodiment of the present invention. Referring first to fig. 5, a photoresist layer 140 is formed over the sacrificial layer 122. The photoresist layer 140 fills the first opening 122a of the sacrificial layer 122 and completely covers the metal layer 130. In one embodiment, the photoresist layer 140 comprises a positive photoresist material.
Next, referring to fig. 6, the photoresist layer 140 is exposed by using the first exposure source LS1, and the sacrificial layer 122 (or the metal layer 130) is used as a first mask, so as to form a first exposed region 140a and a first unexposed region 140b in the photoresist layer 140. It is noted that the first exposure source LS1 is disposed on the other side of the substrate 110, and the light emitted by the first exposure source LS1 travels along the first direction D1. In other words, the light emitted from the first exposure source LS1 will penetrate through the substrate 110 along the first direction D1 and pass through the first opening 122 a. Therefore, the portion of the photoresist layer 140 not shielded by the sacrificial layer 122 (or the metal layer 130) receives the light emitted from the first exposure source LS1, thereby forming the first exposure region 140 a. In addition, the portion of the photoresist layer 140 shielded by the sacrificial layer 122 (or the metal layer 130) will not receive the light emitted from the first exposure source LS1, thereby forming the first unexposed region 140 b.
Next, referring to fig. 7, a second mask MS is disposed on one side of the sacrificial layer 122 on the substrate 110, and a portion of the first unexposed area 140b is exposed using a second exposure source LS2, thereby forming a second exposed area 142a in the first unexposed area 140 b. It is noted that the second exposure source LS2 is disposed on one side of the sacrificial layer 122 on the substrate 110, and the light emitted from the second exposure source LS2 travels along the second direction D2, wherein the second direction D2 is opposite to the first direction D1. In other words, the first exposure source LS1 and the second exposure source LS2 are disposed on opposite sides of the substrate 110, and the light emitted from the second exposure source LS2 does not penetrate the substrate 110.
Next, referring to fig. 8, a developing step is performed to remove the first exposure region 140a and the second exposure region 142a, thereby forming a patterned photoresist layer 144. In other words, after the developing step, the first exposure region 140a and the second exposure region 142a are removed simultaneously, and the remaining photoresist layer is the patterned photoresist layer 144. It is noted that the patterned photoresist layer 144 has a second opening 144a, wherein the second opening 144a is connected to the first opening 122a and exposes a portion of the substrate 110 and a portion 130a of the metal layer 130.
Step S40 is performed to form a first circuit layer filling the second opening and covering the exposed portion of the metal layer. Referring to fig. 9, a first circuit layer 150 is formed to fill the second opening 144 a. The first circuit layer 150 covers the exposed portion of the substrate and the portion 130a of the metal layer 130 exposed by the patterned photoresist layer 144. The first circuit layer 150 includes any conductive material, such as a metal, e.g., copper, nickel, or silver. The first circuit layer 150 is formed by a plating process, but not limited thereto. As shown in fig. 9, the first circuit layer 150 is embedded in the metal layer 130, and the upper surface of the first circuit layer 150 protrudes from the upper surface of the metal layer 130.
Step S50 is performed to form a first dielectric layer over the sacrificial layer and covering the metal layer. Fig. 10 to 11 show the detailed flow of implementing step S50 according to an embodiment of the present invention. Referring first to fig. 10, a second precursor dielectric layer 220 is formed over the sacrificial layer 122 and covers the metal layer 130 and the first circuit layer 150. The second precursor dielectric layer 220 is formed in a manner and with a material similar to the sacrificial material layer 120, and will not be described herein. Referring next to fig. 11, a plurality of third openings 222a are formed in the second precursor dielectric layer 220 to form a first dielectric layer 222. The third opening 222a exposes the first circuit layer 150. The third opening 222a is formed in a manner similar to the first opening 122a, and is not described in detail herein.
Step S60 is performed to form a second circuit layer filling the second opening and covering a portion of the first dielectric layer. Referring to fig. 12, a second circuit layer 250 is formed to fill the third opening 222a and cover a portion of the first dielectric layer 222. The second circuit layer 250 is formed in a manner and with a material similar to that of the first circuit layer 150, and is not described herein again.
It should be understood that the number of dielectric layers and the number of circuit layers shown in fig. 12 are merely exemplary, and those skilled in the art can appropriately select the desired number of dielectric layers and number of circuit layers according to actual needs. For example, referring to fig. 13, in other embodiments of the present invention, after forming the second circuit layer 250, the method 10 further comprises forming a second dielectric layer 322 over the first dielectric layer 222. The second dielectric layer 322 is disposed on the first dielectric layer 222 and the second circuit layer 250, and has a plurality of fourth openings 322 a. With continued reference to fig. 13, in other embodiments of the present invention, after forming the second dielectric layer 322, the method 10 further includes forming a third circuit layer 350 filled in the fourth opening 322a, wherein the third circuit layer 350 covers a portion of the second dielectric layer 322. The formation method and material of the second dielectric layer 322 and the third circuit layer 350 are similar to those of the first dielectric layer 222 and the second circuit layer 250, respectively, and are not repeated herein.
Referring to fig. 14, in one embodiment of the present invention, after the desired number of dielectric layers and number of circuit layers are reached, the method 10 further includes forming a solder mask 400 on the outermost dielectric layer. For example, a solder mask 400 may be formed on the second dielectric layer 322, as shown in fig. 14. The solder resist layer 400 can be formed by, for example, bonding, screen printing, coating, or the like.
Next, in step S70, the substrate is removed, so as to expose the sacrificial layer, a portion of the metal layer and a portion of the first circuit layer. As shown in fig. 15, the substrate 110 is removed, thereby exposing the sacrificial layer 122, a portion of the metal layer 130, and a portion of the first circuit layer 150. Next, in step S80, the sacrificial layer and the metal layer are sequentially removed to expose all the first circuit layer. As shown in fig. 16, in one embodiment of the present invention, the sacrificial layer 122 is first removed, thereby exposing the entire metal layer 130. Next, as shown in fig. 17, the metal layer 130 is removed, so that a portion of the first circuit layer 150 covered by the metal layer 130 is exposed.
It is noted that, compared to the conventional method of forming the conductive bump and the circuit layer directly contacting the conductive bump through different manufacturing processes, the method of manufacturing the circuit board structure of the present invention can form the conductive bump 160 while forming the first circuit layer 150. In detail, the first circuit layer 150 has a first portion 150a and a second portion 150 b. The first portion 150a protrudes out of the first dielectric layer 222 to serve as a conductive bump 160. Therefore, in the circuit board structure obtained by the above method, no hole ring appears at the periphery of the conductive bump 160, thereby improving the area utilization rate of the chip connection side of the circuit board. In addition, compared with the traditional manufacturing method, the method of the invention does not need an additional step of forming the conductive bump, thereby reducing the time and the cost of the manufacturing process. Furthermore, the conductive bump 160 formed by the method of the present invention is integrally formed with the second portion 150b directly contacting with the conductive bump 160, i.e. there is no cross section between the conductive bump 160 and the second portion 150 b.
Another aspect of the present invention is to provide a circuit board structure. Referring to fig. 17, in an embodiment of the invention, the circuit board structure 100 includes a first dielectric layer 222, a second dielectric layer 322, a first circuit layer 150, a second circuit layer 250, a third circuit layer 350 and a solder resist layer 400. It is noted that the first circuit layer 150 has a first portion 150a and a second portion 150 b. The first portion 150a protrudes from the top surface 222b of the first dielectric layer 222, and the second portion 150b is embedded in the first dielectric layer 222 and exposed from the top surface 222 b. The first portion 150a and the second portion 150b are integrally formed. There is no cross-section between the first portion 150a and the second portion 150 b. The second circuit layer 250 is disposed on the first dielectric layer 222 and embedded in the second dielectric layer 322. The third circuit layer 350 is on the second dielectric layer 322 and covers a portion of the second dielectric layer 322. The solder resist layer 400 covers a part of the third circuit layer 350, and the solder resist layer 400 has an opening exposing a part of the third circuit layer 350. The first circuit layer 150, the second circuit layer 250 and the third circuit layer 350 are electrically connected to each other. It should be understood that the number of dielectric layers and the number of circuit layers shown in fig. 17 are only illustrative and not intended to limit the present invention.
It is noted that the first portion 150a and the second portion 150b of the first circuit layer 150 shown in fig. 17 are integrally formed. Please refer to fig. 18 and fig. 19. Fig. 18 shows a bottom view of region R1 in fig. 17. Fig. 19 is a perspective view of the first circuit layer 150 located in the region R1 in fig. 18. Specifically, in fig. 18 and 19, the first circuit layer 150 includes a first portion 150a and a second portion 150 b. The first portion 150a protrudes above the first dielectric layer 222. The second portion 150b is embedded in the first dielectric layer 222. The first portion 150a and the second portion 150b are integrally formed. In other words, the circuit board structure of the present invention is different from the conventional circuit board, and there is no cross section or rough contact surface between the first portion 150a and the second portion 150 b.
In summary, the present invention provides a circuit board structure and a method for manufacturing the same. Compared with the traditional circuit board structure manufacturing method, the manufacturing method of the invention does not need an additional step of forming the conductive bump, thereby reducing the manufacturing process time and cost. In addition, in the circuit board structure obtained by the method, the periphery of the conductive bump does not have a hole ring, thereby improving the area utilization rate of the chip connection side of the circuit board. In addition, in the circuit board structure formed by the method of the present invention, the conductive bump and the circuit layer directly contacted with the conductive bump are integrally formed, that is, a section does not exist between the conductive bump and the circuit layer directly contacted with the conductive bump.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (10)
1. A method of manufacturing a circuit-board structure, comprising the steps of:
forming a sacrificial layer on a substrate, wherein the sacrificial layer has a first opening exposing a portion of the substrate;
forming a metal layer on the sidewalls and top surface of the sacrificial layer;
forming a patterned photoresist layer over the sacrificial layer, wherein the patterned photoresist layer has a second opening, the second opening is communicated with the first opening and exposes a portion of the metal layer;
forming a first circuit layer to fill in the second opening and the first opening and cover the part of the metal layer;
forming a first dielectric layer on the sacrificial layer and covering the metal layer, wherein the first dielectric layer has a third opening to expose the first circuit layer;
forming a second circuit layer filling in the third opening and covering a part of the first dielectric layer;
removing the substrate, thereby exposing the sacrificial layer, a portion of the metal layer and a portion of the first circuit layer; and
removing the sacrificial layer and the metal layer.
2. The method of claim 1, wherein: the first circuit layer has a first portion and a second portion, the first portion is located in the first opening, the second portion is located in the second opening, and the first portion and the second portion are integrally formed.
3. The method of claim 1, wherein: wherein forming the metal layer on the sacrificial layer comprises conformally forming the metal layer on the sacrificial layer.
4. The method of claim 1, wherein forming the patterned photoresist layer over the sacrificial layer comprises:
forming a photoresist layer over the sacrificial layer;
exposing the photoresist layer by using a first exposure source, wherein the first exposure source and the sacrificial layer are arranged on two opposite sides of the substrate;
exposing the photoresist layer by using a second exposure source, wherein the second exposure source is arranged on one side of the sacrificial layer on the substrate; and
and developing to form the patterned photoresist layer.
5. The method of claim 4, wherein: wherein the photoresist layer comprises a positive photoresist material.
6. The method of claim 1, wherein: wherein the substrate is made of a material that is transparent to light.
7. The method of claim 1, further comprising, after the step of forming a second circuit layer and before the step of removing the substrate:
forming a second dielectric layer on the first dielectric layer and covering the first dielectric layer and the second circuit layer, wherein the second dielectric layer has a fourth opening therein to expose the second circuit layer; and
and forming a third circuit layer filled in the fourth opening and covering a part of the second dielectric layer.
8. The method of claim 1, further comprising, after the step of forming the second circuit layer and before the step of removing the substrate:
forming a solder mask layer on the first dielectric layer.
9. A circuit board structure, comprising:
at least one dielectric layer;
a first circuit layer having a first portion and a second portion, wherein the first portion protrudes from the top surface of the dielectric layer, the second portion is embedded in the dielectric layer and exposed from the top surface, the first portion and the second portion are integrally formed, and no cross section exists between the first portion and the second portion; and
the second circuit layer is arranged above the dielectric layer and is electrically connected with the first circuit layer.
10. The circuit board structure of claim 9, wherein: wherein the at least one dielectric layer is a plurality of dielectric layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910672259.3A CN112291940A (en) | 2019-07-24 | 2019-07-24 | Circuit board structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910672259.3A CN112291940A (en) | 2019-07-24 | 2019-07-24 | Circuit board structure and manufacturing method thereof |
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| CN112291940A true CN112291940A (en) | 2021-01-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201910672259.3A Pending CN112291940A (en) | 2019-07-24 | 2019-07-24 | Circuit board structure and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114126240A (en) * | 2021-10-19 | 2022-03-01 | 宏华胜精密电子(烟台)有限公司 | Manufacturing method of MiniLED circuit board |
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| JP2019062113A (en) * | 2017-09-27 | 2019-04-18 | 日立化成株式会社 | Manufacturing method of wiring layer |
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| US5246817A (en) * | 1985-08-02 | 1993-09-21 | Shipley Company, Inc. | Method for manufacture of multilayer circuit board |
| TW502392B (en) * | 2001-09-28 | 2002-09-11 | Taiwan Semiconductor Mfg | Manufacturing method of solder bumps |
| CN101902884A (en) * | 2009-05-26 | 2010-12-01 | 欣兴电子股份有限公司 | Method for making composite material circuit board structure |
| CN107872929A (en) * | 2016-09-27 | 2018-04-03 | 欣兴电子股份有限公司 | Wiring board and its preparation method |
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| CN114126240A (en) * | 2021-10-19 | 2022-03-01 | 宏华胜精密电子(烟台)有限公司 | Manufacturing method of MiniLED circuit board |
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