TW502382B - A wiring and a method for manufacturing the wiring, and a thin film transistor array panel including the wiring and method for manufacturing the same - Google Patents

Abstract

In a method of fabricating a thin film transistor array substrate, a glass substrate suffers oxygen plasma treatment. A silver or silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a gate line assembly proceeding in the horizontal direction. The gate line assembly includes gate lines, gate electrodes, and gate pads. Thereafter, a silicon nitride-based gate insulating layer is deposited onto the substrate, and a semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. The semiconductor layer and the ohmic contact layer are HF-treated. A silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a data line assembly. The data line assembly includes data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer based on silicon nitride or an organic material is deposited onto the substrate, and patterned through dry etching such that the protective layer bears contact holes exposing the drain electrodes, the gate pads and the data pads, respectively. An indium zinc oxide or indium tin oxide-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, and subsidiary gate and data pads. The pixel electrodes are electrically connected to the drain electrodes, and the subsidiary gate and data pads to the gate and data pads.

Description

502382 A7 B7 V. Description of the invention (1) Background of the invention (a) Field of the invention The present invention relates to a wiring assembly and a method for manufacturing the wiring assembly, and a thin film transistor array substrate having the wiring assembly and a method for manufacturing the substrate. . (b) Relevant technical description In general, the wiring of semiconductor devices or display devices is used for signal transmission, so it is very important to avoid signal delay in such wiring. Therefore, this type of wiring must be manufactured using low-impedance conductive materials. For example, silver (Ag) can be used for this type of conductive material. However, if silver or a silver alloy is used for this purpose, there is a disadvantage that the resulting wire has poor adhesion to the underlying substrate or film. Furthermore, the wiring can easily come off the substrate or film. SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor array substrate having a wiring assembly having low impedance and good adhesion. A thin film transistor array substrate having the following functions and having a wiring combination can also achieve other purposes. · A glass substrate is treated with oxygen plasma before depositing a deposited layer containing silver or silver alloy as the main component. If the substrate is made of silicon, it is subjected to hf ^ treatment, and an annealed layer is deposited after depositing the layer with silver or -silver alloy as the main component. In the method for manufacturing a wiring assembly for a display device according to the aspect of the present invention, a glass substrate is subjected to an oxygen plasma treatment. One is mainly composed of silver or silver alloy -4-502382 A7 ----, _ B7_ __ Five, (2) '—' ~ ^-parts of the thin film are deposited on the substrate and form a pattern. When depositing a thin film containing silver alloy as the main component, sputtering can be used. The silver alloy can be composed of silver (Ag) as the main content and a conductive material with an alloy content of 0.01-20 at 0 miC0 / 0. The alloy contents have one or more conductive material components selected from the group consisting of Pd, Cu, Mg, Al, Li, Pu, Np, Eu, Pr, Ca, La, Nb, Nd, or Sm. The substrate having a thin film mainly composed of a silver alloy may be further annealed. In the method for manufacturing a wiring assembly for a display device according to another aspect of the present invention, a silicon substrate is subjected to HF processing. A thin film mainly composed of a silver alloy is deposited on the silicon substrate and formed into a pattern. When depositing a thin film containing silver alloy as the main component, sputtering can be used. The silver alloy can be composed of silver (Ag) as the main content and 0.01-20 atomic% of the alloy content conductive material. The alloy content has one or more conductive material components selected from: Mg, Ca, Th, Zr, Co, Ni, Ti, v,

Nb, Mo, Ta, w, or A silicon substrate having a thin film mainly composed of a silver alloy can be further annealed. The annealing process can be performed at a temperature of 25-50 τ. In the method for manufacturing a thin film transistor array substrate according to another aspect of the present invention, a substrate is subjected to an oxygen plasma treatment. A thin film mainly composed of silver or a silver alloy is deposited on the substrate and formed into a pattern, thereby forming a gate line assembly. The gate line combination includes a gate line and a gate electrode. A gate insulating layer is deposited on the substrate, and a semiconductor layer mainly composed of undoped amorphous silicon is formed on the gate insulating layer. A data line combination is formed on the semiconductor layer. _Data line combination includes data line, source and drain.

DESCRIPTION OF THE INVENTION (This thin film containing silver alloy as the main component can be sputtered. The silver alloy can be composed of the main content silver (Ag) and the alloy content conductive material atomic%. The alloy content has one or more A component selected from the following conductive materials: Pd, Cu, Mg, Al, Li, Pu, Np, Ce, pu, Pr, Ca, La, Mb, Nd, or Sm. The thin film mainly composed of silver alloy can be passed through Annealing. The substrate may be made of glass. In a method of manufacturing a thin film transistor array substrate according to another aspect of the present invention, a layer having a conductive material as a main component is deposited on a substrate and patterned, thereby forming a gate line assembly. The gate line combination includes a gate line and a gate electrode, and a gate insulating layer is deposited on the substrate, and a semiconductor layer is formed on the gate insulating layer. The semiconductor layer is processed by HF. A thin film mainly composed of a silver alloy is deposited on the substrate. A pattern is formed on the semiconductor layer to form a data line combination. The data line combination includes a data line, a source electrode, and a drain electrode. The annealing process can be used for films containing silver alloy as the main component. In order to strengthen the adhesion between the thin film and the underlying semiconductor layer. Τ In this case, the HF treatment applied to the semiconductor layer can be omitted. The thin film containing a silver alloy as a main component can be deposited by sputtering. The silver alloy It can be composed of the main content silver (Ag) and the alloy content conductive material 0.01-20 at 0mic 0 / 〇. The alloy content has one or more conductive material components selected from the following: Mg, Ca, Th, Zr, Co , Ni, Ή, v,

Nb, M0, Ta, W, or Shi Xi substrates with a thin film containing silver alloy as the main component may be additionally annealed. The annealing process may be performed at a temperature of 250-1005. / Dish again

Binding

A protective layer may cover the semiconductor layer and a pixel electrode may be connected to the drain.

502382 V. Description of the invention (4) pole. The pixel electrode may be made of a transparent conductive material. The gate line combination may further include a gate fill connected to the gate line, and the data line combination may further include a data fill connected to the data line. The auxiliary gate and data fill connected to the closed and data fill can be formed on the same plane as the pixel electrode. The semiconductor layer may be composed of a lower layer containing non-rhenium amorphous particles as a main component and an upper layer containing doped amorphous silicon as a main component. Salty; shell material, spring, 'and a, non-doped amorphous silicon as the main component of the deposition, and doped amorphous stone as the main component of the deposition layer, can be formed by photolithography logic simple instructions I That is, a more complete understanding of the present invention can be obtained by referring to the following detailed description, and many related advantages of the present invention will be more obvious. In addition, the accompanying drawings are provided, wherein the reference symbols represent the same or similar elements, wherein: Side view of the thin film of the wiring assembly on the glass substrate; Θ 2A to 2E 疋 Films with a silver film as the main component deposited on the glass substrate. The photo shows the state of adhesion between the film and the glass substrate; Figure 3 is an illustration of Figure 2A to Chart of adhesion between thin film and glass substrate in 2E. Figures 4A to 4E are photos of thin films deposited on glass substrates with two sources of extremely silver alloys as the main damage. The photos show the state of adhesion between thin film and glass substrate; Figure 5 is a graph illustrating the adhesion between the film and the glass substrate in Figures 4A to 4E ____ -7- This paper is compliant with National Standards (CNS) M specifications (21 × 297 public love) V. Description of the invention (5) Figure 6 A to 6E: Films deposited on glass substrates with three sources of extremely silver alloys as the main cause of damage. 'Photos show the state of adhesion between the film and the glass substrate. Graphs of adhesion between Figures 8A to 8D are photos of the main components of the film deposited on the glass substrate. The photos show the state of adhesion between the film and the glass substrate. Figure 9 illustrates the adhesion between the film and the glass substrate in FIGS. Figures 10A to 10D are photographs of films deposited on glass substrates with AgTi as the main component. The photos show the state of adhesion between the film and the glass substrate. Figure 11 illustrates the films and the broken glass substrate in Figures 10A to 10D. Graphs of adhesion between graphs; Figures 12 and 13 illustrate the deposition of AgMg-based films and AgTi-based films on HF-treated and untreated substrates. FIG. 14 is a graph illustrating a melting point temperature of an alloy containing silicon as a main component and an enthalpy content based on the melting point temperature; FIG. 15 is a graph showing A plan view of a thin film transistor array substrate for a liquid crystal display of a preferred embodiment; FIG. 16 is a side view of the thin film transistor array substrate cut along the line of FIG .; FIG. The steps of the thin film transistor array substrate shown in Fig. 15; _ _ 8-This paper size is applicable to the GG family standard (CNS) M specification (for public love) 502382 A7 __ B7 V. Description of the invention (6) 17B is a side view of the thin film transistor array substrate cut along the XVIIb-XVIIb 'line of FIG. 17A; FIG. 18B is a side view of the thin film transistor array substrate cut along XVIIIb-XVIIIb% ^ of FIG. 18A Figure 19B is a side view of the thin film transistor array substrate cut along the XlXb-XIXb 'line of Figure 19A; Figure 20B is a thin film transistor array cut along the XXb-XXb * line of Figure 20A A side view of the substrate; FIG. 21 is a plan view of a thin film transistor substrate for a liquid crystal display according to a second preferred embodiment of the present invention; and FIGS. 22 and 23 are respectively taken along lines XXIII-XXII and XXIII-XXII Cut out the thin as shown in Figure 21 A side view of the transistor array substrate; FIG. 24A illustrates the first step of manufacturing the thin film transistor array substrate shown in FIG. 21; FIGS. 24B and 24C are cut along the lines XXIVb_XXIVbf and XXIVc-XXIVc1 of FIG. 24A, respectively. 25A and 25B illustrate the steps of manufacturing the thin-film transistor array substrate shown in FIG. 21 in accordance with FIGS. 24B and 24C, respectively; FIG. 26A illustrates the steps in accordance with FIGS. 25A and 25B. 25B. The steps of manufacturing the thin film transistor array substrate shown in FIG. 21; FIGS. 26B and 26C are side views of the thin film transistor array substrate cut along the XXVIb-XXVIb1 line and XXVIc-XXVIc1 line of FIG. 26A, respectively- 9- This paper size applies to China National Standard (CNS) A4 (210X297 mm) 502382

The front page of the Yuexi No. 08 patent application (June 91) A7 B7 V. Description of the invention (7) IS2 · _, Figure 27A / B, Figure 28A / B and Figure 29A / B The description is based on Figure 26B and 26C. The steps of manufacturing the thin film transistor array substrate shown in FIG. 21; FIG. 30A illustrates the steps of manufacturing the thin film transistor array substrate shown in FIG. 21 according to FIGS. 29A and 29B; and FIGS. 30B and 30C are respectively A side view of the thin film transistor array substrate cut along the lines XXXb-XXXb * and XXXc-XXXc: of FIG. 30A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be explained with reference to the drawings. Figure 1 is a side view of a thin film deposited on a glass or silicon substrate. In order to manufacture a wiring assembly for a semiconductor device or a display device, as shown in FIG. 1, a thin film 200 mainly composed of a conductive material having a low resistance such as silver and a silver alloy is deposited on a substrate 100 and patterned by photolithography. . In the case of the thin film 200 using a silver alloy as a main component, the thin film may be composed of the main content silver (Ag) and the alloy content conductive material at 0.01-20 atomic% or less. The alloy content has one or two conductive material components selected from the group consisting of Pd, Cu, Mg, Al, Li, Pu, Np, Ce, Eu, Pr, Ca, La, Nb, Nd, or Sm. That is, two or three source silver alloys can be used for the thin film 200. Since the film 200 containing silver or a silver alloy as a main component has poor adhesion to the base substrate 100, it is necessary to strengthen the adhesion between the film 200 and the substrate 100. When using a semiconductor device or a thin film transistor array substrate for liquid crystal display, this adhesion should reach more than 20 Newtons (N) -10- This paper size applies to China National Standard (CNS) A4 (210 X 297) (Mm) 502382 A7 ____B7 V. Description of the invention (8) To this end, in the case of using a glass substrate, the substrate may be treated with an oxygen plasma before depositing a conductive layer containing silver or a silver alloy as its main component, or After the conductive layer is deposited, an annealing process is performed. The oxygen plasma treatment is preferably performed under a pressure of 1 to 100 Tao for 5:00 to 30 minutes, and the oxygen is sprayed at 1 to 100% (^). The annealing process is preferably performed in an air, nitrogen, or hydrogen environment. The temperature is 250-500 ° C for 30-12 minutes. When using a silicon substrate, the substrate can be subjected to HF treatment before deposition of a conductive layer containing silver or a silver alloy as the main component, or it can be conducted by deposition. After the layer, an annealing process is performed. In the HF process, the silicon substrate 100 is immersed in the HF solution. The HF solution is prepared by using HF raw materials and extremely pure water at 1 / 5-1 / 2. 〇 Proportional dilution. The soaking time is preferably between 1-60 minutes (assuming that the dilution concentration is 1/1100, more preferably between 5-10 minutes). If the alloy content is selected from refractory metals, During the annealing process, a silicide layer can be formed between the thin film 200 and the substrate 100. The annealing process can be carried out at a temperature of 25-500 t under the conditions of air, hydrogen, or nitrogen at a temperature of 25-500 t. -12 0 minutes. Figures 2A to 2E are photographs of silver-based films formed on glass substrates, with silver as the main component. A part of the film was scored with a scoring tester to show the adhesion state. Fig. 3 is a graph illustrating the adhesion between the film containing silver as the main component and the glass substrate. In the glass substrate shown in the figure, The films shown in 2A and 2B are covered by films not treated with oxygen plasma, and the A film is scored by a notch test. The glass substrates shown in Figures 2c to 2E are at 150 W, 200 Oxygen plasma treatment was performed at W and 300 W, and the film was scored with a scoring tester. As shown in Figures 璃 to 2], the glass-breaking substrate is covered by a film not treated with oxygen plasma, and -11-502382 A7 at 3000 ° C

The annealing process was performed for 30 minutes. = Established, the thickness of the film with silver as the main component is about i μm. The annealing process was performed in the case of Lili 2 Zulter. Oxygen plasma treatment was performed in the case of Lier and Tao, and the flow rate of oxygen was 13 claws. A notch tester with a diamond-tipped tip can be used to measure adhesion. Scratch the film while measuring, while gradually increasing the force applied to the tip of the score tester, which is in the range of 0-20 N. Take pictures in six areas. The lines shown in the photo were scored with a sharp tip of a scoring tester, and the applied force gradually increased from left to right. ^ #As shown in Figures 2 and 3, a thin film fan with silver as the main component is deposited on a glass substrate 100 without oxygen plasma treatment. Measure the adhesion in this condition. As a result, it was found that the adhesion was slightly increased, but the film 200 detached from the substrate 100 when the applied force reached 7 N. As shown in Figs. 2B and 3 ', a thin film containing silver as a main component was deposited on a glass substrate 100 which had not been treated with oxygen plasma, and passed through%. ^ 'S annealing. Measure the adhesion in this condition. As a result, it was found that the adhesion was slightly increased, but the film 200 detached from the substrate 1000 when the force reached 7 N. As shown in FIGS. 2C to 2E and 3, the glass substrate 100 is subjected to an oxygen plasma treatment at 150 w, 2000 ', or 300 w. A thin film containing silver as the main component is deposited on the substrate 100 and annealed. Measure the adhesion in this condition. Even if the force applied to the tip of the nick tester is more than 20 N, the film is not detached from the substrate 100. Next, after the oxygen plasma treatment, the adhesion between the substrate 100 and the thin film 200 can be increased relative to the substrate 100. 4A to 4E are photographs of a thin film formed of two sources of extremely silver alloys on a glass substrate, in which the thin film is engraved with a nick tester, thereby showing a state of adhesion. Fig. 5 illustrates a thin film containing silver alloy as the main component.

Hold

502382 A7 ____ B7 V. Description of the invention (10 ~) " — Graph of adhesion between film and glass substrate. The processing conditions of FIGS. 4A to 4E are the same as those of FIGS. 2A to 2E, except that the material used for the film is a two-source extremely silver alloy with a main content Ag and an alloy content Mg 5 atomic%, and the deposition method is borrowed These two conditions are performed by sputtering. As shown in Figs. 4A, 4B, and 5, a glass substrate 100 is covered with a thin film 200 mainly composed of AgMg without oxygen plasma treatment. When the force applied to the tip of the nick tester is about 3 N, the thin film 200 is detached from the substrate 100. That is, the adhesion between the substrate 100 and the thin film 200 is relatively weak. As shown in Figs. 4C and 5, a glass substrate 100 treated with an oxygen plasma under 150 W is covered with a thin film 200 composed mainly of a silver alloy and annealed at 300 ° C. It was found that the adhesion increased by 3 n. As shown in Figs. 4D, 4E and 5, the glass substrate 100 which has been subjected to an oxygen plasma treatment at 200 W or 300 W is covered with a thin film 200 containing a silver alloy as a main component and annealed. Even if the force applied to the tip of the nick tester reaches 20 N or more, the film is not detached from the substrate 100. That is, the adhesion between the substrate 100 and the thin film 200 is greatly increased. Figures 6A to 6E are photographs of a thin film formed of three sources of extremely silver alloys on a glass substrate. The thin film is scratched with a nick tester to show the adhered state. Fig. 7 is a graph illustrating adhesion between a film and a glass substrate. The processing conditions of FIGS. 6A to 6E are the same as those of FIGS. 2A to 2E, except that the material used for the film is a three-source polar silver alloy with a main content Ag and an alloy content Pd and Cu 5 atomic%, and a deposition method Beyond these two conditions by cheap shots. As shown in Figures 6A, 6B and 7, it is treated with AgPdCu without oxygen plasma treatment. __ -13 -___ 'This paper size is applicable to China National Standard (CNS) 8-4 specification (21〇x297 public love) — --- 502382 A7 I_______B7 V. Description of the invention (11) The thin film 20 as the main component covers the glass substrate 100. When the force applied to the nick test is about 3 N, the film 200 will be separated from the substrate 100. That is, the adhesion between the substrate 100 and the thin film 200 is relatively weak. As shown in FIGS. 6C to 6E and 7, a glass substrate 100 treated with an oxygen plasma under 150w, 200w, or 300w is covered with a thin film 200 mainly composed of a silver alloy. And annealed. The film did not come off the substrate 100 even when the force applied by the tip of the nick tester reached 20 N or more. That is, the adhesion between the substrate 100 and the thin film 200 was greatly increased by the oxygen plasma treatment. Figs. 8A to 8D are photographs of a film made of AgMg as a main component formed on a single crystal substrate, and the towel film is scribed with a scoring tester, thereby showing an attached state. Fig. 9 is a graph illustrating the adhesion between a thin film containing a silver alloy as a main component and a silicon substrate. In the silicon substrate shown in the figure, the films shown in FIGS. 8A and 8B are covered with a film without HF treatment, and the film is scored with a nick tester. The silicon substrate shown in FIG. 8A is annealed, but the silicon substrate tf shown in FIG. 8B is not annealed. The silicon substrates shown in FIGS. 8 (: and 80) are processed by HF and covered by the film. The silicon substrates shown in FIG. 8 are not annealed, but the substrates shown in FIG. 81 are annealed. The symbols "A" and "HF" indicate the annealing process and HF treatment, respectively, and the symbol nHF-An indicates the annealing and HF treatment. The silver alloy is composed of a target material having a main content of Ag and an alloy content of 5 atomic%. The target material was sputtered onto the substrate under a pressure of 2 Torr, and the pressure of the argon gas sprayed was 2 × ΐ〇th Taur. The annealing was performed at a pressure of 2 × 106 Tall and a temperature of 300 ° C. 3 ° C. 〇minutes. With L-14-This paper is suitable for domestic use (CNS) A4 size (2ιχχ297 public love) View 382 A7-B7 V. Description of the invention (12) Scoring tester with diamond tip Can be used to measure adhesion. Scribing on the film during measurement, while gradually increasing the force applied to the tip of the nick tester, in the range of 0-40 N. Take pictures in six areas. Shown in the photo The lines are scribed with a pointed head of a scoring tester, and the force is gradually increased from left to right. As shown in Figs. 8A and 9, a thin film 200 mainly composed of AgMg is deposited on silicon without HF treatment. On the substrate 100. The adhesion was measured under this condition. As a result, it was found The film 2 0 was detached from the substrate 100 when the force of the tip of the scoring test roll reached 5 n. As shown in FIGS. 8B to 8D and 9, the silicon substrate 100 was subjected to HF treatment, and a film composed mainly of silver alloy. 200 was deposited on a silicon substrate 100. The silicon substrate 100 covered with the thin film 200 was annealed at a temperature of 300 ° C for 30 minutes. The evolution of the results

The adhesion between the substrate 100 and the thin film 200 increased by 27 N, 32 N, and 38 N. FIGS. 10A to 10D are photographs of a thin film containing AgTi as a main component formed on a glass substrate. The thin film is written with a nick tester. Thereby, the adhered state is exhibited. FIG. 11 is a graph illustrating adhesion between a film and a glass substrate. The processing conditions of Figures 10A to 10D are the same as those of Figures 8A to 8D, except that the material used for the film is a target material with 5% atomic% of the main content Ag and alloy content, and the deposition method is borrowed. These two conditions are performed by sputtering. — As shown in FIGS. 10A and 11, a glass substrate 100 is covered with a thin film 200 containing AgTi as the main component without any financial treatment. When the force applied to the tip of the nick tester is about 12 N, the film 200 is detached from the substrate 100. Which is -15-

502382 A7 B7 5. Description of the Invention (13) It is said that the adhesion between the substrate 100 and the film 200 is relatively weak. As shown in FIGS. 10B to 10D and 11, the glass substrate 100 subjected to the oxygen plasma treatment is covered with a thin film 200 containing a silver alloy as a main component and annealed at 300 ° C. As a result, the adhesion between the substrate 100 and the film 200 increased by more than 20 N. Figures 12 and 13 are graphs illustrating the relationship between the resistivity and the annealing temperature of films with AgMg as the main component and films with AgTi as the main component deposited on HF-treated substrates and untreated substrates. The horizontal axis of the graph represents the resistivity, and the vertical axis represents the annealing temperature. The symbol "As-dep" means that the substrate covered with a thin film containing silver alloy as the main component is unannealed. As shown in FIG. 12, AgMg is deposited on the HF-treated substrate and the untreated substrate. The film with the main component has a resistivity of 4 · 5 μ. When the film is annealed, the resistivity decreases. As a result, when the annealing temperature is 3 00-5 00 C, the resistivity is about 3 〇_3 5 μ As shown in Figure 13, the film with AgTi as the main component deposited on HF-treated substrates and untreated substrates has a resistivity of 10 μ Q-cm. When the film is annealed, the resistivity decreases The result is that when the annealing temperature is 300-500 ° C, the resistivity is about 4 5 picm. At the same time, under the annealing process, the thin film 200 and the silicon substrate with a silver alloy (AgMg, AgTi) as the main component can be used. A silicide layer is formed between the two layers. The disintegration layer can be used to increase the adhesion between the thin film 20¾ and the silicon substrate 100. Figure 14 illustrates the melting point temperature (κ) and the heat content (ΔΗΓ, kcal / mole) of the silicon alloy. ). It can be found from the figure that the film A 200 silver alloy interacts with the silicon of the substrate 100 to form a silicide layer. -16-

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The above-mentioned oxygen plasma or HF treatment or annealing techniques are used to increase the adhesion between the thin film and the underlying substrate. This technology is also applicable to substrates other than glass or silicon materials. The structure of the thin film transistor array substrate according to the first preferred embodiment of the present invention will be described with reference to FIGS. 15 and 16. 5 is a plan view of a thin film transistor array substrate according to the first preferred embodiment of the present invention, and FIG. 16 is a side view cut along the line XVI-XVI of FIG. 15. A gate line combination having a single-layer or multi-layer structure is formed on the insulating substrate 10, in which silver or a silver alloy of two or three source electrodes is displayed. This brake wire assembly has an adhesion of 20 N or more to the substrate 10. The gate line combination includes a gate line 22 that is deployed in a horizontal direction and a gate filler 24 connected to the end of the gate line 22. The gate filler 24 receives the gate signal from Wai Shao and transmits it to the gate line 22. The gate electrode 26 of the TFT is connected to the gate line 22. Assume that the formed brake wire combination has a multi-layered structure, which may include a filler material, which has a Teflon that has good contact with other materials. It is assumed that the filling material is a silver alloy bird with two or three source electrodes, and the material can be composed of the silver content of the king content and the conductive material of the alloy content 〇 · 〇ι_2〇 coffee. The gold content includes, for example, pd, cu , Ton, octane Li, PU, Np, Ce, Eu, Pr, Ca, La, Nb, Nd, and Sm. The interlayer 30 formed on the substrate 10 is composed of silicon nitride and covers the Brake line combination. The semiconductor pattern 40 formed on the gate insulating layer 30 is located above the gate electrode 24, and the ohmic contact patterns 55 and% formed on the semiconductor pattern 40 have 17- ^ 297 ^ ¾)

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JUZJ6Z A7

Silicon f hydrogenated amorphous silicon 'wherein n-type impurities are in a high concentration. ^ Mu _㈣ and 56 and the data line group on the gate „3 () are composed of gold. The data and line combination can have a single-layer or multi-layer structure. = Line combination includes the data line expanded in the vertical direction, and at the same time Beyond the first line 22, the pixel is defined, and the source electrode 65 is included, and the data line seems to be expended to extend the ohmic contact pattern on one side at the same time. " The data filling "is dropped to one end of the lean line 62 in order to receive the graphic signal from the outside. The drain 66 is located on the other side of the ohmic contact pattern 56 and is more separated at the gate electrode 26. To increase the storage capacity, the data line The combination may further include storage of each conductive pattern 64 °. The storage capacitor conductive pattern 64 overlaps with the gate line 22 to form a storage capacitor. Two or three source silver alloys can be used for the data line combination. The formed silver σ Gold has a king content silver and an alloy content conductive material 0.]-?. Atomic% or less, where the alloy content includes, for example, Mg, Ca, Th,

Zr, Co, Ni, rhenium, V, Nb, Mo, Ta, W and Cr. If the formed data line combination has a multilayer structure, t may be composed of a conductive material, and the material has the characteristics of good contact with other materials. A protective layer 70 is formed on the data line combination and the semiconductor pattern, and is formed of nitrided or organic materials with good planarization characteristics, and is exposed through the data line combination. One of the protective layers 70 has contact holes 72, 76, and 78, which can expose the storage capacitor conductive pattern 64, the drain 66, and the data fill 68, respectively. Furthermore, the contact hole 74 of the protective layer 70 can expose the gate filling 24 and the gate insulating layer 30. The pixel electrode 82 is formed on the protective layer 70 in the pixel region, and passes through the contact hole.

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72 and 76 are connected to the storage capacitor conductive pattern 64 and the drain 66. Further, auxiliary gates and data fills 84 and 88 are also formed on the protective layer 70 so as to be connected to the gates and data fills 2 4 and 68 through the contact holes 74 and 78. The pixel electrode 82 and the auxiliary gate and data fill 86 and 88 are made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The storage capacitor conductive pattern 64 connected to the pixel electrode 82 overlaps the gate line 22, thereby forming a storage capacitor. If the storage capacitor is not enough, the storage capacitor line combination can be formed on the same plane as the gate line combination. The thin-film transistor array substrate structured as described above is composed of a wiring combination with low impedance silver or a silver alloy as a main component, which can minimize signal delay, and have a wide screen and high resolution. A method of manufacturing a thin film transistor array substrate will now be explained with reference to Figs. 17A to 20B. As shown in Figs. 17A and 17B, a glass substrate 10 was subjected to an oxygen plasma treatment for ten minutes. A deposition layer mainly composed of silver or a silver alloy is deposited on the broken glass substrate 10 and formed into a pattern, thereby forming a gate line assembly. The gate wire combination includes a gate wire 22, a gate electrode 26, and a gate filler 24. It is assumed that two or three source silver alloys are used for the brake wire combination. The combination may be composed of the main content silver and the alloy content conductive material 0.01-20 atomic%. The alloy content includes, for example, Pd, Cu, Mg. A, Li, PU, Np, Ce, Eu, pr, Ca, La, Nb, Nd, and Sm. The silver alloy is sputtered onto the substrate 10, and a pattern is formed to form the question line combination. Oxygen plasma treatment related to the glass substrate 10 increases the adhesion between the substrate and the deposited layer mainly composed of a silver alloy by more than 20 N. Accumulated with silver in Shen -19-

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After the alloy is the main component layer, the deposited layer is annealed. The oxygen plasma treatment is preferably performed at a pressure of 1 to 100 Tao for 530 minutes, while spraying oxygen with 1 to 1000 sccm. The annealing process is preferably performed in the atmosphere of nitrogen, nitrogen, or hydrogen at a temperature of 250-500 ° C for 30-12 minutes. Then, as shown in FIGS. 18A and 18B, a gate insulating layer 30 mainly composed of silicon nitride, a layer 40 mainly composed of amorphous silicon, and a layer doped with amorphous stone as a principal component. 50 is sequentially deposited on the substrate 10. The layer 40 mainly composed of amorphous silicon and the layer 50 mainly composed of amorphous silicon are patterned through a photomask, thereby forming a semiconductor pattern 40 and an ohmic contact pattern $ 0. The semiconductor pattern 40 and the ohmic contact pattern 50 are both located on the gate insulating layer 30 on the gate electrode 24. As shown in FIGS. 19A and 19B, the substrate is immersed in an HF solution so that the semiconductor pattern 40 and the ohmic contact pattern 50 are subjected to hf treatment. A conductive layer mainly composed of a silver alloy is deposited on the substrate 10 by sputtering, and is patterned by photolithography to form a data line assembly. The data line combination includes a data line 62 crossing the gate line 22 and a source 65 connected to the data line 62 and extending across the gate electrode 26 at the same time. The data fill 68 is connected to one end of the data line 62. The immortal electrode 66 is located near the gate electrode 26 with respect to the source electrode 65, and the storage capacitor conductive pattern 64 overlaps the gate line 22. Silver alloys with two or three sources can be used for data and wire combinations. The formed silver alloy has a main content of silver and a 6-gold internal grain conductive material of 0 · q 1 · 2 0 0 mic%, wherein the alloy content includes, for example, Mg, Ca, Th, Zr, Co, Ni, Ti, V, Nb, Mo, Ta, W, and Cr 〇-20- Zhang Jiao Shi Cai @ s Zhuan Zhuan (CNS) M specifications (2 outlines 297 public y-502382 A7 B7 V. Description of the invention

After the layers 40 and 50 having the shred as the main component are subjected to HF treatment, the adhesion between the shred and the data line combination can be increased by more than 20 N. In order to further improve the strength of such adhesion, the substrate 10 having the data line combination can be annealed at a temperature of 250-500 ° C. In this example, a silicide layer is formed between the stone layer 40 and 50 and the data line combination, while enhancing the adhesion. The ohmic contact pattern 50 exposed through the data line combination is etched so that the patterns 55 and 56 separated on both sides are exposed, and the semiconductor pattern 40 of the underlying layer is exposed at the same time. The exposed semiconductor pattern 40 is treated with an oxygen plasma to make the surface characteristics more stable. Thereafter, as shown in FIGS. 20A and 20B, an insulating material, such as silicon nitride or an organic material, having low dielectric characteristics and good planarization characteristics is deposited on the substrate 10, thereby forming a protective layer 70. Next, the protective layer 70 is patterned by dry etching and the gate insulating layer 30, thereby forming contact holes 72, 74, 76, and 78, exposing the storage capacitor conductive pattern 64, gate fill 24, drain 66, and data fill. 68. Finally, as shown in FIGS. 15 and 16, a layer having ΐτο or IZ〇 as a main component is deposited on the substrate 10, and a photomask is used to form a pattern, thereby forming a pixel electrode 82, an auxiliary gate fill 86, and an auxiliary data fill ". The pixel electrode α is connected to the storage capacitor conductive pattern 64 and the drain 66 through contact holes 72 and 76. The auxiliary gate and data fill 86 and 88 are through the contact hole" and "connected to the gate data fill 24 and 68" This technology can be applied to the method of manufacturing and fabricating a thin film transistor array substrate, not only in the case of a five-layer photomask, but also in a case of a four-layer photomask. Fig. 2i shows a liquid crystal according to a preferred embodiment of the present invention. A plan view of a thin film transistor array substrate shown; Figures 22 and 23 are taken along the figure.

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Side view of the thin-film transistor array substrate cut out of the XXIX-XXIX lines and XXIX-XIXII, lines. Using a conductive material with silver as the main component, a gate line combination is formed on the insulating substrate 丨 0. The gate line combination includes a gate line 22, a gate filler 24, and a gate electrode 26. The gate line combination further includes a storage capacitor electrode 28 which is developed in a direction parallel to the gate line 22 to receive a common electrode voltage from the outside. The storage capacitor electrode 28 and the storage capacitor conductive pattern connected to the pixel electrode 82 have a weight "=", thereby forming a storage capacitor and increasing the potential storage capacitance of the pixel. False ^

Since the storage capacitor becomes relatively high due to the overlap of the pixel electrode 82 and the gate line 22, the storage capacitor 28 can be omitted. The gate insulation layer 30 is composed of silicon nitride on the gate wire combination, and covers the gate wire combination at the same time. The semiconductor patterns 42 and 48 are formed on the gate insulating layer 30 by hydrogenated amorphous silicon. The ohmic patterns 55, 56 and 58 are composed of doped amorphous silicon in the semiconductor patterns 42 and 48, in which n-type impurities such as phosphorus (ρ) are doped at a high concentration. One of the data lines is combined in the ohmic contact patterns 55, 56. And 58 are made of silver alloy. The m data line combination includes a data line 62 expanded in a vertical direction, and a data padding 68 connected to a certain end data line 62 to receive a graphic signal from the outside, and a source 65 branching from the data line 62. The data line combination further includes a drain 66, a source 65 opposite the gate electrode 26, and a storage capacitor conductive pattern 64 above the storage capacitor electrode 28. Assuming that the storage capacitor electrode 28 does not exist, the storage capacitor conductive pattern 64 may be ignored. The data line combination consists of aluminum or aluminum alloy, chromium, molybdenum or molybdenum alloy, thorium, -22-

Or Qin's single layer. The Cumming contact patterns 55, 56, and 58 reduce the contact resistance between the underlying semiconductor patterns 42 and 48 and the data line combination covering it, and have the same appearance as the data line combination. That is, the ohmic contact pattern 55 has the same appearance as the data line 62, the source 65, and the data fill 68, the ohmic contact pattern 56 has the same appearance as the drain 66, and the ohmic contact pattern 58 has a storage capacitance The conductive patterns 64 have the same appearance. Except for the channel region C, the semiconductors 42 and 48 have an appearance similar to that of the data line combination and the ohmic contact patterns 55, 56 and 58. In particular, the semiconductor pattern 48, the conductive pattern 64, and the ohmic contact pattern 58 of the storage capacitor all have the same appearance, but the TFT semiconductor pattern 42 and the data line combination and the corresponding ohmic contact patterns 55 and 56 are slightly different. . That is, the source and drain electrodes 65 and 66 are separated from each other in the through region c, and the data line 62, the source 65 and the ohmic contact pattern 55 of the material fill 68, and the ohmic contact pattern of the drain & 56 are also separated from each other in this part. However, the TFT semiconductor pattern 42 continues to develop in this area without separation, and at the same time forms a channel. A protective layer 70 is composed of silicon nitride on the data line assembly, which is an organic material with lower dielectric characteristics and good planarization characteristics. The protective layer 70 has contact holes 72, 76, and 78, respectively, exposing the data filling 64, the electrode 66, and the storage capacitor conductive pattern 68. Furthermore, the protective layer 70 has a contact hole 74 to expose the gate filling 24 and the gate insulating layer 30. The pixel electrode 82 is formed on the protective layer 70 so as to receive a signal from the TFT and generate an electric field and a common electrode of the counter substrate. The pixel electrode 82 is made of a transparent conductive material similar to ιτο and ιζο. The pixel electrode 82 passes through the contact -23- The paper size is suitable for financial purposes_ Tsukawa (CNS) A4 size (Mongolian 297 public love) 502382 A7

The hole 76 is physically and electrically connected to the drain 66 to receive a graphic signal. The pixel electrode 82 overlaps the adjacent gate and data lines 22 and 62 to increase the opening ratio, but the overlap can be controlled. Furthermore, the pixel electrode 82 may be connected to the storage capacitor pattern 64 through the contact hole 72 to transmit a graphic signal to the pattern. At the same time, auxiliary gates and data pads 84 and 88 are formed on the gates and data pads 24 and 68 so as to be connected to the gates and data pads 24 and 68 through the contact holes 74 and 78. Both the auxiliary gate and data fills 84 and 88 utilize external lines to enhance adhesion 'while protecting the gate and data fills 24 and 68. The auxiliary gates and data fills 84 and 88 may be used in a selective manner. A method of manufacturing a thin film transistor array substrate using a four-layer photomask will now be explained with reference to FIGS. 24A to 30 (:). As shown in FIGS. 24A to 24C, the substrate 10 is treated with oxygen plasma, and one of A conductive material with silver alloy as the main component is deposited on the substrate 10. Then, a layer with the conductive material as the main component is patterned by photolithography to form a gate line combination. The gate line combination includes gate lines 22, The gate filling 24, the gate electrode 26, and the storage capacitor electrode 28. As shown in FIGS. 25A and 25B, a gate insulating layer 30 mainly composed of silicon nitride, a semiconductor layer 40, and an ohmic contact layer 5 are shown. 10 are sequentially deposited on the substrate so as to have thicknesses of 1500-5000 A, 500-2000 A, and 300-600 A, respectively. The ohmic contact layer 50 is HF-treated and a conductive layer 60 containing a silver alloy is borrowed. The ohmic contact layer 50 is deposited by sputtering so as to form a thickness of 1500-3 000 A. A photoresist film i 10 covers the conductive layer 60 to a thickness of μm. At this time, the deposited gate The insulating layer 30 is preferably performed in an environment of 300 ° C or higher for five minutes. -24 -ΐPaper Standard Applicable Country Standard (CNS) M Specification (Fine M9? Public Love) 502382 A7 ___ B7_ 5. After the description of the invention (22), as shown in Figures 26B and 26C, the photoresist film 11 〇 Exposure to light through a reticle and developing it, thereby forming photoresist patterns n 2 and 114. At this time, the first photoresist pattern is located at the channel region 源 between the source and cathode electrodes 65 and 66. Regions 1 to 14 are established, the thickness of which is smaller than the second photoresist pattern region 112 above the data line combination. The remaining region b of the photoresist film is completely private. The first photoresist is located in the channel region C. The thickness ratio of the pattern area 114 and the second photoresist pattern area 1 丨 2 located in the data line combination area A should be different depending on the engraved condition. Preferably, the thicknesses of the first area 114 and the second area 112 The ratio is less than 1/2. For example, the thickness of the first region 114 can be established to be less than 4,000 A. The thickness of the photoresistive film may be different in each region. In order to control the light transmission on the data line combination region A, it may be Use a crack or grid pattern, or a translucent film. It is best that the width of the opening of the crack pattern is smaller than that exposed to light Decomposition ability of the device. In the case of translucent film, different light transmission or thickness can be used to control the light transmission. When light is irradiated on the photoresist film through the photomask, the macromolecules in the light exposure area will be full Decomposition 'and the photoresist film on the crack pattern or translucent film will also be partially decomposed. The photoresist film on the photoresist film will not be decomposed at all. When the photoresist film is developing 'The thickness of the remaining photoresistive film will be locally different. If the light exposure time is too long, all molecules may be decomposed. The photoresist film 114, which is relatively thin, can be reflowed. Production. General masks with transparent and opaque areas will appear. -25- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) '^ ----- 502382 A7 __B7 V. Description of the invention (Z3) Will be used to expose the photoresist film 114 with light. The photoresist film 114 is developed, and a reflow is generated on the photoresist film 114, so that the content of the photoresist film flows to the non-film area. Thereafter, the conductive layer 60, the ohmic contact layer 50, and the semiconductor layer 40 all use a photo-resistant I-worm pattern as a photomask. Therefore, the data line combination area A and the bottom layer are left in the data line combination area A. Only the semiconductor layer 40 is left on the channel area C, and only the insulating layer 30 is left on the remaining area B. For this purpose, as shown in FIGS. 27A and 27B, the conductive layer 60 exposed in the B region is removed while the underlying ohmic contact layer 50 is exposed to the outside. In this process, in the case where the conductive layer 60 is etched, dry etching or wet etching may be used while leaving the photoresist patterns 112 and 114 at the same time. However, if dry etching is used, which is usually used less often, the photoresist patterns 1 12 and 1 14 will be etched simultaneously. In this case, the thickness of the first photoresist pattern region 1 14 should be quite thick to avoid the entire removal of the first photoresist pattern region 1 14 while exposing the underlying conductive layer 60. If the conductive layer 60 is Mo or Mo W alloy, A1 or A1 alloy, or Ta, both dry etching and wet etching can be used. However, if the conductive layer 60 is formed using Cr, wet etching should be used for the etching operation, because dry etching cannot completely remove Cr. In the case of wet etching, CeNH03 can be used as an etching solution. If the conductive layer 60 is Mo or MoW, a mixture of CF4 and HC1 or a mixture of CF4 and O2 can be used as the etching gas. In the latter case, the etching ratios of the conductive layer and the photoresist film are quite close. Therefore, as shown in FIGS. 27A and 27B, only the source / drain conduction case 67 and the storage capacitor conduction pattern 64 will remain, and the conductive layer 60 in the B area will all be shifted to -26- This paper scale applies Chinese national standards (CNS) A4 size (21 × 297 mm)

In addition, the underlying ohmic contact layer 50 is exposed at the same time. The conductive patterns 64 and 67 have a combination-like appearance with the data lines except for the condition that the source and imodes 65 and 66 are continuously expanded without being separated. Even in the case of dry etching, the photoresist patterns 112 and 114 are removed to the same extent. Thereafter, as shown in FIGS. 28A and 28B, the exposed ohmic contact layer 50 and the underlying semiconductor layer 40 in the B region are removed simultaneously from the first photoresist pattern region 114 by dry etching. At this time, the etching should be performed under the conditions of the photoresist patterns 112 and 114. The ohmic contact layer 50 and the semiconductor layer 40 (the semiconductor layer and the ohmic contact layer do not choose an etching method) are simultaneously etched while leaving behind The gate insulation layer is 3G. In particular, the etching ratios of the photoresistance patterns 112 and 114 and the semiconductor layer 40 are preferably the same. For example, the two layers can be etched to the same thickness using a mixture of SF6 and HC1 or a mixture of sh and O2. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first photoresist pattern region 114 should be the same as or less than the sum of the thicknesses of the semiconductor layer 40 and the ohmic contact layer 50. That sum. Therefore, as shown in FIGS. 28A and 28B, the first photoresist pattern region 114 in the C region is removed, and the source / drain pattern 67 is exposed at the same time. The ohmic contact layer 50 and the semiconducting layer 40 in the b region are removed, and the underlying holmium insulating layer 30 is exposed at the same time. The second photoresist pattern region 112 in the A region is also etched while the thickness is reduced. In this process, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 indicate ~ an ohmic contact pattern under the source / drain conduction pattern 67 and an ohmic contact pattern under the storage capacitor conduction pattern 64, respectively. The remaining thin film on the source / drain conduction pattern 67 is removed by ashing. -27- A7

Thereafter, as shown in FIGS. 29A and 29B, the source / drain conduction pattern 67 and the underlying ohmic contact pattern 57 on the channel region C are removed by etching. Dry engraving is applicable to all source / drain conduction patterns 67 and ohmic contact patterns 57. In addition, wet etching can be applied to the source / drain conduction pattern 67, and dry etching can be applied to the ohmic contact pattern 57. In the former example, the etching is preferably performed with a high etching selection ratio of the source / drain conduction pattern 67 and the ohmic contact pattern 57. If the etch-selection ratio is low, it will be difficult to find the etch endpoints, and at the same time it will be difficult to control the thickness of the semiconductor pattern 42 left on the channel region C. For example, a mixture of SF6 and O2 can be used to etch the source / drain conduction pattern 67. If wet etching and dry etching are used alternately, the area on the side of the source / drain conductive pattern 67 treated by wet etching will be etched, but the ohmic contact pattern 57 treated by dry etching will hardly be etched, resulting in a stepped area. A mixture of CL and HC1 or a mixture of Cf4 and O2 can be used as the etching gas. When a mixture of cf4 and O2 is used, the resulting semiconductor pattern 42 can have a uniform thickness. As shown in FIG. 22B, the semiconductor pattern 42 can be partially removed while reducing the thickness. The second photoresist pattern region 112 is also etched to some extent. At this time, the insect engraving can be performed without the insect engraving insulation layer 30. The thickness of the photoresist pattern should be so large that the data line combination is not exposed when the second photoresist pattern area n 2 is etched. Therefore, the source and drain electrodes 65 and 66 are separated from each other to complete the data line group and the underlying ohmic contact-patterns 55, 56 and 58. Finally, the second photoresist pattern region 1 12 remaining on the data line combination region A is removed. However, the second photoresist pattern region 112 can be removed after the source / drain conduction pattern 67 on the channel region C is removed, while leaving the underlying Euro-28-this paper size applies to the Chinese National Standard (CNS ) A4 specification (210X297 mm) A7 B7 5. Description of the invention (26) Contact pattern 57. As described above, the wet after-etching and dry I-etching can be used alternately, or only dry etching can be used. In the latter case, only one type of etching can be used while simplifying the relevant processing steps, but it is difficult to find the correct etching conditions. Conversely, in the former case, it is easy to find the correct etching conditions, but the related processing steps are more complicated. At the same time, annealing can be performed at a temperature of 250-500 c to increase the adhesion between the bottom layers of the data line combination. This type of annealing process can be performed directly after the deposition of the data line assembly conductive layer, or after the completion of the data line assembly. In the case of annealing, the HF treatment process can be omitted. After the data line assembly is completed, as shown in FIGS. 30A and 30B, silicon nitride or an organic insulating material is deposited on the substrate 10, thereby forming a protective layer 70. Next, the protection layer 70 is etched using a photomask and the gate insulation layer 30, thereby forming contact holes 72, 74, 76, and 78, respectively, exposing the storage capacitor conductive pattern 64, gate fill 24, drain 66, and Information fill 68. Finally, as shown in FIGS. 21 to 24, a layer having a thickness of 400-5 00 A with ιζο or IT0 as a main component is deposited on the substrate 10, and a photomask is used to form a pixel electrode 8 2. An auxiliary gate Fill it with $ 4 and supplementary stuff with 8. The pixel electrode 82 is connected to the drain 66 and the storage capacitor conductive pattern 64. The auxiliary gate and data fill 84 and 88 are connected to the gate and data fill 24 and 68, respectively. The data line combination and the underlying ohmic contact patterns 55, 56, and 58 and the semiconductor patterns 42 and 48 can be constructed using only a photomask. In this process, the source $ and Wuji 65 and 66 are separated from each other, while simplifying the relevant processing steps. As mentioned above, before the deposition of conductive material, the glass substrate was subjected to oxygen power -29- This paper size applies Chinese National Standard (CNS) A4 specifications (210X297 mm) 502382 A7 V. Description of the invention (27) " " — One-Table processing or Sun's silicon-based layer undergoes 1117 processing. Furthermore, the conductor layer mainly composed of a silver alloy is deposited on the layer mainly composed of silicon and annealed. In this way, the adhesion between a film mainly composed of silver and a silver alloy and a glass substrate or a layer mainly composed of silicon can be enhanced. Furthermore, signal delays can be minimized while producing a wide-screen and high-resolution LCD display. The present invention has been described in detail with reference to a number of preferred embodiments. Experts in the industry will understand that there are different modifications and alternatives to the present invention without departing from the spirit and scope mentioned in the scope of the patent application of the present invention. ____ · 30- The paper size is suitable for wealth _ home fresh (_ Μ specifications (⑽χ tear public love)

Claims (1)

Amendment of the scope of patent application No. P8 (June 91) A8 B8 C8 D8 Application scope of patent application1. A type of wiring for the display device as a gate line for transmitting scanning signals or a data for transmitting data signals Wire, the wiring includes a thin film deposited on the broken or glass substrate, the thin film is composed of silver or a silver alloy 2. The wiring as described in the first item of the patent application, wherein the silver alloy is the main content. 物 银 （ Ag) and alloy content conductive material 〇〇1-2〇at〇niic% 'The alloy content includes one or more conductive material components selected from the group: Mg, Ca, Th, Zi *, Co, Ni, Ti, V, Nb, Mo, Ta, W, and Cr〇3. As for the wiring in the scope of the patent application, the silver alloy is composed of the main content silver (Ag) and the alloy content conductive material 〇〇1_2 〇atomic% 'This alloy content includes one or more conductive materials selected from the group consisting of Pd, Cu, Mg, Al, Li, Pu, Np, Ce, Eu, Pr, Ca, La, Nb , Nd and Sm. 4. A method of manufacturing a wiring assembly for a display device, the method comprising the steps of: performing an oxygen plasma treatment on a substrate; depositing a thin film containing silver or a silver alloy as a main component on the substrate; and The film is patterned. 5. The method according to item 4 of the patent application, wherein the deposition of the thin film containing the silver alloy as the main component is performed by sputtering, and the silver alloy is composed of a main content silver (Ag) and an alloy content conductive material. 〇〇1-2 〇at〇mic%, the alloy content includes one or more conductive material components selected from the group Gutter 502382 A8 B8 C8 D8 Patent application scope: pd, Cn, Mg, Al ·, Li, Pu, NP, Ce, Eu, ρΓ, Ca, La, Nb, Nd, and Sm The method further includes the step of annealing the film. 7. The method according to item 6 of the patent application, wherein the annealing is performed under a vacuum, nitrogen, hydrogen or hydrogen environment at a temperature of 250-500 ° C for 30-120 minutes. 8. The method of claim 4 in the patent application scope, wherein the substrate is made of glass. 9. The method according to item 4 of the patent application, wherein the oxygen plasma treatment is performed under a pressure of 1 to 100 Dow for 0.5 to 30 minutes, while oxygen is sprayed at sccm. 10. A method for manufacturing a wiring assembly for a display device, the method comprising the steps of: processing a silicon substrate with HF; depositing a thin film containing silver alloy as a main component on the silicon substrate; and forming a pattern of the thin film . 11. The method of claiming item 10 of the patent scope, wherein the hf treatment of the silicon substrate is by immersing the broken substrate into an HF solution, wherein the HF raw material is in a ratio of 1/5 0-1/2 0 0 0. Dilute in extremely pure water. 12. The method according to item 10 of the patent application, wherein the deposition of a thin film containing a silver alloy as a main component is performed by sputtering, and the silver alloy is composed of a main content silver (Ag) and an alloy content conductive material 〇〇1_2〇at 〇mic%, the alloy content includes one or more conductive materials selected from the following groups The paper size applies Chinese National Standard (CNS) A4 specifications (210X ^^ Jy m binding line A8 B8 _ C8 --- --- _D8 ^ VI. Scope of patent application: Mg, Ca, Th, Zr ·, Co, Ni, Ti, v, Nb, M〇, Ta, W, and Cr 〇13 · As the method of patent application No. 10 , Further comprising the step of annealing the film. 14. The method according to item 13 of the scope of patent application, wherein the annealing is performed under a vacuum, chlorine, or nitrogen environment at a temperature of 250-50 (rc) for 30-20 °. Min. • A method for gas-making a thin-film transistor array substrate, the method includes the following steps: performing an oxygen plasma treatment on the substrate; depositing a thin film on the substrate, the thin film consisting of silver or a silver alloy; Forming a pattern to form a gate line group The gate line assembly includes a gate line and a gate electrode; a gate insulating layer is deposited on the substrate; a semiconductor layer mainly composed of undoped amorphous silicon is formed on the gate insulating layer; and the semiconductor layer is formed on the gate insulating layer; A data line combination is formed, which includes a data line, a source electrode, and a non-polar electrode. 16. As described in the method of claim 5, the method of depositing a thin film with silver alloy as the main component is performed by sputtering. The silver alloy is composed of the main content silver (Ag) and the alloy content conductive material 〇〇1-2〇at〇mic%, the alloy content includes one or more conductive material components selected from the group: Pd, Cu, Mg, Al, Li, pu, Np, Ce, Eu, pr, Ca, La, Nb, Nd, and Sm 〇 * 3-This paper size applies to China National Standard (CNS) A4 specifications (210 X297¾) A8 B8 17. The steps of the method according to claim 16, Ai includes annealed M thin film team such as: "The method of the 17th scope of benefit", wherein the annealing step is performed for 307 minutes under the conditions of direct air lice or lice% and temperature of 25 ° C. 19 ·: Apply for a patent The method of the scope item 15, wherein the oxygen plasma treatment is performed for 5 to 3 G minutes under the pressure of i-loo. The oxygen is produced by Lmcc at the same time. The step includes the following steps: depositing a protective layer so that the protective layer covers the semiconductor layer; and forming a pixel electrode so that the pixel electrode is connected to the drain electrode. 21. The method according to item 20 of the patent application, wherein The pixel electrode is made of a transparent conductive material. 22. The method of claim 21, wherein the gate line combination further includes a gate fill connected to the gate line, and the data line combination further includes a connection to the data. The method further includes the following steps: opening the auxiliary gate filling connected to the gate filling, and the auxiliary data filling connected to the data filling. The method further includes the step of forming an ohmic contact layer between the semiconductor layer and the data line combination. 24. The method according to item 23 of the patent application, wherein the data line combination, the ohmic contact layer, and the semiconductor layer simultaneously transmit light 25. The method according to item 15 of the scope of patent application, wherein the substrate is made of glass, and the paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) Gutter 502382 A8 B8 C8 Patent application scope. ^ 26 · —A method for manufacturing a thin film transistor array substrate, the method includes the following steps: depositing a layer with a conductive material as a main component on a substrate, and patterning a layer with a ▲ X conductive material as a main component, This forms a gate-wire combination that includes a gate wire and a gate electrode; deposits a gate insulating layer on the substrate; forms a semiconductor layer on the gate insulating layer; processes the semiconductor layer with HF; Depositing a thin film containing silver alloy as a main component on the semiconductor layer; and patterning the thin film to form a data line combination, the data line combination including a data line, a source, and a drain. 27 · A method for manufacturing a thin film transistor array substrate, the method comprising the steps of: depositing a layer having a conductive material as a main component on a substrate, and patterning the layer including the conductive material as a main component; A gate line combination is formed by the gate line combination. The gate line combination includes a gate line and a gate electrode: a gate insulating layer is deposited on the substrate; and a semiconductor layer mainly composed of undoped amorphous silicon is formed on the gate insulating layer. ; Depositing a thin film on the semiconductor layer, the thin film being composed of a silver alloy; strengthening the adhesion between the semiconductor layer and the thin film by annealing; and S g family (CNS) A4 for I paper rulers Specifications (⑽X 297 mm) ---------- 502382 A8 B8 C8 ________ D8 6. The scope of the patent application forms a pattern on the film to form a data line combination. The data line combination includes data lines, Source and drain. 28. The method according to item 26 of the patent application, wherein the deposition of a thin film containing a silver alloy as a main component is performed by sputtering, and the silver alloy is composed of a main content silver (Ag) and an alloy content conductive material 〇01_20 at〇mic %. The alloy content includes one or more conductive material components selected from the group: Mg, Ca, Th, Zr, Co, Ni, Ti, V, Nb, Mo, Ta, W, and Cr o 29 The method of claim 26, further comprising an annealing step after the thin film is deposited. 30. The method of claim 29, wherein the annealing step is performed at a temperature of 250-500 ° C. 31. The method of claim 26, further comprising the steps of: depositing a protective layer so that the protective layer covers the semiconductor layer; and forming a pixel electrode such that the pixel electrode is connected to the drain electrode. 32. The method of claim 3 in the scope of patent application, wherein the pixel electrode is made of a transparent conductive material. 33. The method of claim 32, wherein the gate line combination further includes a gate fill connected to the gate line, and the data line combination further includes a data fill connected to the data line, and the method further includes forming a connection The steps of the auxiliary gate filling to the gate filling and the auxiliary filling connected to the data filling. For example, the method according to item 26 of the patent application range, wherein the semiconductor layer is composed of chips. Winter home fresh (referred to) A4 size _X297 mm) 35 =: The method according to item 34, wherein the semiconductor layer includes a lower layer containing :: amorphous fragment as a main component, and an upper layer containing doped amorphous material as a main component. 36. The method of claim 35, wherein the combination of the data line, the layer containing the amorphous amorphous particles as the main component, and the layer containing the non-crystalline amorphous dream as the main component are simultaneously processed by photolithography. Made up. · 37 · Thin film transistor array substrates, including:-a gate line assembly, shaped on a glass substrate, the gate line assembly includes a gate line and a gate electrode connected to the gate line; a gate insulation layer covering the gate Line combination; a semiconductor pattern formed on the gate insulation layer; and a shell line combination formed on the gate insulation layer and the semiconductor pattern. The data line combination includes a data line and is connected to the data line and is located close to the gate. The source of the electrode and the drain positioned relative to the source near the gate electrode; wherein the gate or data line combination is composed of silver or a silver alloy. 38. The thin-film transistor array substrate according to item 37 of the application, wherein the silver alloy is composed of silver (Ag) as the main content and 〇1-20 atomic% of the alloy content, and the alloy content Includes one or more conductive material components selected from the group consisting of Pd, Cu, Mg, Al, Li, pu, Np, Ce, Eu, Pr, Ca, La, Nb, Nd, and Sm. 39. The thin film transistor array substrate according to item 37 of the patent application, wherein the silver alloy is composed of silver (Ag) as the main content and conductive material with an alloy content of 0.01-20 atomic%, and the alloy content includes One or more options Patent application Composition of conductive materials from the following groups: Mg, Ca, Th, Zr, c. , H v, Nb, Mo, Ta, Cr. 40. The thin film transistor array substrate according to item 37 of the patent application scope, further comprising a protective layer covering the semiconductor pattern. For example, the thin film electric: body array substrate of the scope of application for patent No. 40, further includes a pixel electrode formed on the protective layer, the pixel electrode being made of a transparent conductive material. 42. The thin film transistor array substrate according to the scope of the patent application, wherein the combination of the nuclear gate line includes the gate filling connected to the gate line so as to receive the liver number from the outside, and the step of the data combination is connected to The data line is used for data filling for receiving data signals from the outside, and the thin film transistor array substrate further includes an auxiliary gate and data filling on the same plane as the pixel electrode. The auxiliary gate and data gate are electrically connected to the gate. And data filling. 43. The thin film transistor array substrate according to item 37 of the application, further comprising an ohmic contact pattern t formed between the material conductor pattern and the data line combination, and the ohmic contact pattern is doped with a high concentration of impurities. 44. The thin film transistor array substrate according to item 43 of the patent application scope, wherein the semiconductor pattern 'has the same appearance as the data line combination except for the through area. 45. The method according to item 27 of the patent application, wherein the deposition using a silver alloy as the main damage film is performed by sputtering, and the silver alloy is composed of a main content silver (Ag) and an alloy content conductive material 〇〇1_2. The content of the alloy consists of one or more conductive materials selected from the following groups: -8-This paper size applies Chinese National Standard (CNS) A4 specifications (210X297 public love) 502382 A8 B8 C8 D8 Six Scope of patent application: Mg, Ca, Th, zr., Co, Ni, Ti, V, Nb, Mo, Ta, W, and Cr 〇46. If the method of the scope of patent application No. 27 is further included in the film The annealing step after deposition. 47. The method of claim 46, wherein the annealing step is performed at a temperature of 250-500C. 48. The method of claim 27, further comprising the steps of: depositing a protective layer so that the protective layer covers the semiconductor layer; and forming a pixel electrode such that the pixel electrode is connected to the drain. 49. The method of claim 48, wherein the pixel electrode is made of a transparent conductive material. Order 50. The method of claim 49, wherein the gate line combination further includes a gate fill connected to the gate line, and the data line combination further includes data fill connected to the data line, and the method further includes forming Steps for auxiliary gate filling connected to the gate filling and auxiliary data filling connected to the data filling 骡 51. The method according to claim 27, wherein the semiconductor layer is composed of silicon. '52. The method of claim 51, wherein the semiconductor layer includes a lower layer mainly composed of undoped amorphous silicon and an upper layer mainly composed of doped amorphous silicon. 53. The method according to item 5 of the patent application range, wherein the data line combination, the layer doped with amorphous silicon as a main component, and the layer doped with non-doped amorphous silicon as a main component are simultaneously subjected to photolithography form. -9 -