TW502382B - A wiring and a method for manufacturing the wiring, and a thin film transistor array panel including the wiring and method for manufacturing the same - Google Patents
A wiring and a method for manufacturing the wiring, and a thin film transistor array panel including the wiring and method for manufacturing the same Download PDFInfo
- Publication number
- TW502382B TW502382B TW090113508A TW90113508A TW502382B TW 502382 B TW502382 B TW 502382B TW 090113508 A TW090113508 A TW 090113508A TW 90113508 A TW90113508 A TW 90113508A TW 502382 B TW502382 B TW 502382B
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- Taiwan
- Prior art keywords
- gate
- thin film
- layer
- substrate
- silver
- Prior art date
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 116
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims description 78
- 239000000758 substrate Substances 0.000 claims abstract description 199
- 239000010410 layer Substances 0.000 claims abstract description 156
- 229910001316 Ag alloy Inorganic materials 0.000 claims abstract description 82
- 239000004065 semiconductor Substances 0.000 claims abstract description 64
- 239000011521 glass Substances 0.000 claims abstract description 51
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 47
- 229910052709 silver Inorganic materials 0.000 claims abstract description 47
- 239000004332 silver Substances 0.000 claims abstract description 47
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 29
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- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims 1
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- 239000011368 organic material Substances 0.000 abstract description 4
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 abstract description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 abstract description 2
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- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
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- 229910052702 rhenium Inorganic materials 0.000 description 2
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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- KJZYNXUDTRRSPN-UHFFFAOYSA-N holmium atom Chemical compound [Ho] KJZYNXUDTRRSPN-UHFFFAOYSA-N 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
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- TVMXDCGIABBOFY-UHFFFAOYSA-N octane Chemical compound CCCCCCCC TVMXDCGIABBOFY-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13458—Terminal pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
502382 A7 B7 五、發明説明(1 ) I明背景 (a) 發明領域 本發明涉及一種接線組合和製造該接線組合的方法,以 及一種具有該接線組合的薄膜電晶體陣列基板和製造該基 板的方法。 (b) 相關技藝説明 整體而言,半導體裝置或顯示裝置的接線都用於信號傳 輸,因此要使這類接線避免信號延遲就變得相當重要。 因此’這類接線必須利用低阻抗的傳導材料來加以製造 。例如,銀(Ag)就可用於這類傳導材料。但是,假使將銀 或銀合金應用於這種用途會有一個缺點,就是所產生的接 線相對於底層的基板或薄膜的附著力較差。甚至,接線很 容易會從基板或薄膜上脱落。 發明概要 本發明的目的是要提供一種薄膜電晶體陣列基板,其接 線組合具有低阻抗和良好的附著力。 具備下列功说且具有接線組合的薄膜電晶體陣列基板, 還可達成其他目的。 · 一玻璃基板,在沈積以銀或銀合金爲主要成份的沈積層 之前,先經過氧電漿處理。假使基板由矽組成則經過hf^ 理,並在沈積以銀或—銀合金爲主要成份沈積層之後,對其 進行退火處理。 根據本發明觀點製造用於顯示裝置的接線組合的方法中 ,一玻璃基板經過氧電漿處理。一以銀或銀合金爲主要成 -4 - 502382 A7 --- -,_ B7_ __ 五、(2 ) ' —'〜^- 份的薄膜沈積在該基板上,並形成圖案。 沈積以銀合金爲主要成份的薄膜時可利用濺射方式進行 。該銀合金可由主要内容物銀(Ag)和合金内容物傳導材料 0.01-20 at〇miC0/0所組成。合金内容物具有一或多種選自以 下的傳導材料成份:Pd、Cu、Mg、A卜Li、Pu、Np、以 Eu、Pr、Ca、La、Nb、Nd、或Sm。具有以銀合金爲主 要成份薄膜的基板可進一步經過退火處理。 根據本發明另一觀點製造用於顯示裝置的接線組合的方 法中,一矽基板經過HF處理。一以銀合金爲主要成份的薄 膜沈積在該矽基板上,並形成圖案。 沈積以銀合金爲主要成份的薄膜時可利用濺射方式進行 。該銀合金可由主要内容物銀(Ag)和合金内容物傳導材料 0·01-20 atomic%所組成。合金内容物具有一或多種選自以 下的傳導材料成份:Mg、Ca、Th、Zr、Co、Ni、Ti、v、502382 A7 B7 V. Description of the invention (1) Background of the invention (a) Field of the invention The present invention relates to a wiring assembly and a method for manufacturing the wiring assembly, and a thin film transistor array substrate having the wiring assembly and a method for manufacturing the substrate. . (b) Relevant technical description In general, the wiring of semiconductor devices or display devices is used for signal transmission, so it is very important to avoid signal delay in such wiring. Therefore, this type of wiring must be manufactured using low-impedance conductive materials. For example, silver (Ag) can be used for this type of conductive material. However, if silver or a silver alloy is used for this purpose, there is a disadvantage that the resulting wire has poor adhesion to the underlying substrate or film. Furthermore, the wiring can easily come off the substrate or film. SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor array substrate having a wiring assembly having low impedance and good adhesion. A thin film transistor array substrate having the following functions and having a wiring combination can also achieve other purposes. · A glass substrate is treated with oxygen plasma before depositing a deposited layer containing silver or silver alloy as the main component. If the substrate is made of silicon, it is subjected to hf ^ treatment, and an annealed layer is deposited after depositing the layer with silver or -silver alloy as the main component. In the method for manufacturing a wiring assembly for a display device according to the aspect of the present invention, a glass substrate is subjected to an oxygen plasma treatment. One is mainly composed of silver or silver alloy -4-502382 A7 ----, _ B7_ __ Five, (2) '—' ~ ^-parts of the thin film are deposited on the substrate and form a pattern. When depositing a thin film containing silver alloy as the main component, sputtering can be used. The silver alloy can be composed of silver (Ag) as the main content and a conductive material with an alloy content of 0.01-20 at 0 miC0 / 0. The alloy contents have one or more conductive material components selected from the group consisting of Pd, Cu, Mg, Al, Li, Pu, Np, Eu, Pr, Ca, La, Nb, Nd, or Sm. The substrate having a thin film mainly composed of a silver alloy may be further annealed. In the method for manufacturing a wiring assembly for a display device according to another aspect of the present invention, a silicon substrate is subjected to HF processing. A thin film mainly composed of a silver alloy is deposited on the silicon substrate and formed into a pattern. When depositing a thin film containing silver alloy as the main component, sputtering can be used. The silver alloy can be composed of silver (Ag) as the main content and 0.01-20 atomic% of the alloy content conductive material. The alloy content has one or more conductive material components selected from: Mg, Ca, Th, Zr, Co, Ni, Ti, v,
Nb、Mo、Ta、w、或以。具有以銀合金爲主要成份薄膜的 矽基板可進一步由退火處理。退火過程可在25〇_5〇〇τ溫 下進行。 根據本發明另一觀點製造薄膜電晶體陣列基板的方法中 ,一基板經過氧電漿處理。以銀或銀合金爲主要成份的薄 膜沈積在該基板上並形成圖案,藉此形成一閘線組合。該 閘線組合包括閘線和·閘電極。一閘絕緣層沈積在該基板上 ,且一以非摻雜非晶矽爲主要成份的半導體層在閘絕緣層 上形成。一資料線組合在該半導體層上形成。_資料線組 合包括資料線、源極和汲極。Nb, Mo, Ta, w, or A silicon substrate having a thin film mainly composed of a silver alloy can be further annealed. The annealing process can be performed at a temperature of 25-50 τ. In the method for manufacturing a thin film transistor array substrate according to another aspect of the present invention, a substrate is subjected to an oxygen plasma treatment. A thin film mainly composed of silver or a silver alloy is deposited on the substrate and formed into a pattern, thereby forming a gate line assembly. The gate line combination includes a gate line and a gate electrode. A gate insulating layer is deposited on the substrate, and a semiconductor layer mainly composed of undoped amorphous silicon is formed on the gate insulating layer. A data line combination is formed on the semiconductor layer. _Data line combination includes data line, source and drain.
發明説明( 此積以銀合金爲主要成份的薄膜時可利用濺射方式進行 °孩銀合金可由主要内容物銀(Ag)和合金内容物傳導材料 atomic%所組成。合金内容物具有一或多項選自以 下的傳導材料成份:Pd、Cu、Mg、Al、Li、Pu、Np、Ce 、p u、Pr、Ca、La、Mb、Nd、或Sm。該以銀合金爲主要 成份的薄膜可經過退火處理。該基板可由玻璃構成。. 根據本發明另一觀點製造薄膜電晶體陣列基板的方法中 安以傳導材料爲主要成份的層沈積在一基板上並形成圖 案,藉此形成一閘線組合。該閘線組合包括閘線和閘電極 一閘絕緣層沈積在該基板上,且一半導體層在該閘絕緣 層上形成。該半導體層經過HF處理。以銀合金爲主要成份 的薄膜沈積在該半導體層上並形成圖案,藉此形成一資料 線組合。該資料線組合包括資料線、源極和汲極。 退火過程可用於以銀合金爲主要成份的薄膜,以強化薄 膜與底層半導體層之間的附著力。纟這種情況τ,施加於 半導體層的HF處理可加以省略。 沈積以銀合金爲主要成份的薄膜時可利用濺射方式進行 。該銀合金可由主要内容物銀(Ag)和合金内容物傳導材料 0.01-20 at〇mic〇/〇所組成。合金内容物具有一或多項選自以 下的傳導材料成份:Mg、Ca、Th、Zr、Co、Ni、Ή、v、DESCRIPTION OF THE INVENTION (This thin film containing silver alloy as the main component can be sputtered. The silver alloy can be composed of the main content silver (Ag) and the alloy content conductive material atomic%. The alloy content has one or more A component selected from the following conductive materials: Pd, Cu, Mg, Al, Li, Pu, Np, Ce, pu, Pr, Ca, La, Mb, Nd, or Sm. The thin film mainly composed of silver alloy can be passed through Annealing. The substrate may be made of glass. In a method of manufacturing a thin film transistor array substrate according to another aspect of the present invention, a layer having a conductive material as a main component is deposited on a substrate and patterned, thereby forming a gate line assembly. The gate line combination includes a gate line and a gate electrode, and a gate insulating layer is deposited on the substrate, and a semiconductor layer is formed on the gate insulating layer. The semiconductor layer is processed by HF. A thin film mainly composed of a silver alloy is deposited on the substrate. A pattern is formed on the semiconductor layer to form a data line combination. The data line combination includes a data line, a source electrode, and a drain electrode. The annealing process can be used for films containing silver alloy as the main component. In order to strengthen the adhesion between the thin film and the underlying semiconductor layer. Τ In this case, the HF treatment applied to the semiconductor layer can be omitted. The thin film containing a silver alloy as a main component can be deposited by sputtering. The silver alloy It can be composed of the main content silver (Ag) and the alloy content conductive material 0.01-20 at 0mic 0 / 〇. The alloy content has one or more conductive material components selected from the following: Mg, Ca, Th, Zr, Co , Ni, Ή, v,
Nb、M〇、Ta、W、或具有以銀合金爲主要成份薄膜的 石夕基板可另外經過退火處理》退火過程可在25〇_5〇〇1溫度 下進行。 /皿又Nb, M0, Ta, W, or Shi Xi substrates with a thin film containing silver alloy as the main component may be additionally annealed. The annealing process may be performed at a temperature of 250-1005. / Dish again
裝 訂Binding
一保護層可覆蓋該半導體層 且像素電極可連接至該汲A protective layer may cover the semiconductor layer and a pixel electrode may be connected to the drain.
502382 五、發明説明(4 ) 極。該像素電極可利用透明的傳導材料所構成。 該閘線組合另可包括連接至閘線的閘填充,且該資料線 組合可另外包括連接至該資料線的資料填充。連接至該閉 和資料填充的輔助閘和資料填充,可與像素電極在同一乎 面上形成。 該半導體層可由非㈣的非晶碎爲主要成份的下層以及 有摻雜的非晶矽爲主要成份的上層所構成。 咸;貝料、泉、’且a、非摻雜非晶矽爲主要成份的沈積雇、以 及摻雜非晶石夕爲主要成份的沈積層,可同時由光刻法形成 邏式簡單説明 I曰由參考以下詳細説明能夠對本發明有更完整的瞭解, 且本發明的許多相關優點會更加明顯,另外還提供附圖, 其中的參考符號代表相同或類似的元件,其中: 圖1是沈積在玻璃基板上接線組合的薄膜側視圖; Θ 2A至2E疋沈積在玻璃基板上以銀爲主要成份的薄膜 fe片,照片中有呈現薄膜和玻璃基板間的附著狀態; 圖3爲説明圖2A至2E中薄膜和玻璃基板間附著力的圖表 圖4A至4E是沈積在玻璃基板上、以兩種來源極銀合金爲 主要成伤的薄膜照片,照片中有呈現薄膜和玻璃基板間的 附著狀態; 圖5爲説明圖4A至4E中薄膜和玻璃基板間附著力的圖表 ____ -7- 本紙張尺度適W國國家標準(CNS) Μ規格(21〇X297公愛) 五、發明説明(5 ) 圖6A至6E疋沈積在玻璃基板上、以三種來源極銀合金爲 主要成伤的薄膜照片’照片中有呈現薄膜和玻璃基板間的 附著狀態; 圖7爲说明圖6A至6E中薄膜和玻璃基板間附著力的圖表 圖8A至8D是沈積在玻璃基板上以主要成份的薄 膜照片,照片中有呈現薄膜和玻璃基板間的附著狀態; 圖9爲説明圖8A至8D中薄膜和玻璃基板間附著力的圖表 圖10A至10D是沈積在玻璃基板上、以AgTi爲主要成份的 薄膜照片,照片中有呈現薄膜和玻璃基板間的附著狀態; 圖11爲説明圖10A至10D中薄膜和破璃基板間附著力的 圖表; 圖12和13爲説明在經HF處理過的基板上和未經處理基 板上沈積以AgMg爲主要成份的薄膜和以AgTi爲主要成份 的薄膜,其電阻係數與退火溫度間關係的變化圖; 圖14爲説明以矽爲主要成份的合金之熔點溫度與根據熔 點溫度的知含量(enthalpy)的座標圖; 圖15爲根據本發明第一較佳具體實施例的液晶顯示的薄 膜電晶體陣列基板之平面圖; 圖16爲沿著圖— 線所切割出的薄膜電晶體陣 列基板之側視圖; 圖17A、18A、19A和20A依序說明製造如圖15所示的薄 膜電晶體陣列基板的步驟; 一 _ _ 8 - 本紙張尺度適用巾g g家標準(CNS) Μ規格(⑽㈣了公爱) 502382 A7 __ B7 五、發明説明(6 ) 圖17B爲沿著圖17A的XVIIb-XVIIb’線所切割出的薄膜電 晶體陣列基板之側視圖; 圖18B爲沿著圖18A的XVIIIb-XVIIIb%^所切割出的薄膜 電晶體陣列基板之側視圖; 圖1 9B爲沿著圖19 A的XlXb-XIXb’線所切割出的薄膜電 晶體陣列基板之側視圖; 圖20B爲沿著圖20A的XXb-XXb*線所切割出的薄膜電晶 體陣列基板之側視圖; 圖2 1爲根據本發明第二較佳具體實施例的液晶顯示的薄 膜電晶體基板平面圖; 圖22和23爲分別沿著圖21的ΧΧΙΙ-ΧΧΙΓ線和 ΧΧΙΙΙ-ΧΧΙΙΓ線所切割出如圖21所示的薄膜電晶體陣列基 板之側視圖; 圖24A説明製造如圖2 1所示之薄膜電晶體陣列基板的第 一步驟; 圖24B和24C爲分別沿著圖24A的XXIVb_XXIVbf線和 XXIVc-XXIVc1線所切割出的薄膜電晶體陣歹|J基板之側視 _ , . 圖25A和2 5B説明分別依照圖24B和24C、製造如圖21所示 的薄膜電晶體陣列基板的步驟; 圖26A説明依照圖25A和25B、製造如圖21所示之薄膜電 晶體陣列基板的步驟; 圖26B和26C爲分別沿著圖26A的XXVIb-XXVIb1線和 XXVIc-XXVIc1線所切割出的薄膜電晶體陣列基板之側視 -9- 本纸張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 502382502382 V. Description of the invention (4) pole. The pixel electrode may be made of a transparent conductive material. The gate line combination may further include a gate fill connected to the gate line, and the data line combination may further include a data fill connected to the data line. The auxiliary gate and data fill connected to the closed and data fill can be formed on the same plane as the pixel electrode. The semiconductor layer may be composed of a lower layer containing non-rhenium amorphous particles as a main component and an upper layer containing doped amorphous silicon as a main component. Salty; shell material, spring, 'and a, non-doped amorphous silicon as the main component of the deposition, and doped amorphous stone as the main component of the deposition layer, can be formed by photolithography logic simple instructions I That is, a more complete understanding of the present invention can be obtained by referring to the following detailed description, and many related advantages of the present invention will be more obvious. In addition, the accompanying drawings are provided, wherein the reference symbols represent the same or similar elements, wherein: Side view of the thin film of the wiring assembly on the glass substrate; Θ 2A to 2E 疋 Films with a silver film as the main component deposited on the glass substrate. The photo shows the state of adhesion between the film and the glass substrate; Figure 3 is an illustration of Figure 2A to Chart of adhesion between thin film and glass substrate in 2E. Figures 4A to 4E are photos of thin films deposited on glass substrates with two sources of extremely silver alloys as the main damage. The photos show the state of adhesion between thin film and glass substrate; Figure 5 is a graph illustrating the adhesion between the film and the glass substrate in Figures 4A to 4E ____ -7- This paper is compliant with National Standards (CNS) M specifications (21 × 297 public love) V. Description of the invention (5) Figure 6 A to 6E: Films deposited on glass substrates with three sources of extremely silver alloys as the main cause of damage. 'Photos show the state of adhesion between the film and the glass substrate. Graphs of adhesion between Figures 8A to 8D are photos of the main components of the film deposited on the glass substrate. The photos show the state of adhesion between the film and the glass substrate. Figure 9 illustrates the adhesion between the film and the glass substrate in FIGS. Figures 10A to 10D are photographs of films deposited on glass substrates with AgTi as the main component. The photos show the state of adhesion between the film and the glass substrate. Figure 11 illustrates the films and the broken glass substrate in Figures 10A to 10D. Graphs of adhesion between graphs; Figures 12 and 13 illustrate the deposition of AgMg-based films and AgTi-based films on HF-treated and untreated substrates. FIG. 14 is a graph illustrating a melting point temperature of an alloy containing silicon as a main component and an enthalpy content based on the melting point temperature; FIG. 15 is a graph showing A plan view of a thin film transistor array substrate for a liquid crystal display of a preferred embodiment; FIG. 16 is a side view of the thin film transistor array substrate cut along the line of FIG .; FIG. The steps of the thin film transistor array substrate shown in Fig. 15; _ _ 8-This paper size is applicable to the GG family standard (CNS) M specification (for public love) 502382 A7 __ B7 V. Description of the invention (6) 17B is a side view of the thin film transistor array substrate cut along the XVIIb-XVIIb 'line of FIG. 17A; FIG. 18B is a side view of the thin film transistor array substrate cut along XVIIIb-XVIIIb% ^ of FIG. 18A Figure 19B is a side view of the thin film transistor array substrate cut along the XlXb-XIXb 'line of Figure 19A; Figure 20B is a thin film transistor array cut along the XXb-XXb * line of Figure 20A A side view of the substrate; FIG. 21 is a plan view of a thin film transistor substrate for a liquid crystal display according to a second preferred embodiment of the present invention; and FIGS. 22 and 23 are respectively taken along lines XXIII-XXII and XXIII-XXII Cut out the thin as shown in Figure 21 A side view of the transistor array substrate; FIG. 24A illustrates the first step of manufacturing the thin film transistor array substrate shown in FIG. 21; FIGS. 24B and 24C are cut along the lines XXIVb_XXIVbf and XXIVc-XXIVc1 of FIG. 24A, respectively. 25A and 25B illustrate the steps of manufacturing the thin-film transistor array substrate shown in FIG. 21 in accordance with FIGS. 24B and 24C, respectively; FIG. 26A illustrates the steps in accordance with FIGS. 25A and 25B. 25B. The steps of manufacturing the thin film transistor array substrate shown in FIG. 21; FIGS. 26B and 26C are side views of the thin film transistor array substrate cut along the XXVIb-XXVIb1 line and XXVIc-XXVIc1 line of FIG. 26A, respectively- 9- This paper size applies to China National Standard (CNS) A4 (210X297 mm) 502382
月汐曰 〇8號專利申請案 正頁(91年6月) A7 B7 五、發明説明(7 ) IS2 · _ , 圖27A/B,圖28A/B及圖29A/B說明分別依照圖26B和26C 、製造如圖2 1所示的薄膜電晶體陣列基板的步騾; 圖30A說明依照圖29A和29B、製造如圖21所示之薄膜電 晶體陣列基板的步驟;以及 圖30B和30C為分別沿著圖30A的XXXb-XXXb*線和 XXXc-XXXc:線所切割出的薄膜電晶體陣列基板之側視圖。 較佳具體實施例之詳細說明 將參考附圖來解釋本發明的較佳具體實施例。 圖1為沈積在玻璃或矽基板上的薄膜侧視圖。 為製造用於半導體裝置或顯示裝置的接線組合,如圖1 所示,具有較低阻抗例如銀和銀合金的傳導材料為主的薄 膜200,沈積在基板100上,並利用光刻法形成圖案。在使 用以銀合金為主要成份的薄膜200的情況時,該薄膜可由主 内容物銀(Ag)和合金内容物傳導材料0.01-20 atomic%或以 下所組成。合金内容物具有一或兩項選自以下的傳導材料 成份:Pd、Cu、Mg、Al、Li、Pu、Np、Ce、Eu、Pr、Ca 、La、Nb、Nd、或Sm。也就是兩或三種來源極的銀合金可 ,用於該薄膜200。 由於以銀或銀合金為主要成份的薄膜200,相對於底層基 板100,其附著性較差,因此必須加強薄膜200和基板100 間的附著力。在使用半導體裝置或用於液晶顯示的薄膜電 晶體陣列基板的情況時,這種附著力應達到20牛頓(N)以上 -10- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 502382 A7 ____B7 五、發明説明(8 ) 爲此’在使用玻璃基板的情況時,該基板在沈積以銀或 銀合金爲主要成份的傳導層之前,可經過氧電漿處理,或 在沈積傳導層之後,進行退火過程。氧電漿處理最好是在 壓力1-100陶爾之下進行〇5_3〇分鐘,同時以1-1〇〇〇%(^噴 出氧氣。退火過程最好是在眞空、氮、或氫環境下、溫度 250-500°C的條件下進行30_12〇分鐘。在使用矽基板的情沉 時’該基板在沈積以銀或銀合金爲主要成份的傳導層之前 ,可經過HF處理,或在沈積傳導層之後,進行退火過程。 在HF處理中,矽基板1〇〇會浸在HF溶液中。HF溶液的製備 方式是利用HF原料加上極純的水以1/5〇-1/2〇〇〇比例稀釋 。浸泡時間最好在1-60分鐘之間(假使稀釋濃度爲1/1〇〇時, 更好是在5-1 0分鐘之間)。假使合金内容物係選自耐火金屬 ,則退火過程期間可、在薄膜2〇〇和基板1〇〇間形成一矽化層 。退火過程可在興空、氫、或氮環境下、溫度25〇_5〇〇t下 進4亍3 0 -12 0分鐘。 圖2Α至2Ε爲在玻璃基板上形成以銀爲主要成份的薄膜 照片,其中以銀爲主要成份的薄膜利用刻痕測試器加以刻 劃,藉此呈現附著狀態。圖·3爲説明以銀爲主要成份的薄膜 和玻璃基板間的附著力圖表。在如圖所示的玻璃基板中, 圖2Α和2Β所示的薄膜被未經氧電漿處理的薄膜所覆蓋,且 Α薄膜利用刻痕測试為加以刻劃。如圖2 c至2 Ε所示的玻璃 基板則在150 W、200 W和300 W情況下進行氧電漿處理, 且該薄膜利用刻痕測試器加以刻劃。如圖⑼至2]£所示的破 璃基板由未經氧電漿處理的薄膜所覆蓋,並在3〇〇〇c溫度下 -11 - 502382 A7The front page of the Yuexi No. 08 patent application (June 91) A7 B7 V. Description of the invention (7) IS2 · _, Figure 27A / B, Figure 28A / B and Figure 29A / B The description is based on Figure 26B and 26C. The steps of manufacturing the thin film transistor array substrate shown in FIG. 21; FIG. 30A illustrates the steps of manufacturing the thin film transistor array substrate shown in FIG. 21 according to FIGS. 29A and 29B; and FIGS. 30B and 30C are respectively A side view of the thin film transistor array substrate cut along the lines XXXb-XXXb * and XXXc-XXXc: of FIG. 30A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be explained with reference to the drawings. Figure 1 is a side view of a thin film deposited on a glass or silicon substrate. In order to manufacture a wiring assembly for a semiconductor device or a display device, as shown in FIG. 1, a thin film 200 mainly composed of a conductive material having a low resistance such as silver and a silver alloy is deposited on a substrate 100 and patterned by photolithography. . In the case of the thin film 200 using a silver alloy as a main component, the thin film may be composed of the main content silver (Ag) and the alloy content conductive material at 0.01-20 atomic% or less. The alloy content has one or two conductive material components selected from the group consisting of Pd, Cu, Mg, Al, Li, Pu, Np, Ce, Eu, Pr, Ca, La, Nb, Nd, or Sm. That is, two or three source silver alloys can be used for the thin film 200. Since the film 200 containing silver or a silver alloy as a main component has poor adhesion to the base substrate 100, it is necessary to strengthen the adhesion between the film 200 and the substrate 100. When using a semiconductor device or a thin film transistor array substrate for liquid crystal display, this adhesion should reach more than 20 Newtons (N) -10- This paper size applies to China National Standard (CNS) A4 (210 X 297) (Mm) 502382 A7 ____B7 V. Description of the invention (8) To this end, in the case of using a glass substrate, the substrate may be treated with an oxygen plasma before depositing a conductive layer containing silver or a silver alloy as its main component, or After the conductive layer is deposited, an annealing process is performed. The oxygen plasma treatment is preferably performed under a pressure of 1 to 100 Tao for 5:00 to 30 minutes, and the oxygen is sprayed at 1 to 100% (^). The annealing process is preferably performed in an air, nitrogen, or hydrogen environment. The temperature is 250-500 ° C for 30-12 minutes. When using a silicon substrate, the substrate can be subjected to HF treatment before deposition of a conductive layer containing silver or a silver alloy as the main component, or it can be conducted by deposition. After the layer, an annealing process is performed. In the HF process, the silicon substrate 100 is immersed in the HF solution. The HF solution is prepared by using HF raw materials and extremely pure water at 1 / 5-1 / 2. 〇 Proportional dilution. The soaking time is preferably between 1-60 minutes (assuming that the dilution concentration is 1/1100, more preferably between 5-10 minutes). If the alloy content is selected from refractory metals, During the annealing process, a silicide layer can be formed between the thin film 200 and the substrate 100. The annealing process can be carried out at a temperature of 25-500 t under the conditions of air, hydrogen, or nitrogen at a temperature of 25-500 t. -12 0 minutes. Figures 2A to 2E are photographs of silver-based films formed on glass substrates, with silver as the main component. A part of the film was scored with a scoring tester to show the adhesion state. Fig. 3 is a graph illustrating the adhesion between the film containing silver as the main component and the glass substrate. In the glass substrate shown in the figure, The films shown in 2A and 2B are covered by films not treated with oxygen plasma, and the A film is scored by a notch test. The glass substrates shown in Figures 2c to 2E are at 150 W, 200 Oxygen plasma treatment was performed at W and 300 W, and the film was scored with a scoring tester. As shown in Figures 璃 to 2], the glass-breaking substrate is covered by a film not treated with oxygen plasma, and -11-502382 A7 at 3000 ° C
進行退火處理3 0分鐘。 =建立,銀爲主要成份的薄膜厚度約i μιη。退火過程在 歷力2增陶爾的情況下進行。氧電漿處理在|力⑽以陶 爾的情況下進行,同時噴出氧氣的流速爲13似爪。具有金 剛石尖形頭的刻痕測試器可用來測量附著力。測量時在薄 膜上刻劃,同時逐漸增加施加在刻痕測試器尖形頭的力度 ,約在範圍0_20 N之間。在六個區域拍照。照片中呈現出 來的線條是利用刻痕測試器尖形頭刻劃,且施加的力量從 左至右逐漸增強。 ^ #如圖2八和3所$,以銀爲主要成份的薄膜扇沈積在未經 氧電漿處理的玻璃基板100上。在此狀況下來測量附著力。 結果發現附著力略爲增加,但薄膜200在施力達到7 N時脱 離基板100。 如圖2B和3所示’以銀爲主要成份的薄膜沈積在未經氧電 漿處理的玻璃基板1〇〇上,並經過%。^的退火。在此狀況 下來測量附著力。結果發現附著力略爲增加,但薄膜2〇〇 在施力達到7 N時脱離基板1 〇〇。 如圖2C至2E和3所示,玻璃基板100在15〇 w、2〇〇 ’或3〇〇 w下經過氧電漿處理。以銀爲主要成份的薄膜沈積在基 板1〇〇上,並經過退火處理。在此狀況下來測量附著力。即 使在刻痕測試器尖形頭施加的力量達到2〇 N以上,該薄膜 也沒有從基板100上脱離。接下來,經過氧電漿處理後,相 對於基板100,可增加基板100和薄膜200間的附著力。 圖4A至4E爲在玻璃基板上形成以兩種來源極銀合金爲 主f成,的薄膜照片,其中薄膜利用刻痕測試器加以刻寫 ,藉此王現附著狀態。圖5爲説明以銀合金爲主要成份的薄The annealing process was performed for 30 minutes. = Established, the thickness of the film with silver as the main component is about i μm. The annealing process was performed in the case of Lili 2 Zulter. Oxygen plasma treatment was performed in the case of Lier and Tao, and the flow rate of oxygen was 13 claws. A notch tester with a diamond-tipped tip can be used to measure adhesion. Scratch the film while measuring, while gradually increasing the force applied to the tip of the score tester, which is in the range of 0-20 N. Take pictures in six areas. The lines shown in the photo were scored with a sharp tip of a scoring tester, and the applied force gradually increased from left to right. ^ #As shown in Figures 2 and 3, a thin film fan with silver as the main component is deposited on a glass substrate 100 without oxygen plasma treatment. Measure the adhesion in this condition. As a result, it was found that the adhesion was slightly increased, but the film 200 detached from the substrate 100 when the applied force reached 7 N. As shown in Figs. 2B and 3 ', a thin film containing silver as a main component was deposited on a glass substrate 100 which had not been treated with oxygen plasma, and passed through%. ^ 'S annealing. Measure the adhesion in this condition. As a result, it was found that the adhesion was slightly increased, but the film 200 detached from the substrate 1000 when the force reached 7 N. As shown in FIGS. 2C to 2E and 3, the glass substrate 100 is subjected to an oxygen plasma treatment at 150 w, 2000 ', or 300 w. A thin film containing silver as the main component is deposited on the substrate 100 and annealed. Measure the adhesion in this condition. Even if the force applied to the tip of the nick tester is more than 20 N, the film is not detached from the substrate 100. Next, after the oxygen plasma treatment, the adhesion between the substrate 100 and the thin film 200 can be increased relative to the substrate 100. 4A to 4E are photographs of a thin film formed of two sources of extremely silver alloys on a glass substrate, in which the thin film is engraved with a nick tester, thereby showing a state of adhesion. Fig. 5 illustrates a thin film containing silver alloy as the main component.
裝Hold
502382 A7 ____ B7 五、發明説明(10~) " — 膜和玻璃基板間的附著力圖表。 圖4A至4E的處理狀況與圖2A至2E相同,除了用於該薄膜 的材料,是使用具有主内容物Ag和合金内容物Mg 5 atomic%的兩種來源極銀合金,以及沈積方式是藉由濺射進 行此二條件之外。 如圖4A、4B和5所示,是以未經氧電漿處理、以AgMg爲 主要成份的薄膜200,來覆蓋玻璃基板10〇。當施加在刻痕 測試器尖形頭上的力量約3 N時,薄膜200會脱離基板1〇〇 。也就是説,基板1〇〇和薄膜200間的附著力是相當薄弱。 如圖4C和5所示,在150 W之下經過氧電漿處理的玻璃基 板1〇〇,由以銀合金爲主要成份的薄膜200所覆蓋,並在300 °C下退火。結果發現附著力增加丨3 n。 如圖4D、4E和5所示,在200 W或3 00 W之下經過氧電漿 處理的玻璃基板100,由以銀合金爲主要成份的薄膜2〇〇所 覆蓋,並進行退火。即使在刻痕測試器尖形頭施加的力量 達到20 N以上,該薄膜也沒有從基板100上脱離。也就是説 ,基板100和薄膜200間的附著力大幅增加。 圖6 A至6E爲在玻璃基板上形成以三種來源極銀合金爲 主要成份的薄膜照片,其中薄膜利用刻痕測試器加以刻劃 ,藉此呈現附著狀態。圖7爲説明薄膜和玻璃基板間附著力 的圖表。 圖6 A至6E的處理狀況與圖2A至2E相同,除了用於該薄膜 的材料,是使用具有主内容物Ag和合金内容物Pd和Cu 5 atomic%的三種來源極銀合金,以及沈積方式是藉由賤射進 行此二條件之外。 如圖6A、6B和7所示,是以未經氧電漿處理、以AgPdCu —— __ -13-___ ' 本紙張尺度適用中國國家標準(CNS)八4規格(21〇x297公爱) — --- 502382 A7 I_______B7 五、發明説明(11 ) 爲主要成份的薄膜20〇,來覆蓋玻璃基板100。當施加在刻 痕測試,尖形頭上的力量約3 N時,薄膜2〇〇會脱離基板1〇〇 。也就是說,基板100和薄膜2〇〇間的附著力是相當薄弱。 如圖6C至6E和7所示,在15〇 w、2〇〇 w或3〇〇 w之下經 過氧電漿處理的玻璃基板1〇〇,由以銀合金爲主要成份的薄 膜200所覆蓋,並進行退火。即使在刻痕測試器尖形頭施加 的力里達到20 N以上,該薄膜也沒有從基板1〇〇上脱離。也 就是说,透過氧電漿處理,基板1〇〇和薄膜2〇〇間的附著力 大幅增加。 裝· #圖8A至8D爲在單晶珍基板上形成以AgMg爲主要成份的 薄膜照片’其巾薄膜利用刻痕測試器加以刻劃,藉此呈現 附耆狀態。圖9爲説明以銀合金爲主要成份的薄膜和矽基板 間的附著力圖表。在如圖所示的矽基板中,圖8八和所示 的薄膜被未經HF處理的薄膜所覆蓋,且該薄膜利用刻痕測 試器加以刻劃。如圖8八所示的矽基板係透過退火處理,但 疋如圖8B所tf的矽基板則未經退火處理。如圖8(:和8〇所示 的矽基板經由HF處理,由該薄膜所覆蓋。如圖叱所示的矽 基板未經過退火處理,但是如圖81)所示的基板則經過退火 處理。符號"A”和” HF”分別表示退火過程和HF處理,符號 nHF-An表示退火和HF兩種處理。 該銀合金利用具有主内容物Ag和合金内容物5 atomic%的目標材料所構成。該目標材料在壓力2❿陶爾的 條件下濺射至基板上,同時噴出的氬氣壓力爲2χΐ〇ό陶爾。 退火在壓力2χ106陶爾、溫度3〇〇巧〇〇〇c下進行3〇分鐘。具 L - 14 - 本紙張尺度適财㈣家鮮(CNS) A4規格(2ι〇χ297公爱) 观382 A7 一 B7 五、發明説明(12 ) 有金剛石尖形頭的刻痕測試器可用來測量附著力。測量時 在薄膜上刻劃,同時逐漸增加施加在刻痕測試器尖形頭的 力量,約在範圍0-40 N之間。在六個區域拍照。照片中所 呈現出來的線條是利用刻痕測試器尖形頭刻劃,且施力從 左至右逐漸增強。 如圖8A和9所示,以AgMg爲主要成份的薄膜2〇〇沈積在 未經HF處理的矽基板100上。在此狀況下來測量附著力。 結果發現薄膜2 0 0在刻痕測試卷尖形頭的施力達到5 n時脱 離基板100。 如圖8B至8D和9所示,矽基板100經過HF處理,且以銀合 金爲主要成份的薄膜200沈積在矽基板1〇〇上。覆蓋有薄膜 200的矽基板1〇〇在溫度3〇〇°C下進行退火30分鐘。結果演變502382 A7 ____ B7 V. Description of the invention (10 ~) " — Graph of adhesion between film and glass substrate. The processing conditions of FIGS. 4A to 4E are the same as those of FIGS. 2A to 2E, except that the material used for the film is a two-source extremely silver alloy with a main content Ag and an alloy content Mg 5 atomic%, and the deposition method is borrowed These two conditions are performed by sputtering. As shown in Figs. 4A, 4B, and 5, a glass substrate 100 is covered with a thin film 200 mainly composed of AgMg without oxygen plasma treatment. When the force applied to the tip of the nick tester is about 3 N, the thin film 200 is detached from the substrate 100. That is, the adhesion between the substrate 100 and the thin film 200 is relatively weak. As shown in Figs. 4C and 5, a glass substrate 100 treated with an oxygen plasma under 150 W is covered with a thin film 200 composed mainly of a silver alloy and annealed at 300 ° C. It was found that the adhesion increased by 3 n. As shown in Figs. 4D, 4E and 5, the glass substrate 100 which has been subjected to an oxygen plasma treatment at 200 W or 300 W is covered with a thin film 200 containing a silver alloy as a main component and annealed. Even if the force applied to the tip of the nick tester reaches 20 N or more, the film is not detached from the substrate 100. That is, the adhesion between the substrate 100 and the thin film 200 is greatly increased. Figures 6A to 6E are photographs of a thin film formed of three sources of extremely silver alloys on a glass substrate. The thin film is scratched with a nick tester to show the adhered state. Fig. 7 is a graph illustrating adhesion between a film and a glass substrate. The processing conditions of FIGS. 6A to 6E are the same as those of FIGS. 2A to 2E, except that the material used for the film is a three-source polar silver alloy with a main content Ag and an alloy content Pd and Cu 5 atomic%, and a deposition method Beyond these two conditions by cheap shots. As shown in Figures 6A, 6B and 7, it is treated with AgPdCu without oxygen plasma treatment. __ -13 -___ 'This paper size is applicable to China National Standard (CNS) 8-4 specification (21〇x297 public love) — --- 502382 A7 I_______B7 V. Description of the invention (11) The thin film 20 as the main component covers the glass substrate 100. When the force applied to the nick test is about 3 N, the film 200 will be separated from the substrate 100. That is, the adhesion between the substrate 100 and the thin film 200 is relatively weak. As shown in FIGS. 6C to 6E and 7, a glass substrate 100 treated with an oxygen plasma under 150w, 200w, or 300w is covered with a thin film 200 mainly composed of a silver alloy. And annealed. The film did not come off the substrate 100 even when the force applied by the tip of the nick tester reached 20 N or more. That is, the adhesion between the substrate 100 and the thin film 200 was greatly increased by the oxygen plasma treatment. Figs. 8A to 8D are photographs of a film made of AgMg as a main component formed on a single crystal substrate, and the towel film is scribed with a scoring tester, thereby showing an attached state. Fig. 9 is a graph illustrating the adhesion between a thin film containing a silver alloy as a main component and a silicon substrate. In the silicon substrate shown in the figure, the films shown in FIGS. 8A and 8B are covered with a film without HF treatment, and the film is scored with a nick tester. The silicon substrate shown in FIG. 8A is annealed, but the silicon substrate tf shown in FIG. 8B is not annealed. The silicon substrates shown in FIGS. 8 (: and 80) are processed by HF and covered by the film. The silicon substrates shown in FIG. 8 are not annealed, but the substrates shown in FIG. 81 are annealed. The symbols "A" and "HF" indicate the annealing process and HF treatment, respectively, and the symbol nHF-An indicates the annealing and HF treatment. The silver alloy is composed of a target material having a main content of Ag and an alloy content of 5 atomic%. The target material was sputtered onto the substrate under a pressure of 2 Torr, and the pressure of the argon gas sprayed was 2 × ΐ〇th Taur. The annealing was performed at a pressure of 2 × 106 Tall and a temperature of 300 ° C. 3 ° C. 〇minutes. With L-14-This paper is suitable for domestic use (CNS) A4 size (2ιχχ297 public love) View 382 A7-B7 V. Description of the invention (12) Scoring tester with diamond tip Can be used to measure adhesion. Scribing on the film during measurement, while gradually increasing the force applied to the tip of the nick tester, in the range of 0-40 N. Take pictures in six areas. Shown in the photo The lines are scribed with a pointed head of a scoring tester, and the force is gradually increased from left to right. As shown in Figs. 8A and 9, a thin film 200 mainly composed of AgMg is deposited on silicon without HF treatment. On the substrate 100. The adhesion was measured under this condition. As a result, it was found The film 2 0 was detached from the substrate 100 when the force of the tip of the scoring test roll reached 5 n. As shown in FIGS. 8B to 8D and 9, the silicon substrate 100 was subjected to HF treatment, and a film composed mainly of silver alloy. 200 was deposited on a silicon substrate 100. The silicon substrate 100 covered with the thin film 200 was annealed at a temperature of 300 ° C for 30 minutes. The evolution of the results
成基板100和薄膜200間的附著力增加了 27 N、32 N和38 N 〇 圖10A至10D爲在玻璃基板上形成以AgTi爲主要成份的 薄膜照片,其中薄膜利用刻痕測試器加以刻寫,藉此呈現 附著狀態。圖11爲説明薄膜和玻璃基板間附著力的圖表。 圖10八_至10D的處理狀況·與圖8A至8D相同,除了用於該 薄膜的材料,是使用具有主内容物Ag和合金内容物丁丨5 atomic%的目標材料,以及沈積方式是藉由濺射進行此二條 件之外。 — 如圖10A和11所示,一玻璃基板1〇〇是以未經财處理、以 AgTi爲主要成份的薄膜200所覆蓋。當施加在刻痕測試器尖 形頭上的力量約12 N時,薄膜200會脱離基板10〇。也就是 -15-The adhesion between the substrate 100 and the thin film 200 increased by 27 N, 32 N, and 38 N. FIGS. 10A to 10D are photographs of a thin film containing AgTi as a main component formed on a glass substrate. The thin film is written with a nick tester. Thereby, the adhered state is exhibited. FIG. 11 is a graph illustrating adhesion between a film and a glass substrate. The processing conditions of Figures 10A to 10D are the same as those of Figures 8A to 8D, except that the material used for the film is a target material with 5% atomic% of the main content Ag and alloy content, and the deposition method is borrowed. These two conditions are performed by sputtering. — As shown in FIGS. 10A and 11, a glass substrate 100 is covered with a thin film 200 containing AgTi as the main component without any financial treatment. When the force applied to the tip of the nick tester is about 12 N, the film 200 is detached from the substrate 100. Which is -15-
502382 A7 B7 五、發明説明(13 ) 說,基板100和薄膜200間的附著力是相當薄弱。 如圖10B至1 0D和11所示,經過氧電漿處理的玻璃基板 100,由以銀合金爲主要成份的薄膜2〇〇所覆蓋,並在3〇〇 °C下退火。結果演變成基板1〇〇和薄膜2〇〇間的附著力增加 20 N以上。 圖12和13爲説明沈積在HF處理基板和未處理基板上的 以AgMg爲主要成份的薄膜和以AgTi爲主要成份的薄膜,其 電阻係數與退火溫度間關係的變化圖。圖表水平軸表示電 阻係數,垂直軸表示退火溫度。符號"As-dep”是指覆蓋有 以銀合金爲主要成份的薄膜的基板狀態爲未經退火處理。 如圖12所示,沈積在經HF處理的基板和未經處理的基板 上以AgMg爲主要成份的薄膜,電阻係數爲4·5 μ 。當 對該薄膜進行退火時,電阻係數減少。結果變成在退火溫 度3 00-5 00 C的情況時,電阻係數約3 〇_3 5 μ 。 圖1 3所示,沈積在經HF處理的基板和未經處理的基板上 以AgTi爲主要成份的薄膜,電阻係數爲1〇 μ Q-cm。當對該 薄膜進行退火時,電阻係數減少。結果變成在退火溫度 300-500Ϊ的情況時,電阻係數約4 5 picm。 同時,在退火的處理下,可在以銀合金(AgMg、AgTi)爲 主要成份的薄膜200和矽基板丨〇〇間形成一矽化層。該碎化 層可用來增加薄膜20¾和矽基板1〇〇間的附著力。 圖14説明矽合金的熔點溫度(κ)與根據熔點溫度的熱含 量(ΔΗΓ,kcal/mole)。從圖中可發現,薄膜2〇〇的銀合金與 基板100的矽起作用,藉此形成矽化層。 -16-502382 A7 B7 5. Description of the Invention (13) It is said that the adhesion between the substrate 100 and the film 200 is relatively weak. As shown in FIGS. 10B to 10D and 11, the glass substrate 100 subjected to the oxygen plasma treatment is covered with a thin film 200 containing a silver alloy as a main component and annealed at 300 ° C. As a result, the adhesion between the substrate 100 and the film 200 increased by more than 20 N. Figures 12 and 13 are graphs illustrating the relationship between the resistivity and the annealing temperature of films with AgMg as the main component and films with AgTi as the main component deposited on HF-treated substrates and untreated substrates. The horizontal axis of the graph represents the resistivity, and the vertical axis represents the annealing temperature. The symbol "As-dep" means that the substrate covered with a thin film containing silver alloy as the main component is unannealed. As shown in FIG. 12, AgMg is deposited on the HF-treated substrate and the untreated substrate. The film with the main component has a resistivity of 4 · 5 μ. When the film is annealed, the resistivity decreases. As a result, when the annealing temperature is 3 00-5 00 C, the resistivity is about 3 〇_3 5 μ As shown in Figure 13, the film with AgTi as the main component deposited on HF-treated substrates and untreated substrates has a resistivity of 10 μ Q-cm. When the film is annealed, the resistivity decreases The result is that when the annealing temperature is 300-500 ° C, the resistivity is about 4 5 picm. At the same time, under the annealing process, the thin film 200 and the silicon substrate with a silver alloy (AgMg, AgTi) as the main component can be used. A silicide layer is formed between the two layers. The disintegration layer can be used to increase the adhesion between the thin film 20¾ and the silicon substrate 100. Figure 14 illustrates the melting point temperature (κ) and the heat content (ΔΗΓ, kcal / mole) of the silicon alloy. ). It can be found from the figure that the film A 200 silver alloy interacts with the silicon of the substrate 100 to form a silicide layer. -16-
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上述的氧電漿或HF處理或退火技術,都是用來增加薄膜 和底層基板間的附著力,該技術也適用於非由玻璃或矽材 料所構成的基板之情沉。 在私參考圖1 5和1 6,來說明根據本發明第一較佳具體 貫施例的薄膜電晶體陣列基板的結構。 圖丨5是根據本發明第一較佳具體實施例的薄膜電晶體陣 列基板的平面圖,而圖16則爲沿著圖15的XVI-XVI,線段所 切割出的側視圖。 在絕緣基板10上形成具有單層或多層結構的閘線組合, 其中顯示銀或兩/三種來源極的銀合金。該閘線組合相對於 基板10具有20 N以上的附著力。該閘線組合包括以水平方 向展開的閘線22和連接至閘線22末端的閘填充24。該閘填 充24從外邵接收閘信號,傳送至閘線22。TFT的閘電極26 =連接至閘線22。假設形成的閘線组合具有多層結構,它 可旎包含一填充材料,該材料具有與其他材料接觸效果佳 的特貝。假设填充材料是兩種或三種來源極的銀合禽,該 材料可由王内容物銀和合金内容物傳導材料〇·〇ι_2〇 咖—下所構成,該合.金内容物包括例如pd、cu、吨 、八卜 Li、PU、Np、Ce、Eu、Pr、Ca、La、Nb、Nd和 Sm 〇 在基板10上所形成-的間絕緣層30是由氮化矽所组成,並 覆蓋該閘線組合。 閘絕緣層30上所形成的半導體圖案4〇位於閘電極24之上 ,在半導體圖案40上所形成的歐姆接觸圖案55和%則具有 17- ^297^¾)The above-mentioned oxygen plasma or HF treatment or annealing techniques are used to increase the adhesion between the thin film and the underlying substrate. This technology is also applicable to substrates other than glass or silicon materials. The structure of the thin film transistor array substrate according to the first preferred embodiment of the present invention will be described with reference to FIGS. 15 and 16. 5 is a plan view of a thin film transistor array substrate according to the first preferred embodiment of the present invention, and FIG. 16 is a side view cut along the line XVI-XVI of FIG. 15. A gate line combination having a single-layer or multi-layer structure is formed on the insulating substrate 10, in which silver or a silver alloy of two or three source electrodes is displayed. This brake wire assembly has an adhesion of 20 N or more to the substrate 10. The gate line combination includes a gate line 22 that is deployed in a horizontal direction and a gate filler 24 connected to the end of the gate line 22. The gate filler 24 receives the gate signal from Wai Shao and transmits it to the gate line 22. The gate electrode 26 of the TFT is connected to the gate line 22. Assume that the formed brake wire combination has a multi-layered structure, which may include a filler material, which has a Teflon that has good contact with other materials. It is assumed that the filling material is a silver alloy bird with two or three source electrodes, and the material can be composed of the silver content of the king content and the conductive material of the alloy content 〇 · 〇ι_2〇 coffee. The gold content includes, for example, pd, cu , Ton, octane Li, PU, Np, Ce, Eu, Pr, Ca, La, Nb, Nd, and Sm. The interlayer 30 formed on the substrate 10 is composed of silicon nitride and covers the Brake line combination. The semiconductor pattern 40 formed on the gate insulating layer 30 is located above the gate electrode 24, and the ohmic contact patterns 55 and% formed on the semiconductor pattern 40 have 17- ^ 297 ^ ¾)
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矽f氫化非晶矽’其中n型雜質係以高濃度的方。 ^姆接_㈣和56以及閘„3()上的資料線組 ^金所構成。該資料、線組合可具有單層或多層結構。, =線組合包括以垂直方向展開的資料⑽,同時超越過 甲1線22以疋義像素,並包括源極65,從資料線似支出去 、:同時延伸超過某一側的歐姆接觸圖案”。資料填充“係 丢至貧料線62的某一端,以便從外部接收圖形信號。汲 極66位於歐姆接觸圖案56的另—側,同時在閘電極26處愈 分開。爲增加儲存容量,資料線組合另可包括儲存 ^各傳導圖木64 °該儲存電容傳導圖案64與閘線22重疊, 藉此形成儲存電容。 兩或三種來源極的銀合金都可用於資料線組合。所形成 的銀σ金具有王内容物銀和合金内容物傳導材料Ο·。】-?。 atomic%以下,其中該合金内容物包括例如Mg、Ca、Th、Silicon f hydrogenated amorphous silicon 'wherein n-type impurities are in a high concentration. ^ Mu _㈣ and 56 and the data line group on the gate „3 () are composed of gold. The data and line combination can have a single-layer or multi-layer structure. = Line combination includes the data line expanded in the vertical direction, and at the same time Beyond the first line 22, the pixel is defined, and the source electrode 65 is included, and the data line seems to be expended to extend the ohmic contact pattern on one side at the same time. " The data filling "is dropped to one end of the lean line 62 in order to receive the graphic signal from the outside. The drain 66 is located on the other side of the ohmic contact pattern 56 and is more separated at the gate electrode 26. To increase the storage capacity, the data line The combination may further include storage of each conductive pattern 64 °. The storage capacitor conductive pattern 64 overlaps with the gate line 22 to form a storage capacitor. Two or three source silver alloys can be used for the data line combination. The formed silver σ Gold has a king content silver and an alloy content conductive material 0.]-?. Atomic% or less, where the alloy content includes, for example, Mg, Ca, Th,
Zr、Co、Ni、Ή、V、Nb、Mo、Ta、W和 Cr。假使形成的 資料線組合具有多層結構,t可能由—傳導材料所構成, 孩材料具有與其他材料接觸效果佳的特質。 一保護層70在資料線組合和半導體圖案牝上、具有良好 平面化特性的氮化碎或有機材料所構成,_並透過該資 料線組合顯露出來。 一該保護層70具有,觸孔72、76和78,可分別曝露儲存電 容傳導圖案64、汲極66和資料填充68。甚至,該保護層7〇 所具有的接觸孔74,可曝露閘填充24和閘絕緣層3〇。 像素電極82在像素區的保護層7〇上形成,其透過接觸孔Zr, Co, Ni, rhenium, V, Nb, Mo, Ta, W and Cr. If the formed data line combination has a multilayer structure, t may be composed of a conductive material, and the material has the characteristics of good contact with other materials. A protective layer 70 is formed on the data line combination and the semiconductor pattern, and is formed of nitrided or organic materials with good planarization characteristics, and is exposed through the data line combination. One of the protective layers 70 has contact holes 72, 76, and 78, which can expose the storage capacitor conductive pattern 64, the drain 66, and the data fill 68, respectively. Furthermore, the contact hole 74 of the protective layer 70 can expose the gate filling 24 and the gate insulating layer 30. The pixel electrode 82 is formed on the protective layer 70 in the pixel region, and passes through the contact hole.
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72和76連接至儲存電容傳導圖案64和汲極66。甚至,輔助 閘和資料填充84和88也在保護層70上形成,以致透過接觸 孔7 4和7 8連接至閘和資料填充2 4和6 8。像素電極8 2和輔助 閘和資料填充86和88利用透明傳導材料像銦錫氧化物 (ITO)或銦鋅氧化物(IZO)所構成。 連接至該像素電極82的儲存電容傳導圖案64,與閘線22 重疊,·藉此形成儲存電容。假使儲存電容不夠,儲存電容 線組合可在與閘線組合相同的平面上形成。 如上所述結構的薄膜電晶體陣列基板,利用以低阻抗的 銀或銀合金爲主要成份的接線組合所構成,可達到最小化 的信號延遲,以及寬螢幕和高解析度。 現在將參考圖17A至20B來解釋製造薄膜電晶體陣列基 板的方法。 如圖17A和17B所示,一玻璃基板1〇經過氧電漿處理十分 鐘。以銀或銀合金爲主要成份的沈積層沈積在該破璃基板 1〇上並形成圖案,藉此形成一閘線組合。該閘線組合包括 閘線22、閘電極26和閘填充24。假設兩種或三種來源極的 銀合金是用於該閘線組合,該組合可由主内容物銀和合金 内容物傳導材料0.01-20 atomic%所構成,該合金内容物包 括例如 Pd、Cu、Mg、A卜 Li、PU、Np、Ce、Eu、pr、Ca 、La、Nb、Nd和Sm。該銀合金濺射至該基板1〇上,並形成 圖案’精此形成該問線組合。 與玻璃基板1 0有關的氧電漿處理增加基板和以銀合金爲 主要成份的沈積層之間的附著力2〇 N以上。在沈積了以銀 -19-72 and 76 are connected to the storage capacitor conductive pattern 64 and the drain 66. Further, auxiliary gates and data fills 84 and 88 are also formed on the protective layer 70 so as to be connected to the gates and data fills 2 4 and 68 through the contact holes 74 and 78. The pixel electrode 82 and the auxiliary gate and data fill 86 and 88 are made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The storage capacitor conductive pattern 64 connected to the pixel electrode 82 overlaps the gate line 22, thereby forming a storage capacitor. If the storage capacitor is not enough, the storage capacitor line combination can be formed on the same plane as the gate line combination. The thin-film transistor array substrate structured as described above is composed of a wiring combination with low impedance silver or a silver alloy as a main component, which can minimize signal delay, and have a wide screen and high resolution. A method of manufacturing a thin film transistor array substrate will now be explained with reference to Figs. 17A to 20B. As shown in Figs. 17A and 17B, a glass substrate 10 was subjected to an oxygen plasma treatment for ten minutes. A deposition layer mainly composed of silver or a silver alloy is deposited on the broken glass substrate 10 and formed into a pattern, thereby forming a gate line assembly. The gate wire combination includes a gate wire 22, a gate electrode 26, and a gate filler 24. It is assumed that two or three source silver alloys are used for the brake wire combination. The combination may be composed of the main content silver and the alloy content conductive material 0.01-20 atomic%. The alloy content includes, for example, Pd, Cu, Mg. A, Li, PU, Np, Ce, Eu, pr, Ca, La, Nb, Nd, and Sm. The silver alloy is sputtered onto the substrate 10, and a pattern is formed to form the question line combination. Oxygen plasma treatment related to the glass substrate 10 increases the adhesion between the substrate and the deposited layer mainly composed of a silver alloy by more than 20 N. Accumulated with silver in Shen -19-
A7A7
合金爲主要成份的層之後,對該沈積層進行退火。 该氧電漿處理最好在壓力1 -1 00陶爾的情況下進行〇 5 3 〇 分鐘,同時噴射氧氣1 — 1000 sccm。退火過程最好是在眞空 、氮、或氫環境下、溫度250-500°C的條件下進行3〇_12〇分 鐘。 又後,如圖18A和18B所示,一以氮化矽爲主要成份的閘 絕緣層30、一以非晶矽爲主要成份的層4〇、一摻雜非晶石夕 爲主要成份的層5〇依序沈積在基板10上。該以非晶珍爲主 要成份的層40以及以非晶矽爲主要成份的層5〇都經由光罩 开成圖案,藉此形成一半導體圖案4 〇和一歐姆接觸圖案$ 〇 。違半導體圖案40和歐姆接觸圖案50都位於該閘電極24之 上的閘絕緣層30。 如圖19A和19B所示,該基板會浸在HF溶液中,使得半導 體圖案40和歐姆接觸圖案5〇經過hf處理。以銀合金爲主要 成份的傳導層利用濺射沈積在該基板1 0上,並利用光刻法 形成圖案’藉此形成一資料線組合。該資料線組合包括跨 越閘線22的資料線62,以及連接至資料線62同時延伸越過 該閘電極26的源極65。資料填充68係連接至資料線62的某 一端。没極66位於閘電極26附近相對於源極65的位置,且 儲存電容傳導圖案64係與該閘線22重疊。兩或三種源極的 銀合金都可用於資料·線組合。所形成的銀合金具有主内容 物銀和6金内谷物傳導材料〇 · q 1 · 2 〇 0 m i c %以下,其中該 合金内容物包括例如Mg、Ca、Th、Zr、Co、Ni、Ti、V、 Nb、Mo、Ta、W和 Cr 〇 -20- 張尺度適财@ s轉準(CNS) Μ規格(2綱297公y-- 502382 A7 B7 五、發明説明After the alloy is the main component layer, the deposited layer is annealed. The oxygen plasma treatment is preferably performed at a pressure of 1 to 100 Tao for 530 minutes, while spraying oxygen with 1 to 1000 sccm. The annealing process is preferably performed in the atmosphere of nitrogen, nitrogen, or hydrogen at a temperature of 250-500 ° C for 30-12 minutes. Then, as shown in FIGS. 18A and 18B, a gate insulating layer 30 mainly composed of silicon nitride, a layer 40 mainly composed of amorphous silicon, and a layer doped with amorphous stone as a principal component. 50 is sequentially deposited on the substrate 10. The layer 40 mainly composed of amorphous silicon and the layer 50 mainly composed of amorphous silicon are patterned through a photomask, thereby forming a semiconductor pattern 40 and an ohmic contact pattern $ 0. The semiconductor pattern 40 and the ohmic contact pattern 50 are both located on the gate insulating layer 30 on the gate electrode 24. As shown in FIGS. 19A and 19B, the substrate is immersed in an HF solution so that the semiconductor pattern 40 and the ohmic contact pattern 50 are subjected to hf treatment. A conductive layer mainly composed of a silver alloy is deposited on the substrate 10 by sputtering, and is patterned by photolithography to form a data line assembly. The data line combination includes a data line 62 crossing the gate line 22 and a source 65 connected to the data line 62 and extending across the gate electrode 26 at the same time. The data fill 68 is connected to one end of the data line 62. The immortal electrode 66 is located near the gate electrode 26 with respect to the source electrode 65, and the storage capacitor conductive pattern 64 overlaps the gate line 22. Silver alloys with two or three sources can be used for data and wire combinations. The formed silver alloy has a main content of silver and a 6-gold internal grain conductive material of 0 · q 1 · 2 0 0 mic%, wherein the alloy content includes, for example, Mg, Ca, Th, Zr, Co, Ni, Ti, V, Nb, Mo, Ta, W, and Cr 〇-20- Zhang Jiao Shi Cai @ s Zhuan Zhuan (CNS) M specifications (2 outlines 297 public y-502382 A7 B7 V. Description of the invention
在以碎爲主要成份的層40和50經過HF處理後,該碎層和 資料線組合之間的附著力可增加20 N以上。爲了進一步提 升這類附著力的強度,具有該資料線組合的基板1〇可在 250-500°C的溫度下進行退火。在本例中,一矽化物層在該 石夕層40和50和資料線組合之間形成,同時增強該附著力。 透過該資料線組合曝露出來的歐姆接觸圖案5〇受到蝕刻 ,以致分隔爲兩側的圖案55和56,同時曝露該底層的半導 體圖案40。該曝露的半導體圖案4〇經過氧電漿處理,使表 面特性更穩定。之後,如圖20A和20B所示,具有低電介質 特性和良好的平面化特徵的絕緣材料,像氮化矽或有機材 料,沈積在基板10之上,藉此形成保護層7〇。接著,該保 護層70利用乾蝕刻和該閘絕緣層3〇形成圖案,藉此形成接 觸孔72、74、76和78,曝露該儲存電容傳導圖案64、閘填 充24、汲極66和資料填充68。 最後,如圖15和16所示,以ΐτο或IZ〇爲主要成份的層沈 積在該基板10之上,並利用光罩形成圖案,藉此形成像素 電極82、輔助閘填充86和輔助資料填充“。該像素電極α 係透過接觸孔72和76連接至該儲存電容傳導圖案64和汲極 66。該輔助閘和資料填充86和88係透過接觸孔”和”連接 至閘資料填充24和68。 本技術可應用在製·造薄膜電晶體陣列基板的方法上,不 僅用於五層光罩也用於四層光罩的情況。 圖2i爲根據本發㈣二較佳具體實施例的液晶顯示的薄 膜電晶體陣列基板平面圖;圖22和23爲分別沿著圖。的After the layers 40 and 50 having the shred as the main component are subjected to HF treatment, the adhesion between the shred and the data line combination can be increased by more than 20 N. In order to further improve the strength of such adhesion, the substrate 10 having the data line combination can be annealed at a temperature of 250-500 ° C. In this example, a silicide layer is formed between the stone layer 40 and 50 and the data line combination, while enhancing the adhesion. The ohmic contact pattern 50 exposed through the data line combination is etched so that the patterns 55 and 56 separated on both sides are exposed, and the semiconductor pattern 40 of the underlying layer is exposed at the same time. The exposed semiconductor pattern 40 is treated with an oxygen plasma to make the surface characteristics more stable. Thereafter, as shown in FIGS. 20A and 20B, an insulating material, such as silicon nitride or an organic material, having low dielectric characteristics and good planarization characteristics is deposited on the substrate 10, thereby forming a protective layer 70. Next, the protective layer 70 is patterned by dry etching and the gate insulating layer 30, thereby forming contact holes 72, 74, 76, and 78, exposing the storage capacitor conductive pattern 64, gate fill 24, drain 66, and data fill. 68. Finally, as shown in FIGS. 15 and 16, a layer having ΐτο or IZ〇 as a main component is deposited on the substrate 10, and a photomask is used to form a pattern, thereby forming a pixel electrode 82, an auxiliary gate fill 86, and an auxiliary data fill ". The pixel electrode α is connected to the storage capacitor conductive pattern 64 and the drain 66 through contact holes 72 and 76. The auxiliary gate and data fill 86 and 88 are through the contact hole" and "connected to the gate data fill 24 and 68" This technology can be applied to the method of manufacturing and fabricating a thin film transistor array substrate, not only in the case of a five-layer photomask, but also in a case of a four-layer photomask. Fig. 2i shows a liquid crystal according to a preferred embodiment of the present invention. A plan view of a thin film transistor array substrate shown; Figures 22 and 23 are taken along the figure.
裝 訂Binding
-21 --twenty one -
502382 A7502382 A7
ΧΧΙΙ-ΧΧΙΓ線和ΧΧΙΙΙ-ΧΧΙΙΙ,線所切割出的薄膜電晶體陣 列基板之側視圖。 利用以銀爲主要成份的傳導材料,在絕緣基板丨0上形成 一閘線組合。該閘線組合包括閘線22、閘填充24和閘電極 26。該閘線組合另包括以與閘線22成平行方向展開的儲存 電容電極28,以便從外部接受共用的電極電壓。該儲存電 容電極28與連接至像素電極82的儲存電容傳導圖案“重= ,藉此形成儲存電容同時增加像素的電位儲存電容。假^Side view of the thin-film transistor array substrate cut out of the XXIX-XXIX lines and XXIX-XIXII, lines. Using a conductive material with silver as the main component, a gate line combination is formed on the insulating substrate 丨 0. The gate line combination includes a gate line 22, a gate filler 24, and a gate electrode 26. The gate line combination further includes a storage capacitor electrode 28 which is developed in a direction parallel to the gate line 22 to receive a common electrode voltage from the outside. The storage capacitor electrode 28 and the storage capacitor conductive pattern connected to the pixel electrode 82 have a weight "=", thereby forming a storage capacitor and increasing the potential storage capacitance of the pixel. False ^
裝 孩儲存電容因爲像素電極82和閘線22的重疊而變得相當高 ,則可省略掉儲存電容28。 门 閘絕緣層30在閘線組合上由氮化矽所構成,同時覆蓋閘 線組合。 訂 半導體圖案42和48在閘絕緣層30上由氫化的非晶矽所構 成。歐姆圖案55、56和58在半導體圖案42和48由摻雜的非 晶矽所構成,其中η形雜質例如像磷(ρ)以高濃度摻雜其中 一資料線組合在歐姆接觸圖案55、56和58上由銀合金所 構成。m資料線組合包括資料線62以垂直方向展開、資料 填充68,該填充連接至某一端資料線62以便從外部接收圖 形信號、以及源極65,從該資料線62分支出來。該資料線 組合另包括汲極66,、於閘電極26附近的源極65對面,以 及位於儲存電容電極28之上的儲存電容傳導圖案64。假設 儲存電容電極28不存在,則可忽略儲存電容傳導圖案64。 該資料線組合由以鋁或鋁合金、鉻、鉬或鉬合金、妲、 -22-Since the storage capacitor becomes relatively high due to the overlap of the pixel electrode 82 and the gate line 22, the storage capacitor 28 can be omitted. The gate insulation layer 30 is composed of silicon nitride on the gate wire combination, and covers the gate wire combination at the same time. The semiconductor patterns 42 and 48 are formed on the gate insulating layer 30 by hydrogenated amorphous silicon. The ohmic patterns 55, 56 and 58 are composed of doped amorphous silicon in the semiconductor patterns 42 and 48, in which n-type impurities such as phosphorus (ρ) are doped at a high concentration. One of the data lines is combined in the ohmic contact patterns 55, 56. And 58 are made of silver alloy. The m data line combination includes a data line 62 expanded in a vertical direction, and a data padding 68 connected to a certain end data line 62 to receive a graphic signal from the outside, and a source 65 branching from the data line 62. The data line combination further includes a drain 66, a source 65 opposite the gate electrode 26, and a storage capacitor conductive pattern 64 above the storage capacitor electrode 28. Assuming that the storage capacitor electrode 28 does not exist, the storage capacitor conductive pattern 64 may be ignored. The data line combination consists of aluminum or aluminum alloy, chromium, molybdenum or molybdenum alloy, thorium, -22-
或欽的單層所構成。 居馱姆接觸圖案55、56和58降低底層半導體圖42和48以 及覆盍其上的資料線組合之間的接觸電阻,同時具有與資 料線組合一樣的外觀。也就是,該歐姆接觸圖案5 5具有和 資料線62、源極65和資料填充68一樣的外觀,該歐姆接觸 圖案56具有與汲極66一樣的外觀,以及該歐姆接觸圖案58 具有與儲存電容傳導圖案64相同的外觀。 除了通道區C之外,半導體42和48具有和資料線組合和歐 姆接觸圖案55、56和58—樣的外觀。特別是,該半導體圖 案48、傳導圖案64和該儲存電容的歐姆接觸圖案58,都具 有相同的外觀,但是該TFT半導體圖案42與該資料線組合 和對應的歐姆接觸圖案55和56略有不同。也就是,該源極 和汲極65和66在通遒區c彼此分開,並且該資料線62、源極 65和、料填充68的歐姆接觸圖案55,以及該汲極&的歐姆 接觸圖案56也都在這個部份彼此分開。但TFT半導體圖案 42在该區持續展開並無分開,同時形成通道。 一保護層70在資料線組合上由氮化矽所構成,該氮化矽 爲具有較低電介質特性和良好平面化特徵的有機材料。 該保護層70具有接觸孔72、76和78,分別顯露資料填充 64、没極66和儲存電容傳導圖案68。甚至,該保護層7〇另 具有接觸孔74,顯露閘填充24和閘絕緣層30。 像素電極82在保護層70上形成,以便從TFT接受信號並 產生電場和對立基板的共通電極。該像素電極82利用類似 ιτο和ιζο的透明傳導材料所構成。該像素電極82透過接觸 -23- 本紙張尺度適财_冢辨(CNS) A4規格(蒙297公愛) 502382 A7Or Qin's single layer. The Cumming contact patterns 55, 56, and 58 reduce the contact resistance between the underlying semiconductor patterns 42 and 48 and the data line combination covering it, and have the same appearance as the data line combination. That is, the ohmic contact pattern 55 has the same appearance as the data line 62, the source 65, and the data fill 68, the ohmic contact pattern 56 has the same appearance as the drain 66, and the ohmic contact pattern 58 has a storage capacitance The conductive patterns 64 have the same appearance. Except for the channel region C, the semiconductors 42 and 48 have an appearance similar to that of the data line combination and the ohmic contact patterns 55, 56 and 58. In particular, the semiconductor pattern 48, the conductive pattern 64, and the ohmic contact pattern 58 of the storage capacitor all have the same appearance, but the TFT semiconductor pattern 42 and the data line combination and the corresponding ohmic contact patterns 55 and 56 are slightly different. . That is, the source and drain electrodes 65 and 66 are separated from each other in the through region c, and the data line 62, the source 65 and the ohmic contact pattern 55 of the material fill 68, and the ohmic contact pattern of the drain & 56 are also separated from each other in this part. However, the TFT semiconductor pattern 42 continues to develop in this area without separation, and at the same time forms a channel. A protective layer 70 is composed of silicon nitride on the data line assembly, which is an organic material with lower dielectric characteristics and good planarization characteristics. The protective layer 70 has contact holes 72, 76, and 78, respectively, exposing the data filling 64, the electrode 66, and the storage capacitor conductive pattern 68. Furthermore, the protective layer 70 has a contact hole 74 to expose the gate filling 24 and the gate insulating layer 30. The pixel electrode 82 is formed on the protective layer 70 so as to receive a signal from the TFT and generate an electric field and a common electrode of the counter substrate. The pixel electrode 82 is made of a transparent conductive material similar to ιτο and ιζο. The pixel electrode 82 passes through the contact -23- The paper size is suitable for financial purposes_ Tsukawa (CNS) A4 size (Mongolian 297 public love) 502382 A7
孔76以物理電連接至汲極66,以接收圖形信號。該像素電 極82與鄰近的閘和資料線22和62重疊,以增加開口比例, 但可控制該重疊。甚至,像素電極82也可透過接觸孔72連 接至儲存電容圖案64,以向該圖案傳送圖形信號。 同時,輔助閘和資料填充84和88在閘和資料塡充24和68 上形成,以致透過該接觸孔74和78連接至閘和資料填充24 和68。該輔助閘和資料填充84和88都利用外部線路來加強 附著力’同時保護該閘和資料填充24和68。該輔助閘和資 料填充84和88可以選擇性地方式來加以使用。 現在將參考圖24A至3〇(:來解釋使用四層光罩來製造薄 膜電晶體陣列基板的方法。 如圖24A至24C所示,該基板1〇經過氧電漿處理,且一以 銀或銀合金爲主要成份的傳導材料沈積在該基板1〇上。接 著以傳導材料爲主要成份的層藉由光刻法形成圖案,藉此 形成一閘線組合。該閘線組合包括閘線22、閘填充24和閘 電極26和儲存電容電極28。 足後,如圖25A和25B所示,一以氮化矽爲主要成份的閘 絕緣層30、一半導體層4〇和一歐姆接觸層5〇依序沈積在該 基板上10,以致分別具有1500-5000 A、500-2000 A和 3 00-600 A的厚度。該歐姆接觸層5〇經過HF處理,以及一包 含銀合金的傳導層60藉由濺射沈積在該歐姆接觸層5〇上, 以致形成1500-3 000 A的厚度。一光致抗蝕膜i 1〇覆蓋到該 傳導層60上厚度爲μπι。此時,所沈積的閘絕緣層3〇最 好是在300°C以上的環境下進行五分鐘。 -24- ΐ紙張尺度適财國g家標準(CNS) Μ規格(細Μ9?公爱) 502382 A7 ___ B7_ 五、發明説明(22 ) 之後,如圖26B和26C所示,該光致抗蝕膜11〇透過光罩 曝露在光線之下並顯影出來,藉此形成光致抗蝕圖案n 2 和114。此時’位於源極和没極65和66間通道區匚的第一光 致抗蝕圖案區1 14建立,其厚度小於位於資料線組合之上的 第二光致抗蝕圖案區112。光致抗蝕膜的剩餘區域b則全部 私除。位於通道區C的第一光致抗蚀圖案區114以及位於資 料線組合區A的第二光致抗蝕圖案區1丨2的厚度比例,應視 I虫刻狀況而有所不同。最好第一區114和第二區112的厚度 比爲1/2以下。例如第一區114的厚度可建立爲4〇〇〇 A以下 〇 光致抗餘膜的厚度可能各區不同。爲了控制資料線組合 區A上的光傳輸,可能會用到一裂縫或格狀圖案、或半透 明的膜。 最好裂缝圖案的開口寬度應小於曝露在光線下裝置的分 解能力。在半透明膜的情況下,可使用不同光傳輸或厚度 的薄膜來控制光傳輸。 當光線透過光罩照射在光致抗蚀膜上時光曝露區上的高 分子會芫全分解’且在裂缝圖案或半透明膜上的光致抗蚀 膜也會部份分解。在光阻膜上的光致抗蝕膜一點也不會分 解。當光致抗蚀膜在顯像時’剩餘的光致抗姓膜的厚度會 局部有差異。若光曝露時間過長,所有分子都可能會分解 〇 厚度相當薄的光致抗蚀膜114可使用能夠回流的光致抗 蝕膜來製作。會出現透明區域和不透明區域的一般光罩, -25- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) '^ ---— 502382 A7 __B7 五、發明説明(Z3 ) 會用於以光曝露該光致抗蝕膜114。光致抗蝕膜114會顯像 ,且在光致抗蝕膜114上產生回流,以致光致抗蝕膜的内容 物流至非膜區域。 之後,該傳導層60、歐姆接觸層50和半導體層40都使用 光致抗I虫圖案作爲光罩。因此,在資料線組合區A留下資 料線組合和底層,通道區C上只留下半導體層40,而剩餘區 域B只留下絕緣層30。 爲此目的,如圖27A和27B所示,曝露在B區的傳導層60 被移除,同時使得底層歐姆接觸層50向外顯露。在此過程 中,在蝕刻傳導層60的情況下可使用乾蝕刻或濕蝕刻,同 時會留下光致抗蝕圖案112和114。但是,假使採用乾蝕刻 ,通常較少使用這種蝕刻方式,則會同時蝕刻光致抗蝕圖 案1 12和1 14。在這種情況下,第一光致抗蚀圖案區1 14的厚 度應相當厚,以避免第一光致抗蝕圖案區1 14整個移除,同 時曝露出底層的傳導層60。 ,· 假使傳導層60是Mo或Mo W合金、A1或A1合金、或Ta, 則乾蝕刻或濕蚀刻皆可使用。但是,假使是利用Cr形成傳 導層60,則應使用濕蝕刻來進行蝕刻動作,因爲乾蝕刻無 法完全移除Cr。在濕蚀刻的情況下,可使用CeNH03來作爲 蝕刻溶液。假使傳導層60是Mo或MoW,則可使用CF4和HC1 的混合物,或CF4和〇2的混合物來作爲蝕刻氣體。在後者的 情況下,傳導層和光致抗蝕膜的蝕刻比例相當接近。 因此,如圖27A和27B所示,只有源極/汲極傳導_案67 和儲存電容傳導圖案64會留下,且B區的傳導層60會全部移 -26- 本紙張尺度適用中國國家標準(CNS) A4规格(21〇χ297公釐)The hole 76 is physically and electrically connected to the drain 66 to receive a graphic signal. The pixel electrode 82 overlaps the adjacent gate and data lines 22 and 62 to increase the opening ratio, but the overlap can be controlled. Furthermore, the pixel electrode 82 may be connected to the storage capacitor pattern 64 through the contact hole 72 to transmit a graphic signal to the pattern. At the same time, auxiliary gates and data pads 84 and 88 are formed on the gates and data pads 24 and 68 so as to be connected to the gates and data pads 24 and 68 through the contact holes 74 and 78. Both the auxiliary gate and data fills 84 and 88 utilize external lines to enhance adhesion 'while protecting the gate and data fills 24 and 68. The auxiliary gates and data fills 84 and 88 may be used in a selective manner. A method of manufacturing a thin film transistor array substrate using a four-layer photomask will now be explained with reference to FIGS. 24A to 30 (:). As shown in FIGS. 24A to 24C, the substrate 10 is treated with oxygen plasma, and one of A conductive material with silver alloy as the main component is deposited on the substrate 10. Then, a layer with the conductive material as the main component is patterned by photolithography to form a gate line combination. The gate line combination includes gate lines 22, The gate filling 24, the gate electrode 26, and the storage capacitor electrode 28. As shown in FIGS. 25A and 25B, a gate insulating layer 30 mainly composed of silicon nitride, a semiconductor layer 40, and an ohmic contact layer 5 are shown. 10 are sequentially deposited on the substrate so as to have thicknesses of 1500-5000 A, 500-2000 A, and 300-600 A, respectively. The ohmic contact layer 50 is HF-treated and a conductive layer 60 containing a silver alloy is borrowed. The ohmic contact layer 50 is deposited by sputtering so as to form a thickness of 1500-3 000 A. A photoresist film i 10 covers the conductive layer 60 to a thickness of μm. At this time, the deposited gate The insulating layer 30 is preferably performed in an environment of 300 ° C or higher for five minutes. -24 -ΐPaper Standard Applicable Country Standard (CNS) M Specification (Fine M9? Public Love) 502382 A7 ___ B7_ 5. After the description of the invention (22), as shown in Figures 26B and 26C, the photoresist film 11 〇 Exposure to light through a reticle and developing it, thereby forming photoresist patterns n 2 and 114. At this time, the first photoresist pattern is located at the channel region 源 between the source and cathode electrodes 65 and 66. Regions 1 to 14 are established, the thickness of which is smaller than the second photoresist pattern region 112 above the data line combination. The remaining region b of the photoresist film is completely private. The first photoresist is located in the channel region C. The thickness ratio of the pattern area 114 and the second photoresist pattern area 1 丨 2 located in the data line combination area A should be different depending on the engraved condition. Preferably, the thicknesses of the first area 114 and the second area 112 The ratio is less than 1/2. For example, the thickness of the first region 114 can be established to be less than 4,000 A. The thickness of the photoresistive film may be different in each region. In order to control the light transmission on the data line combination region A, it may be Use a crack or grid pattern, or a translucent film. It is best that the width of the opening of the crack pattern is smaller than that exposed to light Decomposition ability of the device. In the case of translucent film, different light transmission or thickness can be used to control the light transmission. When light is irradiated on the photoresist film through the photomask, the macromolecules in the light exposure area will be full Decomposition 'and the photoresist film on the crack pattern or translucent film will also be partially decomposed. The photoresist film on the photoresist film will not be decomposed at all. When the photoresist film is developing 'The thickness of the remaining photoresistive film will be locally different. If the light exposure time is too long, all molecules may be decomposed. The photoresist film 114, which is relatively thin, can be reflowed. Production. General masks with transparent and opaque areas will appear. -25- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) '^ ----- 502382 A7 __B7 V. Description of the invention (Z3) Will be used to expose the photoresist film 114 with light. The photoresist film 114 is developed, and a reflow is generated on the photoresist film 114, so that the content of the photoresist film flows to the non-film area. Thereafter, the conductive layer 60, the ohmic contact layer 50, and the semiconductor layer 40 all use a photo-resistant I-worm pattern as a photomask. Therefore, the data line combination area A and the bottom layer are left in the data line combination area A. Only the semiconductor layer 40 is left on the channel area C, and only the insulating layer 30 is left on the remaining area B. For this purpose, as shown in FIGS. 27A and 27B, the conductive layer 60 exposed in the B region is removed while the underlying ohmic contact layer 50 is exposed to the outside. In this process, in the case where the conductive layer 60 is etched, dry etching or wet etching may be used while leaving the photoresist patterns 112 and 114 at the same time. However, if dry etching is used, which is usually used less often, the photoresist patterns 1 12 and 1 14 will be etched simultaneously. In this case, the thickness of the first photoresist pattern region 1 14 should be quite thick to avoid the entire removal of the first photoresist pattern region 1 14 while exposing the underlying conductive layer 60. If the conductive layer 60 is Mo or Mo W alloy, A1 or A1 alloy, or Ta, both dry etching and wet etching can be used. However, if the conductive layer 60 is formed using Cr, wet etching should be used for the etching operation, because dry etching cannot completely remove Cr. In the case of wet etching, CeNH03 can be used as an etching solution. If the conductive layer 60 is Mo or MoW, a mixture of CF4 and HC1 or a mixture of CF4 and O2 can be used as the etching gas. In the latter case, the etching ratios of the conductive layer and the photoresist film are quite close. Therefore, as shown in FIGS. 27A and 27B, only the source / drain conduction case 67 and the storage capacitor conduction pattern 64 will remain, and the conductive layer 60 in the B area will all be shifted to -26- This paper scale applies Chinese national standards (CNS) A4 size (21 × 297 mm)
除,同時曝露出底層的歐姆接觸層50。該傳導圖案64和67 有和資料線組合-樣的外觀’除了源極和没極65和66持續 展開沒有分開這個條件除外。甚至,在乾蝕刻的情況下, 光致抗蝕圖案1 12和114也會以相同的程度移除。 之後,如圖28A和28B所示,在B區曝露出來的歐姆接觸 層50,以及底層的半導體層4〇,同時透過乾蝕刻與第一光 致抗蝕圖案區114-起移除。此時,該蝕刻應在光致抗蝕圖 案112和114的條件下進行,該歐姆接觸層5〇和半導體層4〇( 半導體層和歐姆接觸層不選擇蝕刻方式)同步進行蝕刻'同 時留下該閘絕緣層3G。特別是,該光致抗㈣案112和114 和半導體層40的蝕刻比最好是相同。例如,該二層可使用 SF6和HC1的混合物或sh和〇2的混合物來蝕刻相同厚度。在 光致抗蝕圖案112和114以及半導體層40的蝕刻比相同的情 況下,第一光致抗蝕圖案區114的厚度應與半導體層4〇和歐 姆接觸層5 0的厚度總和相同或小於該總和。 因此,如圖28A和28B所示,在C區的第一光致抗蝕圖案 區114會移除,同時曝露出該源極/漏傳傳圖案67。在b區的 歐姆接觸層50和半導層40被移除,同時曝露底層的閜絕緣 層30。在A區的第二光致抗蝕圖案區112也受到蝕刻,同時 厚度減少。在此過程中,完成該半導體圖案42和48。參考 數字57和58分別指示〜位於源極/漏傳導圖案67下的歐姆接 觸圖案,以及位於儲存電容傳導圖案64之下的歐姆接觸圖 案。 源極/漏傳導圖案67上的剩餘薄膜藉由灰化方式移除。 -27- A7In addition, the underlying ohmic contact layer 50 is exposed at the same time. The conductive patterns 64 and 67 have a combination-like appearance with the data lines except for the condition that the source and imodes 65 and 66 are continuously expanded without being separated. Even in the case of dry etching, the photoresist patterns 112 and 114 are removed to the same extent. Thereafter, as shown in FIGS. 28A and 28B, the exposed ohmic contact layer 50 and the underlying semiconductor layer 40 in the B region are removed simultaneously from the first photoresist pattern region 114 by dry etching. At this time, the etching should be performed under the conditions of the photoresist patterns 112 and 114. The ohmic contact layer 50 and the semiconductor layer 40 (the semiconductor layer and the ohmic contact layer do not choose an etching method) are simultaneously etched while leaving behind The gate insulation layer is 3G. In particular, the etching ratios of the photoresistance patterns 112 and 114 and the semiconductor layer 40 are preferably the same. For example, the two layers can be etched to the same thickness using a mixture of SF6 and HC1 or a mixture of sh and O2. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first photoresist pattern region 114 should be the same as or less than the sum of the thicknesses of the semiconductor layer 40 and the ohmic contact layer 50. That sum. Therefore, as shown in FIGS. 28A and 28B, the first photoresist pattern region 114 in the C region is removed, and the source / drain pattern 67 is exposed at the same time. The ohmic contact layer 50 and the semiconducting layer 40 in the b region are removed, and the underlying holmium insulating layer 30 is exposed at the same time. The second photoresist pattern region 112 in the A region is also etched while the thickness is reduced. In this process, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 indicate ~ an ohmic contact pattern under the source / drain conduction pattern 67 and an ohmic contact pattern under the storage capacitor conduction pattern 64, respectively. The remaining thin film on the source / drain conduction pattern 67 is removed by ashing. -27- A7
之後,如圖29A和29B所示,在通道區C上的源極/漏傳導 圖案67和底層的歐姆接觸圖案57都透過蝕刻移除。乾敍刻 可適用所有源極/漏傳導圖案67和歐姆接觸圖案57。另外, 濕蚀刻可適用源極/漏傳導圖案67,且乾蝕刻適用歐姆接觸 圖案57。在前者的例子中,蝕刻最好在源極/漏傳導圖案67 和歐姆接觸圖案57的蝕刻選擇比很高的情況下進行。假使 触刻選擇比很低,則會很難找出蚀刻端點,同時很難控制 通道區C上所留下的半導體圖案42的厚度。例如,可使用 SF6和〇2的混合物來蝕刻源極/漏傳導圖案67。假使濕蝕刻 和乾蚀刻輪流使用,以濕蝕刻處理的源極/漏傳導圖案67側 區域會被蝕刻,但以乾蝕刻·處理的歐姆接觸圖案57則幾乎 不會蚀刻,結果產生階梯狀區域。CL和HC1的混合物或Cf4 和〇2的混合物可用來作爲蝕刻氣體。在使用cf4和〇2的混合 物時,最後產生的半導體圖案42可得到一致的厚度。如圖 22B所示,該半導體圖案42可局部移除,同時減少厚度。該 第二光致抗蝕圖案區112也進行了某種程度的蝕刻。此時, I虫刻可在未|虫刻閘絕緣層3 〇的情況下進行。光致抗蚀圖案 的厚度應相當地大以致在蝕刻第二光致抗蝕圖案區n 2時 不會曝露資料線組合。 因此,該源極和汲極65和66彼此分開,以完成該資料線 組和底層的歐姆接觸-圖案55、56和58。 最後,留在資料線組合區A上的第二光致抗蚀圖案區1 12 會被移除。但是,該第二光致抗蚀圖案區112可在移除通道 區C上的源極/漏傳導圖案67之後移除,同時留下底層的歐 -28 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) A7 B7 五、發明説明(26 ) 姆接觸圖案57。 如上所述,濕餘刻和乾I虫刻可交替使用,或僅使用乾蚀 刻。在後者的例子中,可以只使用一種蝕刻同時又能簡化 相關的處理步驟,但是很難找到正確的蝕刻條件。相反地 ,在前者的例子中,很容易就找到正確的蝕刻條件,但相 關的處理步驟較複雜。 同時可在250-500 c溫度下進行退火,以增加資料線組合 底層間的附著力。這類退火過程可在沈積資料線組合傳導 層之後直接進行,或在完成資料線組合之後進行。在出現 退火處理的情沉時,可省略HF處理過程。 在完成資料線組合之後,如圖3〇A和30B所示,氮化矽或 有機絕緣材料沈積在基板1〇之上,藉此形成一保護層7〇。 接著,该保1筻層70利用光罩和該閘絕緣層3〇蝕刻,藉此形 成接觸孔72、74、76和78,分別曝露該儲存電容傳導圖案 64、閘填充24、汲極66和資料填充68。 最後,如圖21至24所示,以ιζο或IT0爲主要成份、厚度 爲400-5 00 Α的層沈積在該基板10之上,並利用光罩,藉此 形成像素電極8 2、輔助閘填充$ 4和輔助資料填充8 。該像 素電極82連接至該汲極66和儲存電容傳導圖案64。該輔助 閘和資料填充84和88分別連接至閘和資料填充24和68。該 資料線組合和底層歐姆接觸圖案55、56和58和半導體圖案 42和48可以僅利用一光罩加以構成。在此過程中,該源$ 和没極65和66彼此分開,同時簡化了相關的處理步驟。 如上所述,在沈積傳導材料之前,該玻璃基板經過氧電 -29- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 502382 A7 五、發明説明(27 ) "" —一 -- 桌處理或孫以矽爲主要成份的層經過1117處理。甚至,該以 銀合金爲主要成份的導體層係沈積在該以矽爲主要成份的 層^並進行退火。以此方式,以銀和銀合金爲主要成份的 薄膜和玻璃基板或以矽爲主要成份的層之間的附著力,可 以增強。甚至,可最小化信號延遲,同時產生具有寬螢幕 和高解析度的液晶顯示。 本發明已參考若干較佳具體實施例詳細說明如上,本行 業的專家將明瞭本發明有不同的更改和替代方式而仍不脱 離本發明申請專利範圍内所提及之精神與範嘴。 ____ ·30- 本紙張尺度適财_家鮮(_ Μ規格(⑽χ撕公爱)Thereafter, as shown in FIGS. 29A and 29B, the source / drain conduction pattern 67 and the underlying ohmic contact pattern 57 on the channel region C are removed by etching. Dry engraving is applicable to all source / drain conduction patterns 67 and ohmic contact patterns 57. In addition, wet etching can be applied to the source / drain conduction pattern 67, and dry etching can be applied to the ohmic contact pattern 57. In the former example, the etching is preferably performed with a high etching selection ratio of the source / drain conduction pattern 67 and the ohmic contact pattern 57. If the etch-selection ratio is low, it will be difficult to find the etch endpoints, and at the same time it will be difficult to control the thickness of the semiconductor pattern 42 left on the channel region C. For example, a mixture of SF6 and O2 can be used to etch the source / drain conduction pattern 67. If wet etching and dry etching are used alternately, the area on the side of the source / drain conductive pattern 67 treated by wet etching will be etched, but the ohmic contact pattern 57 treated by dry etching will hardly be etched, resulting in a stepped area. A mixture of CL and HC1 or a mixture of Cf4 and O2 can be used as the etching gas. When a mixture of cf4 and O2 is used, the resulting semiconductor pattern 42 can have a uniform thickness. As shown in FIG. 22B, the semiconductor pattern 42 can be partially removed while reducing the thickness. The second photoresist pattern region 112 is also etched to some extent. At this time, the insect engraving can be performed without the insect engraving insulation layer 30. The thickness of the photoresist pattern should be so large that the data line combination is not exposed when the second photoresist pattern area n 2 is etched. Therefore, the source and drain electrodes 65 and 66 are separated from each other to complete the data line group and the underlying ohmic contact-patterns 55, 56 and 58. Finally, the second photoresist pattern region 1 12 remaining on the data line combination region A is removed. However, the second photoresist pattern region 112 can be removed after the source / drain conduction pattern 67 on the channel region C is removed, while leaving the underlying Euro-28-this paper size applies to the Chinese National Standard (CNS ) A4 specification (210X297 mm) A7 B7 5. Description of the invention (26) Contact pattern 57. As described above, the wet after-etching and dry I-etching can be used alternately, or only dry etching can be used. In the latter case, only one type of etching can be used while simplifying the relevant processing steps, but it is difficult to find the correct etching conditions. Conversely, in the former case, it is easy to find the correct etching conditions, but the related processing steps are more complicated. At the same time, annealing can be performed at a temperature of 250-500 c to increase the adhesion between the bottom layers of the data line combination. This type of annealing process can be performed directly after the deposition of the data line assembly conductive layer, or after the completion of the data line assembly. In the case of annealing, the HF treatment process can be omitted. After the data line assembly is completed, as shown in FIGS. 30A and 30B, silicon nitride or an organic insulating material is deposited on the substrate 10, thereby forming a protective layer 70. Next, the protection layer 70 is etched using a photomask and the gate insulation layer 30, thereby forming contact holes 72, 74, 76, and 78, respectively, exposing the storage capacitor conductive pattern 64, gate fill 24, drain 66, and Information fill 68. Finally, as shown in FIGS. 21 to 24, a layer having a thickness of 400-5 00 A with ιζο or IT0 as a main component is deposited on the substrate 10, and a photomask is used to form a pixel electrode 8 2. An auxiliary gate Fill it with $ 4 and supplementary stuff with 8. The pixel electrode 82 is connected to the drain 66 and the storage capacitor conductive pattern 64. The auxiliary gate and data fill 84 and 88 are connected to the gate and data fill 24 and 68, respectively. The data line combination and the underlying ohmic contact patterns 55, 56, and 58 and the semiconductor patterns 42 and 48 can be constructed using only a photomask. In this process, the source $ and Wuji 65 and 66 are separated from each other, while simplifying the relevant processing steps. As mentioned above, before the deposition of conductive material, the glass substrate was subjected to oxygen power -29- This paper size applies Chinese National Standard (CNS) A4 specifications (210X297 mm) 502382 A7 V. Description of the invention (27) " " — One-Table processing or Sun's silicon-based layer undergoes 1117 processing. Furthermore, the conductor layer mainly composed of a silver alloy is deposited on the layer mainly composed of silicon and annealed. In this way, the adhesion between a film mainly composed of silver and a silver alloy and a glass substrate or a layer mainly composed of silicon can be enhanced. Furthermore, signal delays can be minimized while producing a wide-screen and high-resolution LCD display. The present invention has been described in detail with reference to a number of preferred embodiments. Experts in the industry will understand that there are different modifications and alternatives to the present invention without departing from the spirit and scope mentioned in the scope of the patent application of the present invention. ____ · 30- The paper size is suitable for wealth _ home fresh (_ Μ specifications (⑽χ tear public love)
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2001
- 2001-04-13 KR KR1020010019874A patent/KR100750922B1/en active IP Right Grant
- 2001-06-01 TW TW090113508A patent/TW502382B/en not_active IP Right Cessation
- 2001-07-12 JP JP2001212621A patent/JP2002328629A/en active Pending
-
2002
- 2002-04-02 US US10/112,760 patent/US6867108B2/en not_active Expired - Lifetime
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2005
- 2005-02-10 US US11/053,833 patent/US7276731B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US7276731B2 (en) | 2007-10-02 |
US20020151174A1 (en) | 2002-10-17 |
US20050145844A1 (en) | 2005-07-07 |
JP2002328629A (en) | 2002-11-15 |
US6867108B2 (en) | 2005-03-15 |
KR100750922B1 (en) | 2007-08-22 |
KR20020079155A (en) | 2002-10-19 |
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