TW502375B - Manufacturing method of semiconductor device having different size of gate spacer - Google Patents

Abstract

A kind of method for manufacturing small-sized gate structure is disclosed in the present invention. The present invention at least contains the one double-layer spacer structure. A gate oxide layer is provided on the semiconductor substrate surface and a polysilicon layer is formed on top of the gate oxide layer. Then, a conducting layer is formed on the polysilicon layer and is followed by forming the first dielectric layer on top of the conducting layer. After that, the first photoresist layer is formed on top of the first dielectric layer and is followed by using an anisotropic etching manner to etch the photoresist layer, part of the first dielectric layer, the conducting layer, the polysilicon layer and the gate oxide layer so as to form an internal gate device and the peripheral gate device. In addition, the second dielectric layer is formed on the periphery of the internal gate device and the peripheral device. The third dielectric layer is formed on top of the second dielectric layer, and the fourth dielectric layer is formed on top of the third dielectric layer. Then, a photoresist layer is formed on the fourth dielectric layer of the internal gate device and an anisotropic etching method is used to etch the fourth dielectric layer of the peripheral gate device so as to form the second spacer of the peripheral gate device. Additionally, an anisotropic etching method is used to etch the third dielectric layer of the peripheral gate device so as to form the first spacer of the peripheral gate device. After that, the photoresist layer of the internal gate device and the fourth dielectric layer are removed. The fifth dielectric layer is formed on top of the third dielectric layer of the internal gate device. The fourth dielectric layer of the peripheral gate device and the second dielectric layer on top of the gate device surface are removed. The fifth dielectric layer is formed on the first dielectric layer and the third dielectric layer of the peripheral gate device, and a photoresist layer is formed on top of the fifth dielectric layer. Finally, the anisotropic etching method is used to etch the photoresist layer, the internal gate device for having semiconductor substrate bit line contact window, and the peripheral gate device for having gate bit line contact window as well as semiconductor substrate bit line contact window.

Description

V. Description of the Invention 〇 Field of the Invention: The present invention relates to a method for manufacturing a piece by a double-layer gap, especially a gate gap p, a structure of a side gate element, and / or an internal controllable structure. Gate element and peripheral parts. ① The thickness of the wall of the piece, and provide high-quality semiconductor elements 5 ~ 2 Background of the invention: Speed: t in the semiconducting? The demand for components is rapidly increasing due to the heavy use of electronic components. : The rapid spread of computers in the two special areas has increased the need to manufacture semiconductor components. Single: 3 ^ is a complex integrated circuit consisting of thousands of transistors. So the chip size is reduced and improved. Figure T shows a cross-sectional view of a conventional semiconductor device. The traditional constitutive pole structure is mostly ... " Xi 赚 ^ Touch window (bit-rirT is aligned twice to form a semiconductor substrate bit line to e to substrate ) In contact with the gate bit line (bit-line to gate). Traditional semiconductor devices are directly contacted (the bulkhead is mostly made of silicon nitride, which is a semiconductor substrate based on the semiconductor structure of a semiconductor substrate.) d. The size of the contact and the clearance of the surrounding gate elements

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Therefore, body components are urgently needed. This kind of semiconductor has fewer process steps and high-quality semiconductors. 5-3 Purpose and summary of the invention: In the evening review, there are many shortcomings of the existing semiconductor-Du Duo, the main purpose of the present invention is to It can control the internal gate element, and it has a three-layer gap wall structure, and provides a high-quality four-body K-pole element gap wall thickness. Another object of the present invention is to provide a semi-, tungsten silicide 2. The silicon dioxide layer has a gate structure and a double structure: a polycrystalline silicon can simultaneously form a semiconducting s-gap structure of the internal gate element, and its biHine t. substrate),; ^ Bottom: element line contact window (mt rhl. + τ +), surrounding gate bit lines • Gate bit line of two pieces: (blt-llne t0 gate) and bit line of semiconductor substrate bit line to substrate). It is still another object of the present invention to provide a thickness of a semiconductor gap wall for determining a gate size and length, and a semiconductor device connected to Erguya. In addition, another aspect of the present invention is to provide a semiconductor element having a layered spacer structure and an internal gate element for making a wider semiconductor substrate bit line contact window ( bit-line to substrate).

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V. Description of the invention (3) The above method has a gate conductive layer on the electrical layer and a dielectric layer, a conductive element, and a pole element dielectric. Next, using non-layers, isotropically forms a partial gate layer to form a side gate. The polar dielectric-dielectric dielectric layer has internal gate elements, and the polycrystalline spar is layered between the hair layer and the second crystal-engraved second-layer element. The fourth element is engraved on the periphery of the gate by the internal engraving method. The electrode layer and the gate element are dielectrically etched. After the fifth dielectric, Li worm engraves the gate position on the bottom surface according to the structure. . Then, a dielectric internal gate is formed above the conductive layer and the internal gate is formed above the second layer. Above the layer, the fourth dielectric and the fifth dielectric photoresist layer are removed by removing the inner five dielectrics and removing the fifth dielectric photoresist layer of the surrounding second element by using a dielectric layer and a double dielectric layer. , Formed in many parties. Immediately above the anisotropic layer, the multiple peripheral gates and the peripheral gates, a photoresist layer is etched isotropically to form the etching method. The light of the peripheral gate element is on the first layer of the internal element. Then the stratum and the top. Most gate elements are etched out of the wall structure. The silicon layer is formed on top, and a photoresist layer is used to etch and oxidize the gate. In the first periphery, the gate electrode of the multi-layered layer etches the first layer of the fourth dielectric member of the peripheral gate of the peripheral element. The three-mass layer and the dielectric layer above the dielectric layer are contacted with non-isotropic semiconductor element lines from the M, size gate junction. Furthermore, the semiconductor forms a first dielectric light based on the first dielectric layer above the gate oxide layer. The barrier layer and a partial first layer are used to form a second gap between a second dielectric and a third dielectric formed on the fourth interlayer element of the fourth side gate element of the third piece. Stratum. The dielectric layer gate element is formed on the periphery, forming a photo-cut square-shaped bit line window and a semiconducting layer to form the first gap wall of the layered dielectric dielectric member, and three dielectrics. On the top, the gate resistance layer on the surface is in contact with the form substrate.

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Bit line contact window. 5-4 is a simple illustration: the first schematic diagram, the third schematic diagram of the oxide oxide layer, the fourth schematic diagram, the fifth schematic diagram of silicon nitride, the sixth schematic diagram of the first layer, the layer formation into 0 A conventional cross-sectional view of a semiconductor device is known. The oxide layer, the polycrystalline silicon layer, the tungsten silicide layer, and the __ diagram of each step of the μ conductor element in the embodiment are formed by including a gate. This picture contains the inner picture. This picture contains the inner layer and the second picture. This picture contains the inner gap wall and the picture. This picture contains the peripheral gate of the central gate and the central gate of the Zhouming embodiment. The two-layer gap wall of the middle gate element and the second embodiment of the silicon dioxide layer in the embodiment show the formation of the semiconductor element and the side gate element of the semiconductor element side gate shape of the internal gate element in the embodiment. Formation of a photoresist layer of a semiconductor element. The 32nd step of the semiconductor element-the step of oxidizing stone. The seventh diagram of the moving silicon oxide layer, the light layer, and the photoresist layer of each step of the moving tetra-oxyethyl stone in each step of the peripheral gate element is a long history of the semiconductor device in the embodiment of the present invention. _ ^ τ V diagram of the moving you, which includes the semiconductor substrate bit line contact W (bi t -1 i ne to substrate) of the internal gate element, and the gate bit line of the peripheral idler element

No. 9 tribute 502375 V. Description of the invention (5)

Formation of a contact window (bit-line to gate) and a semiconductor substrate bit-line to substrate. Main part 100 120A 120B 140A 140B 160A 160B 180A 180B 200 220A 220C 220D 300A 300B 340A 340B 340C 10 12 Silicon substrate Internal gate element Peripheral gate element Internal gate element Peripheral gate element Internal gate element Peripheral gate element Internal gate element peripheral gate element Siqi ethyl stone layer internal gate element internal gate element peripheral gate element internal gate element peripheral gate element inside.卩 Gate perimeter of gate element Perimeter gate element perimeter of gate element silicon substrate gate oxide layer gate oxide layer polycrystalline silicon layer polycrystalline silicon layer tungsten silicide layer first stone dioxide layer The first silicon dioxide layer, the silicon nitride layer, the spacer wall, the third silicon dioxide layer, the third silicon dioxide layer, the semiconductor substrate bit line contact, and the semiconductor substrate of the gate bit line contact window Bit line contact window

Page 10 502375 V. Description of the invention (6) 1 2 A gate oxide layer of internal gate element 1 2B gate oxide layer of peripheral gate element 1 4 A polycrystalline silicon layer of internal gate element 1 4B polycrystalline silicon of peripheral gate element Layer 1 6 A tungsten silicide layer for internal gate element 1 6B tungsten silicide layer for peripheral gate element 1 8 A first silicon dioxide layer for internal gate element 1 8B first silicon dioxide layer for peripheral gate element 20A Silicon tetraoxide layer of internal gate element 20B Silicon tetraoxide layer of peripheral gate element 22A Silicon nitride layer of internal gate element 2 2 B Silicon nitride layer of peripheral gate element 22C Internal gate element Gap wall 22D Gap wall 24A Peripheral gate element Second silicon dioxide layer 24B Internal gate element Second silicon dioxide layer 26 Peripheral gate element Second photoresistive layer 28 Internal gate element Peripheral gate The shallow doped drain of the device 30 A The third silicon dioxide layer 30B of the internal gate element The third silicon dioxide layer 32A of the peripheral gate element The third photoresistance layer 32B of the internal gate element Semiconductor substrate bit of gate element in third photoresistive layer 34A Line contact window 34B Gate bit line contact window for peripheral gate components

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The semiconductor substrate bit line contact window 5 of the 34C peripheral closed-pole element is described in detail in the following: The seventh figure shows the semiconductor element Liu Yi to the sixth figure in the embodiment of the present invention, and the exploded two-side view L of the semiconductor element Among them, the same components are represented by the same reference numerals: Yu Ting Some second pictures show half-substrates; however, in the N-type silicon substrate furnace tube, the dry oxidation method The gate oxide layer of the oxide part (gate OX deposition method is used to deposit a thickness of about 2,000 layers on the surface of the 12 layer, with a thermal diffusion disk or arsenic, doped with the newly deposited °, and then using low pressure chemistry, more crystalline silicon, better silicide, tungsten 16 In addition, a low-pressure chemical vapor phase is used on the tungsten silicide 16, and the thickness of the photoresist is locally reduced to the photoresist on the first silica (1 8 stepper), and then the conductor substrate 10 is electrically conductive. The p-type can also be used. The Japanese-Japanese film is sent to the oxide to oxidize the silicon on the surface to a thickness of about 500,000 silicon. This silicon dioxide layer will be used as a semiconductor element. Next, the polycrystalline silicon with a low-pressure chemical vapor to 300 angstroms was used in a gate oxidation method or ion implantation method to reduce the resistivity of the gate by high-temperature polycrystalline silicon vapor deposition method. (LPCVD), which deposits and covers the polycrystalline silicon layer 14 with conductivity. The deposition method (LPCVD) deposits a layer of silicon nitride 18 at about 100 to 2000 angstroms. Next, the ytterbium layer is deposited, and an I line stepper (I 1 in ne exposure) is used to completely transfer the pattern on the photoresist to the photoresist etching.

Page 12 502375 V. Description of the invention (8) The second picture does not show the use of anisotropic truncation to describe the photoresist layer, local first silicon dioxide layer 18A & 18B, tungsten silicide 16A & 16B and The polycrystalline silicon layer 14A & 14B is used to form an internal gate element and a peripheral gate element. The fourth figure shows that the local gate oxidation layer is engraved in a non-respective way. Next, low pressure chemical vapor deposition (LpcvD) was used to deposit tetraoxoethyl silicon 20A & 20B with a thickness of about 100 to 300 Angstroms to form a layer of tetraoxoethylsilica 20A & 20B on the semiconductor substrate 10. Above the IgA surface of the first dioxide layer, the deposited tetraoxyethyl silicon 20A & 20B film has better step coverage capability. Next, chemical vapor deposition (CVD) was used to deposit nitride nitride 22A & 22B with a thickness of about 1,500 to 2500 angstroms to form a layer of titanium nitride 22A & 22B on the surface of tetraoxyethyl silicon 20A & 20B. on. Furthermore, the second silicon dioxide layer 24A & 24B with a thickness of about 1 5 QQ to 2 5 QQ angstroms is deposited by chemical vapor deposition (CVD) to form a layer of stone dioxide 24A & 24B On the surface of titanium nitride 22A & 22B. The fifth figure shows that the internal gate element is covered with a photoresist, and the peripheral gate element is etched by the self-align reacUve iQn etch. The second silicon dioxide layer 24B and the nitrided stone 2 2 β I are etched to form a first layer of the partition wall 2 4 C and a first layer of the partition wall 2 2 d. The thickness of the second layer of the partition wall 24C is approximately Between 500 and 600 angstroms, the thickness of the first partition wall 22D is between about 600 and 700 angstroms. Next, using the closed-electrode structure and the barrier wall as a photomask, shallow doped gate electrodes are formed on the peripheral semiconductor substrate.

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The sixth figure shows that the photolithium oxide layer 24A with the internal gate element removed. Next, a chemical vapor deposition method is used to form a silicon dioxide layer 30A & 30B on the internal gate element and the periphery = a second layer of silicon dioxide layer 30A on the internal gate element, Fractal and above the first layer of partition wall 22D of the surrounding gate. Tightly chaotic —, ', _2A The upper layer is first resisted (photoresist) on the internal gate element _ = _ and above the third gate layer of the surrounding gate element I line (I Ilne) stepper (stepper) performs local exposure exposure), so that the pattern on the photomask is completely transferred to the photoresist, and then, the touch of the line photoresist is used to define an internal gate Positions of bit line contact windows of pole elements and bit line contact windows of peripheral gate elements. The seventh figure shows that the photoresist layer and the third dielectric layer 30A & 30B are etched by using an anisotropic etching method, and the internal gate elements of the two gate electrodes & A line-to-substrate window (bit-line to substrate) 3 4 A is in contact with a gate bit line above the gate conductive layer of the surrounding gate element, and a bit-line t0 gate 34B is in contact with the semiconductor substrate bit line ® (bit-line to substrate) 34C. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following Within the scope of patent applications.

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Claims (1)

502375 VI. Application Patent Scope 1. A method for manufacturing a semiconductor device, comprising at least the following steps: providing a semiconductor substrate with a gate oxide layer on its surface; forming a polycrystalline silicon layer over the gate oxide layer; forming A conductive layer is over the polycrystalline silicon layer; a first dielectric layer is formed over the conductive layer; a first photoresist layer is formed over the first dielectric layer, and the photoresist layer is used to define a Internal gate and peripheral gate positions; Anisotropic etching is used to etch the first photoresist layer, the local first dielectric layer, the conductive layer, the polycrystalline silicon layer, and the gate oxide layer to form an internal gate element and a peripheral gate element. Two dielectric layers are formed around the internal gate and the surrounding gate structure; a third dielectric layer is formed above the second dielectric layer; a fourth dielectric layer is formed above the third dielectric layer Forming a second photoresist layer over the fourth dielectric layer of the internal gate element; Anisotropic etching is used to etch the fourth dielectric layer of the peripheral gate element to form a second spacer of the peripheral gate element; Anisotropic etching is used to etch the peripheral gate element. A third dielectric layer for forming a first spacer of the peripheral gate element; removing the second photoresist layer and the fourth dielectric layer of the inner gate element; forming a fifth dielectric Layer on the third dielectric layer of the internal gate element; Page 502 375 The formation layer and the third formation layer above the removal surface are used for the element-level utilization layer, the conductor base utilization layer, and the line contact window and the contact window. A third photoresist on the second gate dielectric, the fifth dielectric dielectric layer, and the peripheral gate defines an internal element line contact window. Non-specific etching. Internal gate element 70 line contact anisotropic etching. Peripheral gate element (the fourth dielectric layer of the bit-line element; a solid layer on the peripheral gate; a layer on the bit position of the fifth dielectric gate element; etching the third gate between the two gates The worm window (bi t-1i ne to etch the third conductive layer of the gate to substrate) is over the first dielectric layer of the gate element epitope element, and the photoresistive line is in contact with Gate gaps and semi-substrates are etched into the window and surrounding gate photoresist layer and the fifth dielectric; and gate bits and semiconductor substrate bit lines are etched over the photoresist layer and the fifth dielectric. The method for manufacturing a semiconductor device according to item 1 of the scope of the patent application, wherein the conductive layer includes at least tungsten silicide. 3. The method for manufacturing a semiconductor device according to item χ in the scope of the patent application, wherein the first dielectric layer described above includes at least silica. 4. The method for manufacturing a semiconductor device according to item 1 of the scope of the patent application, wherein the second dielectric layer includes at least tetra-ethyl-ortho-silicate. Page 16 502375 6. Scope of patent application 5 • The method for manufacturing a semiconductor device as described in item 1 of the scope of patent application, wherein the second dielectric layer described above contains at least element Shi and oxygen. 6. The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the third dielectric layer includes at least silicon nitride. The French method makes the product. The content of Yuan Si's solidification and oxygen-conducting half-second package includes the few items to the first layer, the first-level quality and electricity, Fan Jie Li, and the fourth one. The fragmentation of the elementary oxygen-conducting half-two encapsulation package includes the few items to the T-Η layer, the quality of the electrical circuit, Fan Jili's five-item application, and the application of the above-mentioned eight elements. The copper method, the method of making silicon elements, and the integration of silicon elements. The bottom half of the column contains the lesser items to the 1st floor and the first wall. Fan Jie Jinli Wuhe Specialist Bronze Silicon Requisition Is As above, 9. Zhong Su Di Li Fan Li Requisition As described above • Above ο China IX has at least as many layers as the law to create a component guide. Half-layer cuts and cut crystals have many items including: • Upper 1 in 11 11th Fan Li Zhuan Zhongzhong as described in as little as the wall gap, the method of making the law of the component element. The nitrogen item of the Chemical Research Institute includes the method of enclosing the components of the French-made parts. The Fan Li special application is applied as 2 tx page 17 502375. 6. The above-mentioned spacers in the scope of the patent application include at least oxidation. Silicon is a method for manufacturing a semiconductor device. At least one silicon substrate is provided, and the surface is covered with right U steps: 4 /, a gate oxide layer is on the surface; 70% of the silicon layer is over the gate oxide layer; A tungsten silicide layer is over the polycrystalline silicon layer; a first silicon dioxide layer is formed over the tungsten silicide layer; a first photoresist layer is formed over the first silicon dioxide reed square resistance layer is used to define-internal metal Gates and perimeters belong to Gate 2 in an anisotropic manner, the first photoresistive layer, local second-second: IT tungsten layer, polycrystalline silicon layer, and gate oxide layer are used to form 4 gate elements and peripheral gates. A pole element; forming a tetra-ethylmhh-si icate layer and the surrounding metal gate structure; forming a silicon nitride layer over the tetraoxyethyl silicon layer; forming A second silicon dioxide layer on the silicon nitride Over the layer; forming a second photoresist layer over the second SiO2 layer of the internal metal gate element; one, etching the first silicon oxide of the peripheral metal gate element by anisotropic etching Layer 'is used to form a second gap wall of the peripheral metal gate element; a silicon nitride layer of the peripheral metal gate element is etched by anisotropic etching to form a first layer of the peripheral metal gate element A gap; 13 · a photo-oxygen within the Page 18 502375 6. The scope of the patent application removes the silicon dioxide layer of the internal gate element above the first photoresist layer and the first stone layer of the internal gold; the stone oxide layer removes the surrounding metal gate A tetraoxoethene layer above the surface of the pole-closing element of the pole element; "a third silicon dioxide layer is formed over the i-side gated silicon layer and the silicon nitride layer; a second photoresist layer is formed in violation of The third photoresist layer is used to define the position of the bit line contact window of the metal gate element surrounding an internal metal gate element. The third optical silicon layer is etched by anisotropic etching. Bit gate line contact window of two-gate inter-etched semiconductor substrate (bit_line t〇 uses anisotropic etching to etch the third optical silicon layer, and the gate conductive layer bit line of the peripheral gate element is bit-line to gate) A contact window and a half bit-line to substrate) contact window. The nitrided oxide second layer, which is a gate element, is above the first metal oxide silicon of the gold electrode element, and the third bit line contact window and a resist layer. Engraving the gate gap with the third dioxide And substrate); and the gate layer and the base bit line of the gate conductor are etched over the resist layer and the third dioxide (14. The method for manufacturing a semiconductor device as described in item 13 of the patent application range, wherein the gate electrode includes at least One of the following: polycrystalline silicon, dish, kun and tungsten silicide 15. The method for manufacturing a semiconductor device as described in item 13 of the scope of patent application, 502375 Page 20