TW444339B - Method for forming self-aligned contact - Google Patents

Abstract

There is disclosed a method for forming self-aligned contact in a semiconductor device, which is capable of preventing the gate electrode and landing pad from leakage current or short circuit in a process with a smaller line width. The method comprises the steps of: first providing a substrate; forming a gate structure on the substrate, the gate structure comprising: a gate oxide layer on the surface of the substrate, a gate electrode on the gate oxide layer, a cap insulating layer on the gate electrode, and a spacer located on the side of the gate electrode and contacted with the gate electrode and the substrate via a buffer layer; then, forming a dielectric layer on the gate structure and on the substrate; forming a void passing through the dielectric layer to the surface of the substrate, the void is self-aligned with the surface of the substrate by the spacer, the surface of part of the spacer and the surface of part of the buffer layer are exposed out of the void; and finally, forming a passivation layer on the whole surface except the substrate in the void, including the exposed surface of part of the buffer layer.

Description

4443 3 9 V. Description of the Invention (1) · 5_1 Invention City: The present invention relates to a method for manufacturing semiconductor devices, and in particular, to a method for self-aligning contact windows in a dynamic random access memory scenario 5-2 BACKGROUND OF THE INVENTION: In the manufacturing process of dynamic random access memory (DRAM), 'including the formation of metal oxide semiconductor (MOS) transistors' before proceeding with important insulating layers, etching contact windows, and Formation process of interconnect structure. Self-aligned contact (SAC) technology is a well-known technology and is commonly used to form openings that connect a substrate to a < container. The self-aligned contact window uses an etching process to etch a dielectric layer between two identical elements to form an opening D. The above-mentioned elements are, for example, gates. This opening is usually connected to the substrate (SUbStrate) g by the top of the dielectric layer, or a

Pad). In addition, the formation of the opening can be made more precise by the guidance of the partition wall. The self-aligning contact window is formed before the formation of the contact window.

4443 3 9 V. Description of the invention (2) A gate structure π is formed on the substrate 10, wherein a gate electrode (electrode) 12 is provided with a silicon nitride layer 13 on the top as a cap insulating layer 'The side wall has a spacer 14 to protect its sides' and there is a buffer layer 15 between the spacer 丨 4 and the gate electrode 丨 2 and the substrate. The material of this buffer layer 15 is usually Oxide (ox ide). In order to isolate this gate structure from other unnecessary semiconductor components, a dielectric layer (cUelectric layer) such as borophospho-silicate glass (BPSG) is formed thereon, and its material is mainly oxide. See the second figure 'Then, the position of the contact window is defined by photolithography and silver etch processes, and the dielectric layer 16 is etched to form a hole 17. This etching process is only for oxides. The effect does not respond to the silicon nitride material, so the hole 17 will follow the guidance of the nitride nitride spacer 14 to the surface of the substrate 10, so that the process of self-aligning the contact window can be completed. Next, the native oxide on the surface of the substrate 10 in the hole 17 is usually removed by a cleaning process.

After the oxide etching and cleaning process described above, the oxide buffer layer J5 will be attacked by the reactant hydrogen fluoride (HF). In a process where the gate width is 0.25 micron (in m) or more, the thickness of the spacer 14 The oxide buffer layer 15 etched away does not significantly affect the structure and function of the overall device. However, today and before

Page 6 44433 9 V. Description of the invention (3) In the process of the smaller fields, such as the process of 0.18 micron and 0.15 micron, the width of the partition wall 14 is about 500 and 400 angstroms, respectively. After you engraved the cleaning process, the invaded silver portion of the oxide buffer layer 15 was relatively deeper, and even exposed the gate electrode. Under this structure, wait until the conductor (such as polycrystalline silicon) is filled in and aligned. After contacting the window, a large amount of leakage current between the gate electrode 12 and the conductor may occur, and even a short circuit ('short') may be formed. This will seriously damage the yield of the product. Based on the above reasons, it is necessary to develop a method of self-aligning the contact window 'to prevent the electronic leakage or short circuit between the gate electrode and the conductor in the self-aligning contact window in the smaller line width process, so as to Increasing the product yield of the process of moving the random access memory β "5-3 Purpose and summary of the invention: In view of the above-mentioned invention, the self-aligned contact window in the memory aims to prevent the gate electrode from or Short-circuit phenomenon. 'Many shortcomings of the traditional method of making dynamic random access memory. The electronic omission between the landing pad or the bit line according to the above purpose! ^, 士 总 _ ηη The present invention provides A method for forming a self-aligning contact window on a ZYYU push-pull male and female device in dynamic random access memory®, including at least the following

444339 -----_—— " ________ V. Description of the invention (4) A " "-Step by step 'provide a substrate first, and then form a gate structure on this substrate, this gate structure At least: a gate oxide on the surface of the substrate, a gate electrode on the gate oxide, 'a silicon nitride layer on the gate electrode, and a gasification stone gap wall on the side of the gate electrode' The nitride gap wall is indirectly in contact with the gate electrode and the substrate through an oxide buffer layer. Next, a dielectric layer is formed on the gate structure and the substrate; a hole is formed to penetrate the dielectric layer to the surface of the substrate, and the hole is self-aligned to the nitrogen of the substrate surface by the silicon nitride spacer. The surface of the sintered silicon wall and part of the surface of the oxide buffer layer are exposed in the hole. Finally, an “air-entrained dream layer” is formed on the surface of the oxide buffer layer on all surfaces of the pores except the substrate. Figure 5-4 is a simple explanation: The first and second figures show the traditional method of forming a self-aligning contact window. The second to seventh figures show the method for forming a self-aligned contact window provided by the present invention. The seventh circle shows the main features of the present invention. The eighth perimeter represents subsequent process steps in the field of the present invention. Representative symbols of the main parts: 10 substrate 11 gate structure 12 gate electrode

Page 84443 3 9 V. Description of the invention (5) 13 Cover insulation layer 14 Spacer wall 15 Buffer layer 16 Dielectric layer 17 Hole 100 Substrate 101 Gate oxide layer 102 Polycrystalline dream layer 103 Metal silicide layer 104 Cover insulation layer 105 Photoresist layer 106 Buffer layer 107 Spacer 108 Dielectric layer 109 Photoresist layer 110 Hole 111 ^ Protective layer ------- 112 Detailed description of the conductor 5-5 invention ... One embodiment of the present invention is based on dynamic The formation of self-aligned contact windows in random access memory is taken as an example. The invention is characterized in that the connection after etching and cleaning i ^ nn 4443 3 9 V. Description of the invention (6) A thin protective layer is deposited on the inner wall of the window hole to prevent the phenomenon of remote leakage or short circuit of electrons. The main steps of this self-aligning contact window process are detailed in reference to Section III. First, a substrate 100 is provided, in which all necessary processes in the substrate 100 must be completed, such as isolation, p-type wells and n-type wells. Etc. have been completed by traditional standard processes. These processes are not directly related to the present invention, such as subsequent source / drain regions and other processes implemented inside the substrate 100, so they will not be repeated here. A gate oxide layer 1 0 1 is formed on the surface of the substrate 100 by a conventional method, and then on the oxide latent 101 > a polycrystalline layer 102 is then formed. A metal silicide layer 103 is deposited on the ply_siUcon layer 102, and the composite layer formed by the two conductor layers is used as the gate electrode; then, the metal is silicided. A cap insulating layer 104 is formed on the object layer 103. The material can be silicon nitride (silicon nitride), which is used to isolate the gate electrode from other components above it. Next, a "phostoresist layer" 105 is formed on the covering layer 104, and then photolithography procedures such as exposure and development are used to illuminate the gate region. A pattern is defined on the photoresist layer 105, and this patterned photoresist layer is used as a #etching mask; then the unnecessary parts are removed by official engraving to form a gate shape, and then The photoresist layer 105 was removed. Referring to the fourth step, a thin buffer layer is deposited.

Page 10 4443 3 9 V. Description of the invention (7) (buffer layer) 106 on all surfaces, then deposit a layer of silicon nitride 107 on the buffer layer 106 'and then etch back two layers to complete The spacer of the gate can protect the sides of the gate electrode. The material of the buffer layer 106 is usually oxide, because the silicon nitride spacer 107 will generate great stress at high temperature. This may cause deformation or peeling, but if it is indirectly in contact with the gate electrode and the substrate 100 via the buffer layer 106, the stress can be mitigated. Referring to the fifth circle, after the gate structure is completed, a dielectric layer 108 is formed on the gate structure and the substrate 100 to isolate the gate from other components above. The main material of this dielectric layer 108 is The oxide can be selected from borophospho-silicateglass (BPSG) and other commonly used materials. Then, a photoresist layer 109 is formed on the dielectric layer, and the self-aligned contact window is defined on this photoresist layer 10 by exposure and development. The photoresist layer 109 is used as a mask. After the curtain is engraved with the oxide dielectric layer to form a hole by the engraving procedure, the structure of the photoresist layer 10 is removed as shown in Fig. 6A. This hole 110 penetrates the dielectric layer 108 to the surface of the substrate 100, and is self-aligned to the substrate 100 surface by the spacer 107. Part of the surface of the spacer jo? And part of the surface of the buffer layer 106 are exposed to the surface. Within the hole, the hole 110 is referred to as a self-aligned contact (SAC). A subsequent cleaning process uses hydrogen fluoride (HF) to clean the surface of the substrate 100 in the hole 110 to remove unnecessary raw materials.

4443 3 9 V. Description of the invention (8) Native oxide. After the above-mentioned dielectric layer (mainly composed of oxide) is etched and the native oxide is cleaned, the buffer layer i 06, which is also made of oxide material, which is located below the silicon wall of the nitride stone, will be invaded to avoid oxides. The erosion range of the buffer layer 106 leads to the phenomenon of electron leakage or short circuit between the gate electrode and the landing pad or bit line (especially when the thickness of the gap wall is very small). The following steps are as follows: As shown in FIG. 7, a protective layer 111 is deposited on all the surfaces in the hole 110, and then an etching back process is performed to remove a part of the protective layer 111 on the surface of the substrate 100 to expose the substrate 001. At this time, the protective layer 111 covers the eroded part of the buffer layer 106 without being exposed to the outside, and further ensures that the gate electrode is isolated from the outside. This protective layer 111 can be selected from silicon oxynitride (SiON) 'less stress due to heating' so as not to be affected by subsequent processes, and the thickness of the deposited layer is between 80 and 120 angstroms; Silicon nitride is used as the material of this protective layer ui, but it must be protected from the effects of thermal stress. Due to the implementation of the present invention, in the process of a trailing dynamic random access memory ship (DRAM), as shown in the eighth figure, a conductor 112 such as polycrystalline silicon is deposited in the hole 110 to complete a landing or bit. Element wire, this conductor will be smoothly connected to the substrate 100; and because of the barrier layer 111, there will be no remote leakage or short circuit of electrons with the gate electrode, which can improve the semiconductor with a smaller line width in the future Manufacturing yield in the component field.

Page 12 4443 3 9 V. Description of the invention (9) The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application for the present invention; all others do not depart from the spirit disclosed by the present invention. Equivalent changes or modifications completed shall be included in the scope of patent application described below.

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Claims (1)

4443 3 9 VI. Patent application group 1 · A forming method at least includes providing a substrate on the substrate, a gate oxide, a gate electrode on a silicon nitride layer, and an oxide interposed between a silicon nitride gap An object forms a hole in the surface of the gasified silicon gap and a silicon barrier wall; and an air surface is formed, which includes a random access memory to align itself with the square material of the contact window; a gate structure is formed on the gate; The electrode structure includes at least: a layer on the surface of the substrate, the gate oxide layer, the gate electrode, and a wall on the side of the gate electrode. The silicon nitride barrier wall is widely buffered with the gate. The electrode is in indirect contact with the substrate; the electrical layer is on the gate structure and the substrate; a hole penetrates the dielectric layer to the surface of the substrate, and the hole is aligned by the wall to the surface of the substrate by itself Part of the surface of the nitride and part of the oxide buffer layer is exposed to the surface of the oxide buffer layer of the hole oxide layer in the hole except for the substrate. 2. The method according to item 1 of the scope of patent application, wherein the above gate electrode includes at least a composite layer of a polycrystalline dream layer and a metal silicide layer. 3. The method of claim 1 in which the above-mentioned dielectric layer contains at least an oxide. '' For the method of applying for the first item of the patent scope, wherein the above-mentioned holes are the following Page 14 4443 3 9-^^^ ----# 'Applied to form a column method: forming a photoresist layer on the dielectric layer; aligning the self-aligned contact window with the exposure and development A pattern is defined on the piano resist layer; '^ the patterned photoresist layer is used as a mask' to etch the dielectric layer to form the hole by an etching process; and remove the photoresist layer. 5 'The method according to item 1 of the patent application range, wherein the above-mentioned nitrogen fossil layer is formed by depositing silicon oxynitride on all surfaces in the hole, and then oxidizing the nitrogen located on the surface of the substrate by an etch-back process. Silicon Removal "6. The method according to item 1 of the scope of the patent application, wherein the thickness of the oxynitride dream layer is about 80 to 120 angstroms. 7. A method for forming a self-aligned contact window in a semiconductor element, at least comprising: providing a substrate; forming a gate structure on the substrate, the gate structure including at least: a gate oxide layer On the surface of the substrate, a gate electrode is on the gate oxide layer, a cap insulating layer is on the gate electrode, and a gap wall is located on the side of the gate electrode. The gap is separated by a wide buffer 4443 3 9 VI. Indirect contact with the gate electrode and the substrate in the scope of Shenlong's patent; forming a dielectric layer on the gate structure and the substrate; forming a hole penetrating the dielectric layer to the On the surface of the substrate, the hole 4 is aligned with the surface of the substrate to the surface of the substrate, part of the surface & part of the buffer layer is exposed in the hole; and a protective layer is formed on the hole. All surfaces except the substrate include the exposed surface of the buffer layer. 8. The method according to item 7 of the scope of patent application, wherein the closed-electrode mentioned above comprises at least a composite layer of a polycrystalline stone layer and a metal hairpin layer. 9. The method of item 7 in the patent scope as described above, wherein the above-mentioned covering spacer includes at least silicon nitride 1 10. The method of claim γ of the patent scope, wherein the above-mentioned spacers contain silicon nitride β 11 The method according to item γ of the patent application, wherein the above buffer layer contains at least oxide β. The method according to item 7 of the patent scope, wherein the above dielectric layer includes at least oxide. 13. The method according to item 7 of the patent application park, wherein the above-mentioned dielectric layer is at least Page 16 4443 3 9 Including collar-filling stone filling (bpsg) »Among the above-mentioned pores are the following 14. The method and method described in item 7 of the scope of patent application are formed: forming a photoresist layer on the dielectric layer; exposure and development A pattern of self-aligned contact windows is defined on the light, and the photoresist layer masked by the dielectric is etched to form a mask, and the photoresist layer is etched to form the hole; and the photoresist layer is removed. 15. The method according to item 7 of the patent application, wherein the above-mentioned degree is between 80 and 120 angstroms. 16. The method according to item 7 of the scope of patent application, wherein the protective layer includes at least a silicon oxynitride layer. 17. The method according to item 16 of the scope of patent application, wherein the above-mentioned gas oxide layer is deposited by deposition. The silicon oxynitride is formed on all surfaces in the hole, and then the silicon oxynitride on the surface of the substrate is removed by an etch-back process. 18 ' The method of claim 7 in the scope of patent application, wherein said protective layer includes at least a silicon nitride layer. No. 17 Buy 4443 3 9 VI. Apply for patent Fangu 19. For the method of applying for patent No. 18, wherein the above silicon nitride layer is formed by depositing silicon nitride on all surfaces in the hole, and then using The etch-back procedure removes silicon nitride on the surface of the substrate. 11 ^ 11 Page 18