JP2008218727A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of applying larger distortion than in the case that a high stress nitride film is used for an MOS transistor channel region. <P>SOLUTION: The semiconductor device comprises a field effect transistor equipped with a gate structure 11 composed of a gate insulating film 12, a gate electrode 13, offset spacer films 15 formed on both sides in line width directions of the laminate of the gate insulating film 12 and the gate electrode 13, and a side wall film 16 formed outside the offset spacer film 15 formed at a specified position on a silicon substrate 10, and diffusion layers 17 formed near the surface of the silicon substrate 10 on both sides in the line width direction of the gate structure 11. The device also comprises a barrier layer 20 of metals formed on the side wall film 16 and the diffusion layer 17, and a stress application layer 21 of the metal formed on the barrier layer 20. The barrier layer 20 and the stress application layer 21 are insulated from the gate electrode 13 by the offset spacer film 15 and the side wall film 16. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a structure for imparting strain to a channel region and a method for manufacturing the same.

  Improvement in the current driving capability of field effect transistors (hereinafter referred to as MOS (Metal-Oxide Semiconductor) transistors) by reducing the channel length and reducing the thickness of the gate oxide film has become difficult due to miniaturization. In recent years, as a technique for improving the performance of MOS transistors in place of these techniques, a technique for giving distortion to the channel region of a MOS transistor has been proposed. This is to increase the carrier mobility and increase the current driving capability of the MOS transistor by applying mechanical strain to the channel region of the MOS transistor.

  FIG. 7 is a diagram illustrating a conventional example of a cross-sectional structure of a semiconductor device having a strained structure. As shown in this figure, the semiconductor device includes a gate structure 111 formed at a predetermined position on the silicon substrate 101, and a source / drain formed near the surface of the silicon substrate 101 on both sides of the gate structure 111 in the line width direction. The MOS transistor includes a diffusion layer 117 serving as a region. The gate structure 111 includes a stacked body of a gate insulating film 112 and a gate electrode 113 formed at a predetermined position on the silicon substrate 101, an offset spacer film 115 formed on both sides of the stacked body in the line width direction, And a sidewall film 116 formed further outside the offset spacer film 115. An extension portion 118 is formed in a shallow region on the channel region side of the diffusion layer 117. Silicide films 114 and 119 are formed on the gate electrode 113 and the diffusion layer 117. A high stress SiN film 130 is formed on the gate structure 111 and the diffusion layer 117.

  Here, in the case of an N channel type MOS transistor (hereinafter referred to as an NMOS transistor), the high stress SiN film 130 applies a tensile stress to the channel region, and the MOS transistor is a P channel type MOS transistor (hereinafter referred to as a PMOS transistor). In the case of a transistor), the high-stress SiN film 130 applies compressive stress to the channel region to enhance the current drive capability (see, for example, Non-Patent Documents 1 and 2). Note that the stress applied to the channel region is different even in the same SiN film 130 between the NMOS transistor and the PMOS transistor because the deposition conditions of the SiN film 130 formed in each transistor formation region are different.

S. Pidin, et al., "A Novel Strain Enhanced CMOS Architecture Using Selectively Deposited High Tensile And High Compressive Silicon Nitride Films", 2004, IEDM H. S. Yang, et al., "Dual Stress Liner for High Performance sub-45nm Gate Length SOI CMOS Manufacturing", 2004, IEDM

  As described above, in a semiconductor device currently under development, a high stress nitride film (SiN film) is mainly used as a strained Si technique. This nitride film is formed by the plasma CVD method, and the stress is improved by optimizing the film forming conditions and the film forming method and the curing technique using ultraviolet light. With this technology, it is now possible to apply a compressive stress close to about 2 GPa. However, a technique for applying a higher stress to the semiconductor device to be developed in the future is required. Therefore, there has been a problem that, for example, the thickness of the high stress nitride film has to be increased further. However, when the high stress nitride film is thickened, as shown in the region R of FIG. 7, the film thickness of the high stress nitride film (SiN film 130) on the diffusion layer 117 between the gate structures 11 increases. In this region R, it becomes difficult to form a contact hole for connecting to the upper layer wiring.

  The present invention has been made in view of the above, and has a strain larger than that in the case where a high-stress nitride film is used in the channel region of the MOS transistor, specifically, tensile stress in the channel region of the NMOS transistor. An object of the present invention is to obtain a semiconductor device capable of applying a compressive stress to a PMOS transistor and a manufacturing method thereof.

  In order to achieve the above object, a semiconductor device according to an embodiment of the present invention is a field effect transistor having a gate structure having a sidewall layer, wherein a metal film is formed in a space above a diffusion layer between adjacent gate structures. And a stress application layer made of a metal film. The barrier layer and the stress application layer are electrically insulated from the gate electrode by the sidewall film and the offset spacer film in the gate structure.

  According to one embodiment of the present invention, a higher tensile stress is applied to the channel region of the NMOS transistor and a higher compressive stress is applied to the channel region of the PMOS transistor than when a conventional high stress nitride film is used. Has the effect of being able to.

  Exemplary embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be explained below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments. The cross-sectional views of the semiconductor devices used in the following embodiments are schematic, and the relationship between the thickness and width of the layers, the ratio of the thicknesses of the layers, and the like are different from the actual ones.

Embodiment 1 FIG.
FIG. 1 is a diagram schematically showing a cross-sectional structure of a semiconductor device according to a first embodiment of the present invention. This semiconductor device has a structure in which a field effect transistor (hereinafter referred to as a MOS transistor) is formed at a predetermined position on a silicon substrate 10. This MOS transistor has a gate structure 11 formed at a predetermined position on the silicon substrate 10 and impurity atoms of a predetermined conductivity type formed on the surface of the silicon substrate 10 sandwiching a channel region below the gate structure 11. And a diffusion layer 17 to be a diffused source / drain region.

  The gate structure 11 includes a laminated body having a predetermined shape formed of a gate insulating film 12 made of a silicon oxide film or the like and a gate electrode 13 made of a polysilicon film on the silicon substrate 10, and the both sides of the laminated body in the line width direction. An offset spacer film 15 made of a silicon nitride film or the like to be formed, and a sidewall film 16 made of a silicon oxide film or the like formed further outside the offset spacer film 15 is constituted. Silicide films 14 and 19 made of nickel silicide or the like having a predetermined thickness are formed on the gate electrode 13 and the diffusion layer 17. An extension portion 18 in which impurities of the same conductivity type as the diffusion layer 17 are diffused is formed in a shallow region at the end of the diffusion layer 17 on the channel region side.

  On the sidewall film 16 and the silicide film 19 on the diffusion layer 17, a barrier layer 20 made of a laminated film of TiN (titanium nitride) / Ti (titanium) is formed. In the space between the adjacent gate structures 11, a stress application layer 21 embedded with W (tungsten) is formed. In order to prevent short-circuiting between the silicide films 14 on the adjacent gate electrodes 13 by the barrier layer 20 and the stress applying layer 21, the silicide film 14 is formed by an offset spacer film 15 and a sidewall film 16 formed of an insulating film. It is insulated from the barrier layer 20 and the stress applying layer 21 made of metal embedded between the gate structures 11.

  In this manner, by forming a metal film such as Ti, TiN, or W on the diffusion layer 17 between the gate structures 11, compressive stress or tensile stress can be applied to the channel region below the gate structure 11. Whether the compressive stress or the tensile stress is applied can be arbitrarily changed depending on the metal film production conditions (substrate temperature, pressure, film-forming power, etc.). For example, in the case of a TiN film, those produced at high temperature can apply tensile stress to the channel region, and those produced at low temperature can apply compressive stress to the channel region. In the case of a W film, those produced at a low temperature can apply a tensile stress to the channel region, and those produced at a high temperature can apply a compressive stress to the channel region.

  As the film stress of TiN, Ti, and W formed by sputtering or CVD, the stress shown below can be applied by changing the substrate temperature, pressure, and film formation power during film formation. A film having a stress of about 100 Mpa (tensile) to 50 GPa (compressed) with respect to TiN formed by the sputtering method and about 1 to 2.5 GPa (tensile) with respect to TiN formed by the CVD method can be obtained. Further, it is possible to obtain a film having a stress of about 100 Mpa (tensile) to 50 Gpa (compressed) with respect to Ti formed by sputtering, and about 100 Mpa (tensile) to 3 GPa (tensile) with respect to Ti formed by CVD. . Furthermore, a film having a stress of about 500 Mpa (tensile) to 5 Gpa (compressed) with respect to W formed by the sputtering method and about 100 Mpa (tensile) to 2.5 GPa (tensile) with respect to W formed by the CVD method is obtained. Can do. The stress value can be changed from a tensile stress to a compressive stress depending on the combination of film types (film forming conditions).

  Further, as shown in FIG. 1, since the barrier layer 20 and the stress applying layer 21 are made of a metal film, the silicide film 19 on the diffusion layer 17 serving as the source / drain region is connected to the upper wiring layer. In addition, the position to be the contact can be the upper surface of the stress application layer 21. That is, with the structure shown in FIG. 1, it is not necessary to form a contact hole up to the formation position of the silicide film 19.

  As a result, when an insulating film such as a nitride film is used as the barrier layer 20 or the stress applying layer 21, a thin film is required depending on conditions such as the ease of processing of the contact hole. In the case of using a metal film, the barrier layer 20 and the stress application layer 21 also serve as a contact, so that it is possible to use a thicker film than the nitride film. As a whole, high stress can be applied to the channel region.

  Next, a method for manufacturing a semiconductor device having such a structure will be described. 2A to 2C are cross-sectional views schematically showing the procedure of the semiconductor device manufacturing method according to the present invention. First, a MOS transistor is formed on the silicon substrate 10 by a known salicide process (FIG. 2-1). That is, a laminated body of a gate insulating film 12 and a gate electrode 13 having a predetermined shape is formed on the silicon substrate 10, and an offset spacer film 15 made of a silicon nitride film or the like is formed on both side surfaces in the line width direction of the laminated body. . The offset spacer film 15 has an L-shaped cross-sectional structure in contact with the side surface of the stacked body of the gate insulating film 12 and the gate electrode 13 in a plate shape and in the lower part thereof in contact with the surface of the silicon substrate 10 in a plate shape. Next, an extension portion 18 of a predetermined conductivity type is formed in a shallow region on the surface of the silicon substrate 10 using the laminate and the offset spacer film 15 as a mask, and then a sidewall made of a silicon oxide film or the like outside the offset spacer film 15. A film 16 is formed. Thereby, the gate structure 11 is formed. Thereafter, a metal film such as Ni (nickel) that reacts with the silicon substrate 10 to form silicide is formed on the silicon substrate 10 and heat-treated, so that the silicide film 14 is formed on the upper surface of the gate electrode 13 and the upper surface of the diffusion layer 17. , 19 is formed.

Next, a barrier layer 20 made of a TiN / Ti film is formed on the entire surface of the silicon substrate 10 on which the MOS transistor is formed by sputtering or CVD, and then at 300 ° C. in an N ₂ or NH ₃ atmosphere as necessary. Heat treatment is performed at a temperature of 600 ° C. or less (FIG. 2-2).

  Next, a stress applying layer 21 made of a W film is formed by sputtering, CVD, or a combination thereof (FIGS. 2-3). Thereafter, the surplus stress application layer 21 (W film) and the barrier layer 20 (TiN / Ti film) are etched back by CMP (Chemical Mechanical Polishing) using the silicide film 14 on the gate electrode 13 as a stopper or by dry etching. ) Is removed. As a result, the structure shown in FIG. 1 is obtained.

  Here, for example, in the case of an NMOS transistor, a tensile strain is required in the channel region by appropriately selecting the conditions for forming Ti, TiN, and W as the barrier layer 20 and the stress applying layer 21. It can be applied by stress. Similarly, in the case of a PMOS transistor, a compressive strain can be applied to the channel region with a necessary stress.

  According to the first embodiment, by forming a metal film between the gate structures under a predetermined condition, the value is larger than when a conventional insulating film or the like is used for the channel region under the gate structure 11. It is possible to apply a tensile stress or a compressive stress (strain).

  In addition, when an insulating film such as the SiN film 130 conventionally used is used as the stress application film, as shown in FIG. 7, when applying a large stress (strain) to the channel region, the stress application film It is necessary to increase the film thickness. When the film thickness is increased, in a fine device, for example, the nitride film (SiN film 130) is blocked on the silicide film 119 between the adjacent gate structures 111, and an upper layer is formed in a portion indicated by a region R in FIG. When a contact hole with a wiring is provided, it causes a defective opening of the contact hole. However, if the structure of the first embodiment is used, not only a sufficiently large stress (distortion) can be applied to the channel region, but there is no need to consider the contact hole opening defect between the adjacent gate structures 11.

Embodiment 2. FIG.
FIG. 3 is a diagram schematically showing a cross-sectional structure of the semiconductor device according to the second embodiment of the present invention. In this semiconductor device, in FIG. 1 of the first embodiment, the sidewall film 16 of the gate structure 11 is removed, and a barrier layer 20 made of a TiN / Ti film and a stress applying layer 21 made of a W film are also formed on the removed portion. Is formed. In addition, the same code | symbol is attached | subjected to the component same as FIG. 1, and the description is abbreviate | omitted.

  Also in the second embodiment, as in the first embodiment, the film formation conditions of the metal film constituting the barrier layer 20 and the stress applying layer 21 on the silicon substrate 10 (silicide film 19) between the adjacent gate structures 11 are similar. It is possible to apply tensile or compressive stress (strain) to the channel region under the gate structure 11 by appropriately selecting.

  Next, a method for manufacturing a semiconductor device having such a structure will be described. 4A to 4D are cross-sectional views schematically showing the procedure of the method for manufacturing the semiconductor device according to the present invention. First, a MOS transistor is formed on the silicon substrate 10 by a known salicide process (FIG. 4A). That is, a laminated body of a gate insulating film 12 and a gate electrode 13 having a predetermined shape is formed on the silicon substrate 10, and an offset spacer film 15 made of a silicon nitride film or the like is formed on both side surfaces in the line width direction of the laminated body. . The offset spacer film 15 has an L-shaped cross-sectional structure in contact with the side surface of the stacked body of the gate insulating film 12 and the gate electrode 13 in a plate shape and in the lower part thereof in contact with the surface of the silicon substrate 10 in a plate shape. Next, an extension portion 18 of a predetermined conductivity type is formed in a shallow region on the surface of the silicon substrate 10 using the laminate and the offset spacer film 15 as a mask, and then a sidewall made of a silicon oxide film or the like outside the offset spacer film 15. A film 16 is formed. Thereby, the gate structure 11 is formed. Thereafter, a metal film such as Ni (nickel) that reacts with the silicon substrate 10 to form silicide is formed on the silicon substrate 10 and heat-treated, so that the silicide film 14 is formed on the upper surface of the gate electrode 13 and the upper surface of the diffusion layer 17. , 19 is formed.

Next, the sidewall film 16 is selectively removed by dry etching or the like (FIG. 4-2). Thereafter, a TiN / Ti film is formed as the barrier layer 20 by sputtering or CVD (FIG. 4-3), and heat treatment is performed in an N ₂ or NH ₃ atmosphere at a temperature of 300 ° C. to 600 ° C. as necessary. . Next, a W film is formed as the stress applying layer 21 by sputtering, CVD, or a combination thereof (FIGS. 4-4). Then, the surplus stress applying layer 21 and the barrier layer 20 are removed by polishing using CMP or dry etching using the silicide film 14 on the gate electrode 13 as a stopper film. As described above, the structure of the semiconductor device shown in FIG. 3 can be obtained.

  According to the second embodiment, since the sidewall film in the gate structure is removed, a metal film having a volume larger than that in the first embodiment can be arranged in the space between the adjacent gate electrodes 13. This has the effect that a larger stress can be applied to the channel region.

Embodiment 3 FIG.
In the first and second embodiments, the gate electrode is not particularly described, but in the third embodiment, a case where a metal gate having a W / TiN / Ti structure is used as the gate electrode will be described as an example.

  FIG. 5 is a diagram schematically showing a cross-sectional structure of the semiconductor device according to the second embodiment of the present invention. In FIG. 3 of the second embodiment, this semiconductor device removes the gate electrode 13 made of the polysilicon film and the silicide film 14 of the gate structure 11 and embeds the gate electrode 13A made of the W / TiN / Ti film therein. It is characterized by that. More specifically, the gate electrode includes a barrier layer 20 made of a Ti / TiN film formed so as to be in contact with the offset spacer film 15 and the gate insulating film 12, and a stress application layer in which a W film is embedded in the internal space. 21. Further, the third embodiment is characterized in that silicide films 14 and 19 are not formed on the upper surface of the diffusion layer 17 and the upper surface of the gate electrode 13. The same components as those in FIGS. 1 and 3 are denoted by the same reference numerals, and the description thereof is omitted.

  Also in this third embodiment, as in the first and second embodiments, the film formation conditions for the metal film constituting the barrier layer 20 and the stress applying layer 21 on the silicon substrate 10 between the adjacent gate electrodes are appropriately selected. This makes it possible to apply tensile or compressive stress (strain) to the channel region under the gate electrode 13.

  Next, a method for manufacturing a semiconductor device having such a structure will be described. 6A to 6D are cross-sectional views schematically showing the procedure of the method for manufacturing the semiconductor device according to the present invention. First, a MOS transistor is formed on the silicon substrate 10 by a known process (FIG. 6-1). That is, a laminated body of a gate insulating film 12 and a gate electrode 13 having a predetermined shape is formed on the silicon substrate 10, and an offset spacer film 15 made of a silicon nitride film or the like is formed on both side surfaces in the line width direction of the laminated body. . The offset spacer film 15 has an L-shaped cross-sectional structure in contact with the side surface of the stacked body of the gate insulating film 12 and the gate electrode 13 in a plate shape and in the lower part thereof in contact with the surface of the silicon substrate 10 in a plate shape. Next, an extension portion 18 of a predetermined conductivity type is formed in a shallow region on the surface of the silicon substrate 10 using the laminate and the offset spacer film 15 as a mask, and then a sidewall made of a silicon oxide film or the like outside the offset spacer film 15. A film 16 is formed. Thereby, the gate structure 11 is formed.

  Next, the sidewall film 16 of the gate structure 11 is removed by a selective etching technique (FIG. 6-2). Here, since the offset spacer film 15 is formed of a silicon nitride film and the sidewall film 16 is formed of a silicon oxide film, the sidewall film 16 is removed by etching under the condition of etching only the silicon oxide film. Is possible.

  Subsequently, the gate electrode 13 of the gate structure is removed by a selective etching technique (FIG. 6-3). Here, since the gate electrode 13 is formed of a polysilicon film and the offset spacer film 15 is formed of a silicon nitride film, the gate electrode 13 is removed by etching under the condition of etching only the polysilicon film. Is possible. As a result, as shown in FIG. 6C, the offset spacer film 15 is erected on the silicon substrate 10.

  Next, a barrier layer 20 made of a TiN / Ti film is formed on the silicon substrate 10 by sputtering or CVD. At this time, the TiN / Ti film is formed on the side surfaces of the offset spacer film 15 upstanding on the silicon substrate 10, the gate insulating film 12, and the diffusion layer 17. Subsequently, a stress application layer 21 made of a W film is formed on the TiN / Ti film by sputtering, CVD, or a combination thereof. At this time, the stress applying layer 21 is formed such that the upper surface thereof is higher than the height of the offset spacer film 15 (FIG. 6-4).

  Thereafter, the stress application layer 21 and the barrier layer 20 are polished by CMP until the upper surface of the offset spacer film 15 is exposed, whereby the semiconductor device having the structure shown in FIG. 5 is obtained.

  According to the third embodiment, a high stress metal film and a metal gate are formed simultaneously by embedding a W / TiN / Ti structure between gate structures and further using a W / TiN / Ti structure metal gate as a gate electrode. I tried to do it. As a result, the manufacturing process of the semiconductor device can be simplified and the stress applied to the channel region portion of the silicon substrate 10 can be further increased.

  In the first to third embodiments described above, the manufacturing method of the same conductivity type MOS transistor has been described as an example. However, when the PMOS transistor and the NMOS transistor are provided on the same silicon substrate, the PMOS transistor The formation of the barrier film and the stress application layer in the formation region and the formation of the barrier film and the stress application layer in the NMOS transistor formation region may be performed separately. That is, when the barrier film and the stress application layer are formed in the PMOS transistor formation region, the mask is applied to the NMOS transistor formation region so that compressive stress is applied to the channel region of the PMOS transistor formation region. What is necessary is just to adjust the film-forming conditions of an application layer. In addition, when forming a barrier film and a stress application layer in the NMOS transistor formation region, the barrier film and the stress are applied so that a tensile stress is applied to the channel region of the NMOS transistor formation region by masking the PMOS transistor formation region. What is necessary is just to adjust the film-forming conditions of an application layer.

  In the first to third embodiments described above, the metal film embedded between the gate structures is a W / TiN / Ti structure, but this is an example, and any metal film can be used. For example, a TiN / Ti structure without a W film may be used.

  As described above, the semiconductor device according to the present invention is useful for a semiconductor device that requires a high-performance MOS transistor such as an advanced SoC (System on a Chip) or a nonvolatile memory.

It is a figure which shows typically the cross-section of Embodiment 1 of the semiconductor device by this invention. It is sectional drawing which shows typically the procedure of the manufacturing method of the semiconductor device by this invention (the 1). It is sectional drawing which shows typically the procedure of the manufacturing method of the semiconductor device by this invention (the 2). It is sectional drawing which shows typically the procedure of the manufacturing method of the semiconductor device by this invention (the 3). It is a figure which shows typically the cross-section of Embodiment 2 of the semiconductor device by this invention. It is sectional drawing which shows typically the procedure of the manufacturing method of the semiconductor device by this invention (the 1). It is sectional drawing which shows typically the procedure of the manufacturing method of the semiconductor device by this invention (the 2). It is sectional drawing which shows typically the procedure of the manufacturing method of the semiconductor device by this invention (the 3). It is sectional drawing which shows typically the procedure of the manufacturing method of the semiconductor device by this invention (the 4). It is a figure which shows typically the cross-section of Embodiment 2 of the semiconductor device by this invention. It is sectional drawing which shows typically the procedure of the manufacturing method of the semiconductor device by this invention (the 1). It is sectional drawing which shows typically the procedure of the manufacturing method of the semiconductor device by this invention (the 2). It is sectional drawing which shows typically the procedure of the manufacturing method of the semiconductor device by this invention (the 3). It is sectional drawing which shows typically the procedure of the manufacturing method of the semiconductor device by this invention (the 4). It is a figure which shows the prior art example of the cross-section of the semiconductor device which has a distortion structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 11 Gate structure 12 Gate insulating film 13 Gate electrode 14, 17 Silicide film 15 Side wall 16 Diffusion layer 21 Etching stopper film 22, 22A-22E Interlayer insulation film 23, 23A, 23E after hardening process Interlayer before hardening process Insulation film

Claims (12)

A gate insulating film formed at a predetermined position on a semiconductor substrate, a gate electrode patterned in a predetermined shape on the gate insulating film, and formed on both side surfaces in the line width direction of the stacked body of the gate insulating film and the gate electrode An offset spacer film, a gate structure having a sidewall film formed outside the offset spacer film, and a diffusion layer formed near the surface of the semiconductor substrate on both sides in the line width direction of the gate structure. A field effect transistor;
A metal film formed on the sidewall film and the diffusion layer;
With
The semiconductor device, wherein the metal film is insulated from the gate electrode by the sidewall film and the offset spacer film. A gate insulating film formed at a predetermined position on a semiconductor substrate, a gate electrode patterned into a predetermined shape on the gate insulating film, and both side surfaces in the line width direction of the stacked body of the gate insulating film and the gate electrode; A gate structure having an offset spacer film formed with a predetermined thickness on a part of the surface of the semiconductor substrate on both sides thereof, and a diffusion layer formed near the surface of the semiconductor substrate on both sides in the line width direction of the gate structure; A field effect transistor having
Side surfaces and upper surface of the offset spacer film, a metal film formed on the upper surface of the diffusion layer,
With
The semiconductor device, wherein the metal film is insulated from the gate electrode by the offset spacer film.   The semiconductor device according to claim 1, wherein the gate electrode is constituted by the metal film.   The semiconductor device according to claim 1, wherein an upper surface of the metal film on the diffusion layer has the same height as an upper surface of the gate electrode. Field effect transistors of different conductivity types are formed on the same semiconductor substrate,
The metal film of the first conductivity type field effect transistor applies compressive stress to the channel region below the gate structure, and the metal film of the second conductivity type field effect transistor corresponds to the channel below the gate structure. 5. The metal film of the first and second conductivity type field effect transistors is manufactured under different conditions so as to apply a tensile stress to the region. A semiconductor device according to 1. The metal film is
A barrier layer made of metal formed on the sidewall film and the diffusion layer;
A stress applying layer made of a metal formed on the barrier layer;
The semiconductor device according to claim 1, comprising:   The semiconductor device according to claim 6, wherein the barrier layer is composed of any one of a Ti film, a TiN film, and a laminated film of TiN and Ti.   The semiconductor device according to claim 6, wherein the stress application layer includes a W film. A gate insulating film formed at a predetermined position on a semiconductor substrate, a gate electrode patterned into a predetermined shape on the gate insulating film, and formed on both side surfaces in the line width direction of the stacked body of the gate insulating film and the gate electrode An offset spacer film, a gate structure having a sidewall film formed outside the offset spacer film, and a diffusion layer formed near the surface of the semiconductor substrate on both sides in the line width direction of the gate structure. A field effect transistor forming step of forming a field effect transistor;
A first metal film forming step of forming a first metal film having a predetermined thickness on the entire surface of the semiconductor substrate on which the field effect transistor is formed;
Forming a second metal film on the first metal film, the second metal film for applying a stress to the channel region under the gate structure so that an upper surface thereof is higher than a height of the gate structure; Process,
Removing the second metal film and the first metal film until the surface of the gate electrode is exposed;
A method for manufacturing a semiconductor device, comprising:   10. The semiconductor device according to claim 9, further comprising a sidewall film removing step of removing the sidewall film after the field effect transistor forming step and before the first metal film forming step. Manufacturing method.   11. The method of manufacturing a semiconductor device according to claim 10, further comprising a gate electrode removal step of removing the gate electrode after the sidewall film removal step and before the first metal film formation step. .   The step of forming the first and second metal films is performed for each of the field effect transistors of different conductivity types when field effect transistors of different conductivity types are formed on the semiconductor substrate. Item 12. A method for manufacturing a semiconductor device according to any one of Items 9 to 11.

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