TW501159B - Multilayer electrode structure and method for forming multilayer electrode structure for a flat panel display device - Google Patents

Multilayer electrode structure and method for forming multilayer electrode structure for a flat panel display device Download PDF

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Publication number
TW501159B
TW501159B TW090113225A TW90113225A TW501159B TW 501159 B TW501159 B TW 501159B TW 090113225 A TW090113225 A TW 090113225A TW 90113225 A TW90113225 A TW 90113225A TW 501159 B TW501159 B TW 501159B
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Taiwan
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layer
electrode
metal alloy
display device
scope
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TW090113225A
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Chinese (zh)
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Jueng-Gil Lee
Christopher J Spindt
Kishore K Chakravorty
Johan Knall
Matthew A Bonn
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Candescent Tech Corp
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Priority claimed from US09/588,115 external-priority patent/US6844663B1/en
Application filed by Candescent Tech Corp filed Critical Candescent Tech Corp
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Publication of TW501159B publication Critical patent/TW501159B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02Manufacture of electrodes or electrode systems
    • H01J9/022Manufacture of electrodes or electrode systems of cold cathodes
    • H01J9/025Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J29/00Details of cathode-ray tubes or of electron-beam tubes of the types covered by group H01J31/00
    • H01J29/02Electrodes; Screens; Mounting, supporting, spacing or insulating thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02Manufacture of electrodes or electrode systems
    • H01J9/14Manufacture of electrodes or electrode systems of non-emitting electrodes
    • H01J9/148Manufacture of electrodes or electrode systems of non-emitting electrodes of electron emission flat panels, e.g. gate electrodes, focusing electrodes or anode electrodes

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electrodes For Cathode-Ray Tubes (AREA)
  • Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

A multilayer electrode for a flat panel display device and a method for forming a multilayer electrode for a flat panel display device. In one embodiment, the multilayer electrode is formed by depositing a metal alloy layer. After the deposition of the metal alloy layer, the present embodiment deposits a protective layer above the metal alloy layer to form a multilayer stack. The present embodiment then subjects the multilayer stack to a cleansing process to remove contaminants. Subsequently, the present embodiment etches the multilayer stack to form the multilayer electrode for the flat panel display device. In another embodiment, the present invention provides a method for forming a multilayer stack with reduced formation of an intermetallic compound. In such an embodiment, the present embodiment deposits a first metal alloy layer above a substrate. Next, the present embodiment forms a barrier layer above the first metal alloy layer. In this embodiment, the barrier layer is adapted to prevent the formation of an intermetallic compound within the first metal alloy layer. Next, the present embodiment deposits a second metal alloy layer above the barrier layer. In so doing, the barrier layer also prevents the formation of the intermetallic compound within the second metal alloy layer.

Description

501159 五、發明說明(1) 本申請案為Lee et al· 於October 19, 1 999提出之 標題為"ELECTRODE STRCUTURE AND METHOD FOR FORMING ELECTRODE STRUCTURE FOR A FLAT PANEL DISPLAY"之 United States Patent Application Serial No. 09/421 ,781的延續案,並且本案亦與同時申請之標題為” DUAL- LAYER METAL FRO FLAT PANEL DISPLAY” 的United States Patent Application有相關性。 本發明係有關於一種平面顯示裝置,特別是有關於一 種用以形成一平面顯示裝置用之電極結構之成型方法。 [習知技術] 、 以顯示裝置中之平面顯示器為例,該平面顯示器中所 採用之陰極結構係形成於一背板之上,該陰極結構係包括 有複數列電極及複數攔電極,藉由複數列電極、複數欄電 極以啟動場射極(f ie Id emitters)之部分區域。由場射極 所發射出來的電子係直接移動朝向於該背板之上的像素 (pixel)或次像素區域(sub-pixei regi〇ns),並且在選擇 性啟動列電極及攔電極的情況下係可使得該電子直接撞擊 於該像素或次像素區域。一般而言,於該面板之内側面上 係沉積有一磷層,當該電子撞擊於該磷層時將可以產生 紅、綠或藍之可見光,進而藉由該紅、綠或藍之可見光以 形成一可見圖像(visible display)。 藉由銘層以形成列電極及攔電極係為習知技術中所常 見的方法,然而在鋁廣上係相容易形成凸起物(hi丨1〇ck) ’這些凸起物除了影響結構之平整性之外,亦會造成列電501159 V. Description of the invention (1) This application is Lee et al. The title of the application filed in October 19, 1999 is " ELECTRODE STRCUTURE AND METHOD FOR FORMING ELECTRODE STRUCTURE FOR A FLAT PANEL DISPLAY " United States Patent Application Serial No. The continuation of 09 / 421,781, and this case is also related to the United States Patent Application entitled "DUAL-LAYER METAL FRO FLAT PANEL DISPLAY". The present invention relates to a flat display device, and more particularly, to a method for forming an electrode structure for forming a flat display device. [Known technology] Take a flat display in a display device as an example. The cathode structure used in the flat display is formed on a back plate. The cathode structure includes a plurality of rows of electrodes and a plurality of barrier electrodes. The electrodes of the plurality of columns and the electrodes of the plurality of columns are used to activate a part of the field emitters. The electron system emitted by the field emitter moves directly toward the pixel or sub-pixel region (sub-pixei regins) above the backplane, and when the column electrode and the barrier electrode are selectively activated The system can cause the electrons to directly impact the pixel or sub-pixel area. Generally speaking, a phosphor layer is deposited on the inner surface of the panel. When the electrons impinge on the phosphor layer, visible light of red, green, or blue can be generated, and then formed by the visible light of red, green, or blue. A visible display. It is a common method in the conventional technology to form a column electrode and a barrier electrode system by using a layer. However, it is easy to form protrusions on the aluminum phase. These protrusions affect the structure in addition to In addition to flatness, it will also cause electricity

第7頁 1012-4065-PF ; ALEX.ptd .. 501159Page 7 1012-4065-PF; ALEX.ptd: 501159

極及攔電極之間的短路現象。 …於另一習知技術中係採用將一钽層形成於該鋁層之上 以減少凸起物的形成。然而,由鈕層所形成的結構係在大 型1平板顯示器中具有相當低的導電性,亦即,該鈕層於 大型的平板顯示器之列電極或欄電極上形成相當大的1抗 因而由组層所形成的結構僅能適用於小型的平板顯示哭 =上述具有鈕層之該鋁層之結構中,其成型方式係首 ,3銘層,冗積形成於一賤鍍室(sputtering chamber)中 ^ ί Ϊ板上,並且在該鋁層的沉積作業完成後便可將該背 J移”職錢室。隨後’對…層進行罩幕作業,並1 溼蝕^:積形成於該背板上以進行曝光作業,進而藉由 結:序對於該銘層進行触刻,如此便可形成所欲的紹 之沉積作業將-第二濺鍍室之中以進行叙層 板移出㈣鍍室,=後背 沉積形成於該背板上且推一 s、μ ^皁眷作菜在將一光阻 .以對於該鈕層進行蝕刻。=二考作業之後,藉由蝕刻程序 蝕刻作業,一般係採用 ;溼蝕刻無法對於該鈕層進行 heme iQn ^或是藉由反應離子餘刻 了相當地耗i成本Ϊ: C冗:步驟及兩次罩幕步驟除 過量〇均無法有以於=之 501159 五、發明說明(3) 所形成之具有陡靖壯 脆裂。 1電極或欄電極將會造成該叙層之 再者,ϋ由乾飿刻方式亦是 時,乾蝕刻過程將會經由針孔而侵蝕=:孔(了。丨es. 只〜用 间成本之尚分子帶裎床 bdymer Strip process)對於該高分子進行移除##The short circuit between the electrode and the barrier electrode. ... In another conventional technique, a tantalum layer is formed on the aluminum layer to reduce the formation of protrusions. However, the structure formed by the button layer has a relatively low conductivity in a large flat panel display, that is, the button layer forms a relatively large primary reactance on the column electrode or the column electrode of the large flat panel display. The structure formed by the layers can only be applied to small flat panel display. In the structure of the aluminum layer with the button layer described above, the molding method is first, 3 layers, and redundantly formed in a sputtering chamber. ^ Ϊ the plate, and after the deposition of the aluminum layer is completed, the back can be moved to the office. Then 'the curtain layer operation is performed on the layer, and 1 wet etching is formed on the back plate. The exposure operation is performed on top, and then the inscription layer is sequentially etched by the knot, so that the desired deposition operation can be formed. The second sputtering chamber is used to move the layering board out of the ㈣ plating chamber. = The back deposit is formed on the back plate and pushed for one s, μ ^ Soap is used as a dish, and a photoresist is used to etch the button layer. = After the second examination operation, the etching operation is performed by an etching program, which is generally used. ; Wet etching cannot perform heme iQn ^ or borrow on this button layer The considerable cost of i is due to the remaining ion ions: C redundant: the steps and the two masking steps are not excessive except for 501159. V. Description of the invention (3) It has a steep and strong crack. 1 electrode or fence electrode will cause this layer to be repeated, and the dry etching process is also the case, the dry etching process will be eroded through the pinhole =: 孔 (了. 丨 es. Only the cost of use Zhishang molecular band process (bdymer Strip process) to remove the polymer ##

,於乾蝕,過程中亦會於該玻璃〜背板上形成針孔。 在後續的製程步驟中,該攔電極將可能在離子揸 (1〇n bombardment)、凹部蝕刻(cavity etch)、錐體冗 (cone deposition)、介電沉積(dielectric '、 deposition)、介電層之遮罩與蝕刻、鉬層之沉積與蝕刻 、鉻層之沉積與蝕刻、聚醯亞胺沉積等過程中受到破壞, 並且在這些過程中除了可能會形成電極的短路、開路之外 ,同時也可能會降低產品良率及裝置的故障。 習知技術中所產生的另一問題在於欄位至聚焦格子短 路(column to focus waffle short),該欄位至聚焦袼子 短路之現象將可能造成產品良率的降低及裝置的故障之外 ,攔位電極將與熔塊密封區域(frit seal regi〇n)之溶塊 密封材料之間產生反應,如此則可能形成攔電極之間的短 路。 因此’在電極結構及其成型方法中除了必須避免凸起 III ! 1 II 1 I 1 11 ί 1 I 1012-4065-PF ; ALEX.ptd 第 9 頁 」In the dry etching process, pin holes are also formed in the glass ~ back plate. In the subsequent process steps, the barrier electrode may be in ion bombardment, cavity etch, cone deposition, dielectric ', deposition, and dielectric layer. It is damaged during the process of masking and etching, molybdenum layer deposition and etching, chromium layer deposition and etching, and polyimide deposition. In addition to these processes, in addition to the possible short-circuit and open-circuit of the electrode, May reduce product yield and device failure. Another problem that arises in the conventional technology is the column to focus waffle short. The phenomenon of the column to focus waffle short may cause a decrease in product yield and device failure. The stop electrode will react with the frit seal material of the frit seal region, so a short circuit between the stop electrodes may be formed. Therefore, in addition to the electrode structure and its forming method, it is necessary to avoid the protrusion III! 1 II 1 I 1 11 ί 1 I 1012-4065-PF; ALEX.ptd page 9 ”

物的產生及符合上述要件 不當短路、開路等現象, 品可保有既定的良率及品 之外,亦要能夠效降低電極間之 同時在符合最低成本下以使得產 質0 習用技 行多層電極 (oxidizing 並且該多層 構。然而, 層疊狀物產 可能形成過 必須在精確 及過度I虫刻 習用技 之多層電極 即,於該標 層係可與所 一化合物係 並且隨著其 氧化及钕刻 、夂後續氧化 因此, 合物的生成 :1ί另箆:〒係在於藉由兩次蝕刻步驟來進 、生產。第一乂蝕刻步驟係藉由氧化劑The production of products and the phenomenon of improper short circuit and open circuit in accordance with the above requirements, the product can maintain the established yield and product, and it must also be able to effectively reduce the electrode space and meet the minimum cost to make the product quality. (oxidizing and the multilayer structure. However, the laminate may have formed a multilayer electrode that must be used with precise and excessive techniques, that is, the target layer can be combined with the compound system and with its oxidation and neodymium engraving,夂 Subsequent oxidation, the formation of the compound: 1 箆 Another: 〒 is based on the production and production through two etching steps. The first etch step is through an oxidant

以對於一多層疊狀物進行氧化處理, 在餘刻劑的作用下形成多層電極結 决、二f料及特定的環境下將可能會造成該多 二二:化現象,並且此一過度氧化現象亦 ^ ^現的產生。因此,電極之成型過程係 白、蝕刻控制下進行,如此以避免因為過度氧化 =可能造成之”開路”或斷路現象的產生。Oxidation treatment of a multi-layered object, the formation of multi-layer electrode junctions under the action of the etchant, the second material, and the specific environment may cause the phenomenon of multi-layered: 2, and this excessive oxidation phenomenon is also ^ ^ Present generation. Therefore, the electrode forming process is performed under white and etching control, so as to avoid “open circuit” or disconnection due to excessive oxidation.

術中之又一缺點係為於標準真空環境中所進行 的成型過程中會有金屬間化合物的生成,亦 準真空環境中所形成之多層疊狀物中的兩金屬 生成,金屬間化合物之間形成電性的連接。此 由於忒兩金屬層之原子與分子的擴散所形成, 所包含金屬間化合物之成分大小將明顯地影響 之速率。因此,金屬間化合物的生成將可能導 及蝕刻的改變及不可預期的結果。 在多層電極及其成型方法中必須避免金屬間化 出改有二Another disadvantage in the operation is that during the forming process in a standard vacuum environment, intermetallic compounds will be formed, and the two metals in the multi-layered layer formed in the vacuum environment will be formed, and the intermetallic compounds will be formed. Electrical connection. This is due to the diffusion of atoms and molecules between the two metal layers, and the size of the components of the intermetallic compounds contained will significantly affect the rate. Therefore, the generation of intermetallic compounds may lead to changes in etching and unpredictable results. Interlayer metal must be avoided in multilayer electrodes and their forming methods

、發明說明(5) ==、、、σ構上係不存在有凸起物,並且在陰極結構中不會形 :,性的短路或開路現象,同時在符合最低成本下係可以 便侍所產品保有既定的良率及物料通過量。 Μ 於本發明之一實施例中所提出之平板顯示用之電極結 ΐ:^括有底部電極及頂部電極,於本實施例中之該底部 带° ,,列電極,而該頂部電極係為欄電極,並且該底部 二f /、該頂部電極之間係由一阻層及一介電層所分隔。於 :I施例中之該底部電極與該頂部電極係由一金屬合金所 ^ 士,並且於一實施例中之該金屬合金係為一鋁合金或銀 於冬發明所提 層電極的方法中, 後將一夾合層沉積 刻步驟以形成—電 知技術而言,本發 沉積係依序於一賤 、增加良率及提高 •^罩幕步驟及餘刻 電極結構僅藉由單 ,如此可有效地降 由於本發明並 型,除了可以省去 不會對於底部銘層 面板的損傷(例如: 出之用以形成一平 首先係沉積一金屬 於該金屬合金層之 極層。相較於必須 明所提出之該金屬 鍍工具中進行,如 物料通過量。再者 步驟之習知技術而 一罩幕步驟及單一 低成本 '增加良率 不需採用乾蝕刻程 相關於乾蝕刻設備 產生腐蝕現象,同 針孔(pinholes)) 面顯示裝置 合金層於一 上,繼而藉 藉由兩濺鍍 合金層與該 此可有效地 ,相較於必 言,本發明 溼蝕刻步驟 及提高物料 序來進行列 之外,於製 時亦不會造 ,並且更不 用之一多 背板’隨 由一溼餘 工具之習 夾合層之 降低成本 須藉由兩 所提出之 即可完成 通過量。 電極之成 作過程中 成該玻璃 必進行聚、 Explanation of the invention (5) == ,,, σ There are no protrusions on the structure, and it will not be shaped in the cathode structure: sexual short circuit or open circuit phenomenon, and at the same time, it can be used in the clinic at the lowest cost. The product has a predetermined yield and material throughput. The electrode structure for flat panel display proposed in one embodiment of the present invention: ^ includes the bottom electrode and the top electrode, in this embodiment, the bottom band is a column electrode, and the top electrode is Fence electrodes, and the bottom two f / and the top electrodes are separated by a resistive layer and a dielectric layer. In: I, the bottom electrode and the top electrode are made of a metal alloy, and in an embodiment, the metal alloy is an aluminum alloy or silver Then, a sandwich layer is deposited and etched to form—in terms of electrical knowledge technology, the deposition of the hair is in order to increase the yield and improve the order of the masking step and the remaining electrode structure. It can be effectively reduced due to the combination of the present invention, in addition to omitting damage to the bottom surface layer panel (for example: used to form a flat electrode system that first deposits a metal on the metal alloy layer). The metal plating tool proposed by Ming Dynasty, such as the material throughput, and the conventional technique of the step and a mask step and a single low-cost 'increasing the yield without using a dry etching process is related to the corrosion phenomenon of the dry etching equipment. The same pinholes) surface display device alloy layer on one, and then by two sputtered alloy layer and this can effectively, compared with must, the present invention wet etching step and improve material order In addition to carrying out the process, it will not be produced during the manufacturing process, and it does not need a lot of back plates. With the practice of a wet tool, the cost of the sandwich layer can be reduced by two proposals. During the formation of the electrode, the glass must be gathered during the formation of the electrode.

501159 五、發明說明(6) 合物帶程序(polymer strip process),如此係有助於物 料通過量之增加及良率之提昇。 於一實施例中,一鈍化層(paSSiVati〇n layer)係藉 由沉積方式形成於該頂部電極之上’於本實施例中之該曰純 化層係藉由氮化矽材料所製成,隨後便對於該氮化矽層進 行罩幕及蝕刻程序,如此便可使得部分的氮化矽層覆^於 該頂部電極之上,並且藉由該部分的氮化矽層以防止二頂 部電極於後續製程中不受到損壞。 、 隨後,藉由沉積方式所形成之一閘極金屬 metal)係在遮罩、蝕刻步驟下形成了一閘極結構 structure),並且於沉積、遮罩及蝕刻程序中係藉由該鈍 化層對於該頂部電極進行保護,隨後便可藉由一般的製程 步驟以形成一完整陰極結構。於一實施例中,藉由這^製 程步驟係可以形成複數射極(e m i ^ ^ e r s)及一聚焦於才^ (focus structure),並且於本實施例之這些製、程°步驟中 係包括有離子撞擊(i〇n bombardment)、凹部蝕刻(ah etch)、錐體沉積(cone deposition)、介電沉積 (dielectric deposition)、介電層之遮罩與蝕刻、聚醯 .亞胺沉積等。在陰極結構之成型期間,該頂部電極係藉由 該鈍化層所保護,如此可避免該頂部電極於一般製程^ 中受到破壞,並且可以防止該頂部電極之短路及^陷二產 生。此外,由於該頂部電極受到該鈍化層的保護,如此 可避免於熔塊密封區域(frit seal regi〇n)之中形成攔短 路(column shorts),並且本實施例在相較於習知技術下501159 V. Description of the invention (6) Polymer strip process. This is to help increase the throughput and yield of the material. In an embodiment, a passivation layer (paSSiVation layer) is formed on the top electrode by a deposition method. In this embodiment, the purification layer is made of a silicon nitride material, and then Then, the silicon nitride layer is masked and etched, so that part of the silicon nitride layer is covered on the top electrode, and the part of the silicon nitride layer is used to prevent the two top electrodes from being subsequently No damage during manufacturing. Then, a gate metal formed by a deposition method is formed under a masking and etching step, and a gate structure is formed under the masking and etching steps. The top electrode is protected, and then a complete cathode structure can be formed through general process steps. In one embodiment, a complex emitter (emi ^ ^ ers) and a focus structure can be formed by this process step, and the steps of these processes and processes in this embodiment include There are ion bombardment, ah etch, cone deposition, dielectric deposition, masking and etching of dielectric layers, polyimide, and imine deposition. During the formation of the cathode structure, the top electrode is protected by the passivation layer, so that the top electrode can be prevented from being damaged in the general process ^, and the short circuit and depression of the top electrode can be prevented. In addition, since the top electrode is protected by the passivation layer, column shorts can be prevented from being formed in the frit seal regiron, and this embodiment is compared with the conventional technology.

501159501159

五、發明說明(7) 係具有較少的曝光金屬, 袼子金屬的短路現象。 、可以減少攔相對於該聚焦 由於銘合金或銀合金係具 或銀合金係可適用於大:之電性,該鋁合金 技術,本發明係可防止在。相較於習知 得該鋁合金具有良好的平整'14 :同日;除了;物’如此以使 極的短路、開路之外…以有效提昇】以免形成電 -多層電極的結構及其方法;:::;::::裝置用之 f可以避免形成電極的短路、開路之外,㈤時可:J = 幵產品良率及物料通過量。 有放提 於本發明之另一實施例中所提出之用以形成一平面顯 不裝置用之一多層電極的結構及其方法中係可以減少非必 要之過度氧化現象的形成,同時更可避免”開路,,或破穸 象的產生。更特別的是,在完成一金屬合金層之沉積彳^, 進而沉積一保護層於該金屬合金層之上以形成一多層疊狀 物。隨後’指定該多層疊狀物經由一清潔程序移除污染 物,如此便可在餘刻該多層疊狀物之後形成了該平面顯示 裝置用之該多層電極。 μ μ 於另一實施例中,本發明所提出之用以形成一平面顯 示裝置用之一多層電極的結構及其方法中係可在電極的成 型過程中不會產生金屬間化合物。於該實施例中係先沉積 一第一金屬合金層於一基底,其次形成一阻層於該第一金 屬合金層之上’該阻層係用以防止該第一金屬合金層内之V. Description of the invention (7) It is a short-circuit phenomenon with less exposure metal and metal. It can reduce the focus relative to the focus. Because the alloy or silver alloy system or silver alloy system can be applied to the electrical properties of the aluminum alloy technology, the invention can be prevented. Compared with the known, the aluminum alloy has good flatness '14: the same day; except; the object 'is so as to make the poles short-circuited and open-circuited ... to effectively improve] so as not to form the structure of the electro-multilayer electrode and its method ;: ::; ::::: The device can avoid the formation of short circuit and open circuit of the electrode, and can be used for a short time: J = 幵 product yield and material throughput. The structure and method proposed in another embodiment of the present invention for forming a multi-layer electrode for a planar display device can reduce the formation of unnecessary over-oxidation phenomena, and can moreover "Avoid", or the occurrence of broken artifacts. More specifically, after the deposition of a metal alloy layer is completed, a protective layer is deposited on the metal alloy layer to form a multi-layered object. Subsequently, ' The multi-layered object is designated to remove contaminants through a cleaning process, so that the multi-layer electrode for the flat display device can be formed after the multi-layered object is left. Μ μ In another embodiment, the present invention In the proposed structure and method for forming a multilayer electrode for a flat display device, an intermetallic compound is not generated during the electrode forming process. In this embodiment, a first metal alloy is deposited first. Layer on a substrate, and secondly forming a resistive layer on the first metal alloy layer. The resistive layer is used to prevent

1012-4065-PF; ALEX.ptd1012-4065-PF; ALEX.ptd

501159 五、發明說明(8) 金屬間化合物的形成。隨後’沉積一第二金屬合金層於 該阻層,該阻層係用以防止該第二金屬合金層内之該金屬 間化合物的形成。如此一來’藉由該阻層係可防止於該第 二金屬合金層内部形成金屬間化合物。 為讓本發明之上述目的、特徵及優點能更明顯易懂, 下文特舉一較佳實施例,並配合所附圖式,作詳細說明如 下。 塁_式農見說明 弟1圖係表示根據本發明之一實施例中之顯示裝置之 電極結構的形成方法。 第2圖係表示藉由一側剖面圖以說明本發明之一實施 例中之藉由沉積方式將一顯示裝置用之一金屬合金層 (metal alloy layer)形成於一背板(backplate)之上。 第3圖係表示藉由一側剖面圖以說明本發明之一實施 例中之顯示裝置用之一覆蓋層的沉積作業。 第4A圖係表示當藉由罩幕及餘刻等步驟於第3圖中所 示之結構中形成一覆蓋層之後的放大圖示。 第4B圖係表示當藉由罩幕及蝕刻等步驟於第3圖中所 示之結構中形成一覆蓋層之後的放大圖示。 第5A圖係表示當藉由沉積步驟於第4A圖中所示之結構 中形成一阻層之後的放大圖示。 第5B係表示當藉由沉積步驟於第4β圖中所示之結構中 形成一阻層之後的放大圖示。 第6Α圖係表示當藉由沉積步驟於第5Α圖中所示之結構501159 V. Description of the invention (8) Formation of intermetallic compounds. Subsequently, a second metal alloy layer is deposited on the resist layer, the resist layer is used to prevent the formation of the intermetallic compound in the second metal alloy layer. In this way, the formation of the intermetallic compound inside the second metal alloy layer can be prevented by the resistance layer system. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows. Fig. 1 shows a method for forming an electrode structure of a display device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view illustrating the formation of a metal alloy layer for a display device on a backplate by a deposition method according to an embodiment of the present invention. . Fig. 3 is a cross-sectional view illustrating the deposition operation of a cover layer for a display device according to an embodiment of the present invention. Fig. 4A is an enlarged view showing a case where a cover layer is formed in the structure shown in Fig. 3 through steps such as a mask and a rest. Fig. 4B is an enlarged view showing a case where a cover layer is formed in the structure shown in Fig. 3 through steps such as masking and etching. FIG. 5A is an enlarged view showing when a resist layer is formed in the structure shown in FIG. 4A by a deposition step. Fig. 5B shows an enlarged view when a resist layer is formed in the structure shown in Fig. 4? By the deposition step. Figure 6A shows the structure shown in Figure 5A by the deposition step.

1012-4065-PF » ALEX.ptd 第14頁1012-4065-PF »ALEX.ptd Page 14

發明說明 中形成介電阻層之後的放大圖示。 中所示之結構 中所示之結構 中所示之結構 中所示之結構 第6 B圖係表示當藉由沉積步驟於第5 B圖 中形成一介電阻層之後的放大圖示。 第7A圖係表示當藉由沉積步驟於第6A圖 中形成一金屬合金層之後的放大圖示。 第7B圖係表示當藉由沉積步驟於第6B圖 中形成一金屬合金層之後的放大圖示。 第8 A圖係表示當藉由沉積步驟於第7A圖 中形成一覆蓋層之後的放大圖示。 第8 B圖係表示當藉由沉積步驟於第7 B圖中所示之結構 中形成一覆蓋層之後的放大圖示。 第9 A圖係表示根據第8 A圖中所示之結構在完成罩幕及 蝕刻等步驟之後的放大圖示。 第9 B圖係表示根據第8 B圖中所示之結構在完成罩幕及 蝕刻等步驟之後的放大圖示。 第10A圖係表示當藉由沉積步驟於第9人圖中所示之結 構中形成一鈍化層(passivation layer)之後的放大圖 示0 第10B圖係表示當藉由沉積步驟於第9β圖中所示之結 構中形成一鈍化層之後的放大圖示。 ° 第11Α圖係表示根據第1 0 Α圖中所示之結構在完成罩幕 及蝕刻等步驟之後的放大圖示。 第11B圖係表示根據第10B圖中所示之結構在完成罩幕 及蝕刻等步驟之後的放大圖示。BRIEF DESCRIPTION OF THE INVENTION An enlarged view after a dielectric resistance layer is formed in. Structure shown in Structure shown in Structure shown in Structure shown in Structure shown in Figure 6B is an enlarged view of a dielectric resistive layer formed in Figure 5B by a deposition step. FIG. 7A is an enlarged view after a metal alloy layer is formed in FIG. 6A by a deposition step. FIG. 7B is an enlarged view after a metal alloy layer is formed in FIG. 6B by a deposition step. FIG. 8A is an enlarged view after a capping layer is formed in FIG. 7A by a deposition step. FIG. 8B is an enlarged view after a cover layer is formed in the structure shown in FIG. 7B by a deposition step. Fig. 9A is an enlarged view showing the structure shown in Fig. 8A after the steps of masking and etching are completed. Fig. 9B is an enlarged view showing the structure shown in Fig. 8B after the steps of masking and etching are completed. Fig. 10A shows an enlarged view when a passivation layer is formed in the structure shown in Fig. 9 by a deposition step. Fig. 10B shows when a passivation layer is formed by a deposition step in Fig. 9β. An enlarged view of the structure shown after a passivation layer is formed. ° Figure 11A is an enlarged view of the structure shown in Figure 10A after the steps of masking and etching are completed. Fig. 11B is an enlarged view showing the structure shown in Fig. 10B after the steps of masking and etching are completed.

1012-4065-PF ; ALEX.ptd 第15頁 501159 五、發明說明(ίο) 第l^A圖係表示當藉由沉積步驟於第11A圖中所示之結 構中形成一閘極金屬層(gate metal layer layer)之後的 放大圖示。 第圖係表示當藉由沉積步驟於第11B圖中所示之結1012-4065-PF; ALEX.ptd Page 15 501159 V. Description of the invention (ίο) Figure l ^ A shows when a gate metal layer (gate metal layer) is formed in the structure shown in Figure 11A by a deposition step (gate) metal layer layer). The figure shows the junction shown in Figure 11B by the deposition step.

W 構中形成一閘極金屬層之後的放大圖示。 第圖係表示根據第12A圖中所示之結構在完成罩幕 及餘刻等攀驟之後的放大圖示。 第Γ§ί圖係表示根據第1 2B圖中所示之結構在完成罩幕 及餘刻等步驟之後的放大圖示。An enlarged view after a gate metal layer is formed in the W structure. The first figure is an enlarged view of the structure shown in FIG. 12A after the steps of the mask and the rest are completed. Figure Γ§ί shows an enlarged view of the structure shown in Figure 12B after the steps of masking and remaining time are completed.

第l^A圖係表示根據第1 3A圖中所示之結構在形成射和 (—emitters)及聚焦結構(focus structure)之後的放大圖—Figure l ^ A is an enlarged view of the structures shown in Figure 13A after forming the emitters and focus structures—

TfC 〇 第圖係表示根據第13B圖中所示之紝娃― 及聚焦結構之後的放大㈣。 結構在形成射相 第1 5圖係表示根據本發明之一實施例中之顧 電極結構的形成方法。 ”、員不裝置^ 第1參A圖係表示根據一實施例中之—一抑 的剖面視圖,於該背板上具有底部、r"、不态之一背板 板包括有一阻層、一介電層及一閘極層=電極,並且該$TfC 〇 The figure shows the magnification of the focusing structure and the focusing structure shown in Figure 13B. Fig. 15 is a diagram showing a method for forming an electrode structure according to an embodiment of the present invention. "A member is not installed. ^ The first reference A is a cross-sectional view according to an embodiment of the present invention. The back plate has a bottom, r ", and one of the back plates. Dielectric layer and a gate layer = electrode, and the $

第16/B圖係表示根據一實施例中之— 一 的剖面視圖,於該背板上具有底部、頂苦^員不器之一背板 板包括有一阻層、一介電層及一閘極層。極,並且該$ 第11 €圖係表示當藉由沉積、罩暮 9A圖中所示之結構中形成之—鈍化層。蝕刻等步驟於第FIG. 16 / B is a cross-sectional view of one of the first embodiment according to an embodiment. The back plate has a bottom plate and a top plate on the back plate. The back plate includes a barrier layer, a dielectric layer, and a gate. Polar layer. The figure shows the passivation layer formed in the structure shown in Figure 9A by deposition and masking. Etching and other steps

1012-4065-PF; ALEx.ptd 第16頁 5U1159 五、發明說明(π) 第16D圖係矣;丄 , ^ ^ 9B H Φ所-夕a表藉積、罩幕及蝕刻等步驟於第 圖中所不之結構中形成之一鈍化層。 第16E圖係表示根據第16(:圖中所 及姓刻等步驟之後的剖面視圖。 構在疋成罩幕 及敍係表示根據第16D圖中所示之結構在完成罩幕 及蝕^ 4步驟之後的剖面視圖。 第1 6G圖係表示根據第丨6E中之結 ^ ' ^^#^(c〇ne raaterial),^ . 積及罩幕、餘刻等步驟之後的剖面視圖。材料層之此 第1 6Η圖係表示根據第1 6F中之結構在完成一含鉻層 4發、一錐體材料之沉積、一介電材料層之 蝕刻等步驟之後的剖面視圖。 檟卓綦 第1 6 I圖係於本發明之一實施例中之 & 整陰極結構。 衣直ι % 第16 J圖係於本發明之一實施例中之 * 整陰極結構。 貝τ展直(^ 係ίΓ根據本發明之一實施例中之用以形成- μ員不裝置之一電極結構的形成方法。 第1 8Α圖係表示根據一實施例中之一一、抑 一 板包括有一阻層、一介電層及一閘極層。 λ月 第1 8Β圖係表示根據一實施例中之一县一即 的剖面視圖,於該背板上具有底部、抑、1不器之一背板 板包括有一阻層、一介電層及一閘極層"。電極,並且該背1012-4065-PF; ALEx.ptd Page 16 5U1159 V. Description of the invention (π) Figure 16D is shown in Figure 矣; 丄, ^ ^ 9B H Φ-a table borrowing, masking and etching steps are shown in Figure A passivation layer is formed in the structure not shown in the figure. Figure 16E is a cross-sectional view after the steps such as the last name and the engraving in the figure. (Constructed in the mask and the serie show that the mask and etch are completed according to the structure shown in Figure 16D ^ 4 Cross-sectional view after the steps. Figure 16G shows the cross-sectional view after the steps such as the integration and masking, and engraving according to the knot in the 6th ^ ^ ^^ ## (c〇ne raaterial), material layer. This 16th figure is a cross-sectional view showing the structure in 16F after the completion of a step containing 4 layers of chromium, deposition of a cone material, and etching of a dielectric material layer. 槚 卓 綦 第 1 Fig. 6I is an & entire cathode structure in one embodiment of the present invention. Straight%% Fig. 16J is an * entire cathode structure in one embodiment of the present invention. According to an embodiment of the present invention, a method for forming an electrode structure for forming a μ-member device. FIG. 18A shows that according to an embodiment, a plate includes a resistance layer, a dielectric The electric layer and a gate layer. Fig. 18B shows a cross-sectional view of a county according to an embodiment, The back plate having a bottom, suppression, not one of a backplane board comprises a resistive layer, a dielectric layer and a gate layer ". electrode, and the back

1012-4065-PF; ALEX.ptd 第17頁 501159 五、發明說明(12) 第1 8C圖係表示根據第1 8A中之結構在利用罩幕、蝕刻 等步驟形成一閘極結構之後的剖面視圖。 第1 8D圖係表示根據第1 8B中之結構在利用罩幕、蝕刻 等步驟形成一閘極結構之後的剖面視圖。 第1 8E圖係表示根據第1 8C中之結構在經由罩幕、蝕刻 等步骤之後的剖面視圖。 第1 8F圖係表示根據第1 8D中之結構在經由罩幕、蝕刻 等步驟之後的剖面視圖。 第18G圖係表示當藉由沉積步驟於第18E圖中所示之結 構中形成一鈍化層且經由罩幕、蝕刻等步驟之後的剖面視 圖。 第18H圖係表示當藉由沉積步驟於第18F圖中所示之結 構中形成一鈍化層且經由罩幕、蝕刻等步驟之後的剖面視 圖。 第1 8 I圖係表示根據第1 8G中之結構在完成一含鉻層之 蒸發、一錐體材料之沉積、一介電材料層之沉積及罩幕、 蝕刻等步驟之後的剖面視圖。 第1 8 J圖係表示根據第1 8H中之結構在完成一含鉻層之 蒸發、一錐體材料之沉積、一介電材料層之沉積及罩幕、 蝕刻等步驟之後的剖面視圖。 第1 81(圖係表示根據第1 8 I中之結構在完成罩幕、蝕刻 等步驟之後的剖面視圖。 第1 8L圖係表示根據第1 8 J中之結構在完成罩幕、蝕刻 等步驟之後的剖面視圖。1012-4065-PF; ALEX.ptd Page 17 501159 V. Description of the invention (12) Figure 18C shows a cross-sectional view of the structure in Figure 18A after a gate structure is formed using steps such as masking and etching. . Fig. 18D is a cross-sectional view showing a structure of the gate electrode 18B after a gate structure is formed according to the structure in Fig. 18B. Fig. 18E is a cross-sectional view showing the structure in Fig. 18C after going through steps such as masking and etching. Fig. 18F is a cross-sectional view showing the structure in Fig. 18D after going through steps of masking and etching. FIG. 18G is a cross-sectional view after a passivation layer is formed in the structure shown in FIG. 18E by a deposition step and is subjected to steps such as masking and etching. FIG. 18H is a cross-sectional view after a passivation layer is formed in the structure shown in FIG. 18F by a deposition step and is subjected to steps such as masking and etching. FIG. 18I is a cross-sectional view showing the structure in Article 18G after completing the steps of evaporation of a chromium-containing layer, deposition of a cone material, deposition of a dielectric material layer, masking, and etching. Figure 18J is a cross-sectional view of the structure in Figure 18H after completing the steps of evaporation of a chromium-containing layer, deposition of a cone material, deposition of a dielectric material layer, masking, and etching. No. 1 81 (picture shows a cross-sectional view after the steps of masking and etching are completed according to the structure in No. 18 I. No. 18L shows a step of completing the masks and etchings according to the structure in No. 18 J Later section view.

1012-4065-PF : ALEX.ptd 第18頁 5011591012-4065-PF: ALEX.ptd page 18 501159

第18M圖係表示於本發明之一 一完整陰極結構。 她例中之顯示裝置之 第1 8N圖係表示於本發明之一 ^ 一完整陰極結構。 知例中之顯示裝置之 第1 9圖係表示根據本發明之一徐^ 顯示裝置之一電極結構的形成方法貫施例中之用以形成一 第20A圖係表示根據一實施例 的剖面視圖,於該背板上具有底部、—顯示器之一背板 板包括有一阻層、一介電層、鈦声 項部電極,並且該背 第2〇b圖係表示根據Λ施例VV閉極層。 餘刻 的剖面視圖,於該背板上具有底 之一顯示器之一背板 板包括有一阻層、一介電層、三σ 、頂部電極,並且該背 第20C圖係表示根據第曰= =及—閘極層。 蝕刻 等步驟形成一鈦結構、一閘極妹、:、°構在利用罩幕 第20D圖係表示根據第2〇β、中° ^ ^後的剖面視圖 等步驟形成一鈦結構、—Μ<、,、D構在利用罩幕 第20E圖係表示當藉由沉穑、°構之後的剖面視圖。 構中形成一鈍化層且經由罩農、V驟於第20C圖中所示之舄 圖。 、餘刻等步驟之後的剖面頑 步驟於第20D圖中所示之 餘刻等步驟之後的剖面 結 視 第20F圖係表示當藉由沉積 構中形成一鈍化層且經由罩幕'、 圖〇 第20G圖係表示板墟 1# 很據第20E中之結構在完成一含鉻層之 泰發、一錐體材料之沉籍 ^ ^ m ^ 儿積、一介電材料層之沉積及罩幕、 五、發明說明(14) 蚀刻等步驟之後的剖面視圖。 第2 Ο Η圖係表示根撼笛9 蒸發、一錐體材料之沉#、 A ^ t構在完成—含絡層之 餘刻等步驟之後的剖面^圖:介電材料層之沉積及罩幕、 第2 Ο I圖係表示根撼笛9 n 等步驟之後的剖面視圖。 《結構在a成罩幕、#刻 第20J圖係表示根攄證9 等步驟之後的剖面視圖弟2°H中之結構在完成罩幕、餘刻 第20K圖係表示於本發 一完整陰極結構。 貝鉍例中之顯示裝置之 « 第20L圖係表示於本發 ^ 一完整陰極結構。 月之一貫施例中之顯示震置之 第2 1圖係表示根據本路 — 一 顯示裝置之-電極結構的形貫施例中之用以形成一 第22A圖係表示根據_實施例中之一顯示写之一背 的剖面視圖,於該背板上星右 * " 月板 姑白杠女rt口庶 人,、有底部、頂部電極,並且該背 Ϊ99:層、一介電層及-閘極層。 的剖面視圖,於該背板上且貫有^^中之一顯示器之一背板 •锚白杠女.^ :上具有底部、頂部電極,並且該背 板〇括有一阻層、一介電層及一閘極声。 ,22C圖係表示當藉由沉積步驟於曰第⑽圖中所示之結 形成-鈍化層且經由罩幕、㈣等步驟之後的剖面視 第22D圖係表不s藉由沉積步驟於第圖中所示之結Fig. 18M shows a complete cathode structure according to one of the inventions. Figure 18N of the display device in her example is shown in one of the present invention ^ a complete cathode structure. Fig. 19 of a display device in the known example shows a method for forming an electrode structure of a display device according to the present invention, and a 20A diagram in the embodiment is a cross-sectional view according to an embodiment. There is a bottom plate on the back plate, a back plate of the display including a resist layer, a dielectric layer, and a titanium acoustic head electrode, and the back figure 20b shows the VV closed electrode layer according to the Λ embodiment. . A cross-sectional view at a later time, one of the backplanes having a bottom display on the backplane includes a resistive layer, a dielectric layer, three σ, and a top electrode. And-the gate layer. Etching and other steps to form a titanium structure, a gate electrode, and a structure. Using the mask in the 20D picture system shows a step according to the 20 °, middle ° ^ ^ cross-sectional view and other steps to form a titanium structure, -M < Figures 20E of the D, D, and D structures show cross-sectional views when the structure is settled by the Shen and Dian structures. In the structure, a passivation layer is formed and is shown in FIG. 20C through the cover film. The cross-section after the steps such as steps and after-cuts is shown in Figure 20D. The cross-section view after the steps such as steps shown in Figure 20D shows that when a passivation layer is formed in the deposited structure and passes through the mask ', Figure 〇 Figure 20G shows the structure of Banxu 1 # according to the structure in 20E. A chrome-containing layer of Taifa, a cone-shaped material, ^ ^ m ^ child product, deposition of a dielectric material layer, and a mask are shown. 5. Explanation of the invention (14) A cross-sectional view after steps such as etching. Fig. 2 is a cross-sectional view showing the evaporation of the root flute 9 and the deposition of a cone material #, A ^ t structure after the completion of the steps including the formation of the complex layer ^ Figure: the deposition and cover of the dielectric material layer The curtain and Figure 2O are cross-sectional views after the steps of 9n. `` The structure is shown in a mask, # 20J is a cross-sectional view after steps 9 and so on. The structure in 2 ° H is completed, and the 20K picture is shown in a full cathode in this hair. structure. Fig. 20L of the display device in the case of bismuth is shown in the present invention ^ a complete cathode structure. Figure 21 of the display arrangement in the first embodiment of the month is shown in accordance with the present embodiment of the electrode structure of the electrode structure of a display device, which is used to form a 22A diagram according to the embodiment of the A cross-sectional view showing the back of one of the writes, on the back panel, the star is right * " The moon board female white bar rt mouth is pretty, has bottom and top electrodes, and the back panel 99: layer, a dielectric layer and -Gate layer. A cross-sectional view of the backplane and one of the monitors ^^ backplane • anchor white bar female. ^: There are bottom and top electrodes on the backplane, and the backplane includes a barrier layer, a dielectric Layer and a gate sound. The 22C diagram shows the cross-sectional view when the passivation layer is formed by the deposition step shown in the second figure, and the steps after the mask and the step are shown in FIG. 22D. Knot shown

501159 五、發明說明(15) :中形成-鈍化層且經由罩I、蝕刻等步驟之後的剖面視 圖。 夕” f係表7^根據第22G巾之結構在完成介電材料層 之/儿積及罩幕、蝕刻等步驟之後的剖面視圖。 係表示根據第22D中之結構在完成介電材料層 之/儿積及罩幕、蝕刻等步驟之後的剖面視圖。 糾G圖係表示根據第,中之結構在利用蝕刻步驟以 瓜成凹4 (cavity)之後的剖面視圖、 # 第22H圖係表示根據第22F中之結構在利用 形成一凹部之後的剖面視圖。 〗艾诹乂 “ A第2一2 系表示根據第2 2G中之結構在完成一含鉻層之 笙牛材料之沉積、一介電材料層之沉積及罩幕、 蝕刻^步驟之後的剖面視圖。 罩幕 基發:一錐表不根據第2211中之結構在完成一含鉻層之 ㈣等步之沉積、一介電材料層之沉積及罩幕、 第m圖传/剖面視圖。. 等步驟之後的=示根據第221中之結構在完成罩.幕、姓刻 ^ 面視圖。 , 第22L圖係矣_ _ 等步驟之後的:示根據第2 2】中之結構在完成罩幕、蝕刻 ㈣圖V/視圖。 一完整陰極結構^不於本發明之一實施例中之顯示裝置之 第22N圖係參一 一完整陰極結構'不於本發明之一實施例中之顯示裝置之501159 V. Description of the invention (15): A cross-sectional view after the formation of a passivation layer through the mask I, etching and other steps. Xi "f is Table 7 ^ A cross-sectional view of the structure of the 22G towel after completing the steps of the dielectric material layer / layer, mask, and etching. It shows the structure of the dielectric material layer according to the structure in 22D. / The cross-sectional view after the steps of masking, etching, etc. The G-correction diagram is a cross-sectional view of the structure after the etching step is used to form a cavity 4 according to the first and second steps, and the # 22H diagram is based on the A cross-sectional view of the structure in the 22F after the formation of a recess. Ai "" A 2-2 means the completion of the deposition of a chrome-containing layer of Sheng Niu material according to the structure in 2 2G, a dielectric A cross-sectional view after the material layer deposition and masking and etching steps. Mask base: A cone is used to complete the first step deposition of a chromium-containing layer, the deposition of a dielectric material layer and the mask according to the structure in Section 2211, and the m-th view / section view. After waiting for the steps, = shows that the mask, screen and surname are carved according to the structure in No. 221. Figure 22L is after __ _ and other steps: it shows the mask and etched figure V / view according to the structure in [2 2]. A complete cathode structure is not shown in Figure 22N of a display device in one embodiment of the present invention. A complete cathode structure is not shown in a display device of one embodiment of the present invention.

1012-4065-PF ; ALEX.ptd 第21頁 5011591012-4065-PF; ALEX.ptd page 21 501159

第23圖係表示根據本發明之一實施例 顯示裝置之一電極結構的形成方法。 用以形成一 第2 4 A圖係表示根據一實施例中之一一、口。Fig. 23 shows a method for forming an electrode structure of a display device according to an embodiment of the present invention. Figure 2 4A is used to illustrate a port according to an embodiment.

的剖面視圖,於該背板上具有底部、邱,不器之—背板 板包括有一阻層、一介電層及一閘極層°。電極,並且該I 第24B圖係表示根據一實施例中之一 _ 的剖面視圖,於該背板上具有底部、頂部不為之一背板 板包括有一阻層、一介電層及一閘極層。一 ° ,並且該負 第24C圖係表示根據第24A中之結^ . (sputtered molybdenum layer)之沉積、二 * 一濺鍍鉬肩A cross-sectional view of the backplane includes a bottom, a Qiu, and other components-the backplane includes a barrier layer, a dielectric layer, and a gate layer. The electrode and the 24B diagram are cross-sectional views according to one of the embodiments. The back plate has a bottom and a top portion. The back plate includes a barrier layer, a dielectric layer, and a gate. Polar layer. 1 °, and the negative Figure 24C shows the deposition according to the knot in Section 24A, (sputtered molybdenum layer), two * a splash of molybdenum shoulder

積及濺鍍鉬層之沉積步驟之後的剖面視圖。蒸鍍銦層之別 第24D圖係表示根據第2〇中之結構二三 之沉積、一蒸鍍鉬層之沉積及濺鍍鉬芦=一濺鍍鉬眉 剖面視圖。 "< /儿積步驟之後合 之結構在完成罩幕及蝕刻 之結構在完成罩幕及蝕刻 第2 4Ε圖係表示根據第24C中 等步驟之後的剖面視圖。 第24F圖係表示根據第24D中 等步驟之後的剖面視圖。A cross-sectional view after the step of depositing and depositing a molybdenum layer. The difference between the vapor-deposited indium layer and FIG. 24D are cross-sectional views showing the deposition of the structure two or three, the vapor-deposited molybdenum layer, and the sputtered molybdenum reed according to the structure in item 20 = a sputtered molybdenum eyebrow. " < / The structure after the child product step is completed after the mask and etching is completed The structure after the mask and etching is completed Figure 24E shows a cross-sectional view after the intermediate step according to step 24C. Figure 24F is a cross-sectional view after the intermediate step according to 24D.

第24G圖係表示根據第me中之結構 層及一鈍化層之沉積步驟之後的剖面視=^成一介電材料 第24Η圖係表示根據第24F中之結構在☆ 層及一鈍化層之沉積步驟之後的剖面視圖=成—介電材料 第241圖係表示根據第24G中孓結構在 等步驟之後的剖面視圖。 成罩幕及蝕刻Figure 24G shows the cross-sectional view after the deposition step of the structural layer and a passivation layer in me = ^ becomes a dielectric material. Figure 24Η shows the deposition steps of the ☆ layer and a passivation layer according to the structure in 24F Subsequent cross-sectional view = Cheng-dielectric material. Fig. 241 shows a cross-sectional view after the isochronous step according to the 24th gadolinium structure. Masking and etching

1012-4065-PF ; ALEX.ptd 501159 五、發明說明(17) ~" ' ' ' - I牛圖係表示根據第2411中之結構在完成罩幕及蝕刻 荨步驟之後的剖面視圖。 I牛圖係表示根據第24ί中之結構在完成罩幕及钮刻 寺步驟之後的剖面視圖。 第24L圖係表示根據第24J中之結構在完成罩簋芬爲糾 等步驟之後的剖面視圖。 战罩幕及蝕刻 第24M圖係表示根據第24K中之結構 等步驟之後的剖面視圖。 成罩幕及蝕刻 第24Ν圖係表示根據第24l中之結構在完成 等步驟之後的剖面視圖。 成罩幕及蝕刻 第25圖係表示根據本發明之一實施例中 / 顯不,置之一電極結構的形成方法。 以形、 第2 6 Α圖係表示根據一實施例中之一;时 結構於完成罩幕及蝕刻等步驟之後、完·、、、」、裔之一背板 之後的剖面視圖,於該背板上具有底 二電層之沉積 該背板包括有一阻層、一介電層、—閉頂4電極,並且 層、一蒸鍍鉬層及一濺鍍鉬層。 甲亟層、一濺鍍鉬 第26B圖係表示根據一實施例中之一 一 結構於完成罩幕及蝕刻等步驟之後、$顯示器之一背板 之後的剖面視圖,於該背板上具有底=成一介電層之沉積 層 該背板包括有一阻層、一介電層、二°卩、了I部電桉,並且 一蒸鍍鉬層及一濺鍍鉬層。 第26C圖係表示根據第26A中之姅 ''Ό構在 閘極 嘈、一濺鍍鉬 等步驟之後的剖面視圖 元成罩幕及蝕刻1012-4065-PF; ALEX.ptd 501159 V. Description of the invention (17) ~ " '' '-I The bull picture is a cross-sectional view showing the structure after the mask and etching steps according to the structure in No. 2411. The I-picture is a cross-sectional view after the steps of the mask and the engraved temple are completed according to the structure in No. 24th. Figure 24L is a cross-sectional view of the structure according to Item 24J after the steps of masking and rectifying are completed. Battle mask and etching Figure 24M is a cross-sectional view after the steps such as the structure in Figure 24K. Masking and Etching Fig. 24N is a cross-sectional view showing the structure according to No. 24l after the completion of the steps. Forming a Mask and Etching FIG. 25 shows a method for forming an electrode structure according to an embodiment of the present invention. Fig. 2A is a cross-sectional view of the structure according to one of the embodiments; after the steps of masking and etching are completed, and after the back plate is finished, The backplane has two bottom electrical layers. The backplane includes a barrier layer, a dielectric layer, and a closed-top 4 electrode, and a layer, a vapor-deposited molybdenum layer, and a sputtered molybdenum layer. A layer, a sputtered molybdenum plate 26B is a cross-sectional view of a structure after a mask and an etching step are completed, and after a backplane of a display according to one of the embodiments. The backplane has a bottom = A deposition layer that forms a dielectric layer The backplane includes a resistive layer, a dielectric layer, 2 ° 卩, an electric eucalyptus, and a vapor-deposited molybdenum layer and a sputtering molybdenum layer. Figure 26C is a cross-sectional view showing the structure of the gate in No. 26A after the noisy, sputtered molybdenum plating and other steps.

五、發明說明(18) 第26D圖係表示根據第26 等步驟之後的剖面視圖。 之結構在完成罩幕及蝕刻 第2 6 E圖係表示根據第2 6。中 等步驟之後的剖面視圖。 之結構在完成罩幕及蝕刻 第2 6F圖係表示根據第26])中 等步驟之後的剖面視圖。 〜構在完成罩幕及蝕刻 第2 6G圖係表示根據第26£中 等步驟之後的剖面視圖。 〈…構在完成罩幕及蝕刻 第26H圖係表示根據第26{? 等步驟之後的剖面視圖。 &lt; …構在完成罩幕及蝕刻 第2 6 I圖係表示根據第2 β c i 等步驟及一聚焦結構的成型之之結構在完成罩幕、蝕刻 第26J圖係表示根據第26/的剖面視圖。 等步驟及一聚焦結構的成型 之、、構在元成罩幕、餘刻 第26K圖係*示根據第261^ =面視圖。 等步驟之後的剖面視圖。 構在完成罩幕及蝕刻 第2 6L·圖係表示根據第2 6】中士 、 等步驟之後的剖面視圖。 、、、°構在元成罩幕及餘刻 _ 第2 7圖係表示根據本發明之—给 顯示裝置之一電極結構的形成方、、貝施例中之用以形成一 第28A圖係表示根據一實施例中 抑 的剖面視圖,於該背板上氣右颁不态之一老板 板包括有-阻層、-介電層、頂部電極,並且該背 鍍鉬層及一介電層。 甲極層、蒸鍍鉻層、一蒸V. Description of the Invention (18) Figure 26D is a cross-sectional view after steps 26 and so on. The structure is finished in the mask and etched. Figure 2E is shown in Figure 6E. Sectional view after intermediate steps. The structure is shown in section 26F after the mask and etching are completed. Figure 26F shows a cross-sectional view after the steps according to step 26]). Figure 6G is a cross-sectional view after the intermediate steps according to step 26 £. <... Constructing the mask and etching is completed. Figure 26H is a cross-sectional view showing the steps following Step 26 {? &lt;… constructed on the completion of the mask and etching 2 6 I picture shows the structure according to the steps such as the 2 β ci and the formation of a focusing structure Fig. 26J on the completion of the mask and etching shows the section according to 26 / view. The other steps and the formation of a focusing structure, the structure is formed in the cover of Yuancheng, and the rest is shown in Figure 26K. * Shown according to No.261 ^ = surface view. Section view after waiting for steps. The structure is completed after the mask and etching are completed. Section 2L · The diagram is a cross-sectional view after the steps according to Section 2]. ,,, ° structured in the cover of Yuancheng and the rest_ Figure 27 shows the formation of an electrode structure for a display device according to the present invention, which is used to form a 28A picture system in the example. Shows a cross-sectional view according to an embodiment. One of the boss boards on the back board includes a resist layer, a dielectric layer, a top electrode, and the back molybdenum layer and a dielectric layer. . Tier layer, chrome layer, one steam layer

1012-4065-PF ; ALEX.ptd1012-4065-PF; ALEX.ptd

苐24頁 五、發明說明(19) 第28β圖係表示根據一實施例中 一 的剖面視圖,於該背板上具有底部、 顯不器之一背板 板包括有一阻層、一介電層、一閘梳^ °卩電極’並且該背 鍍鉬層及一介電層。 蒸鍍鉻層、一蒸 構在完成罩幕及蝕刻 餘刻 第28C圖係表示根據第28Α中之結 等步驟之後的剖面視圖。 第28D圖係表示板據第28Β中之姓播—#丄 〜、、、口稱在完成置莫 等步驟之後的剖面視圖。 X旱泰及 第28E圖係表示根據第28C中之結構在☆点w苗 等步驟之後的剖面視圖。 70罩幕及#刻 第28F圖係表示根據第28D中之結構在 等步驟之後的剖面視圖。 早奉及蚀刻 第28G圖係表示根據第28E中之結構在完 之後的剖面視圖。 &gt; “、、、、、。構 第28H圖係表示根據第28F中之結構在完成了聚焦結 之&quot;ί灸的剖面視圖。 第281圖係表示根據第28G中之結構在完 後的剖面視圖。 成餘刻步驟 之 第28J圖係表示根據第28H中之結構在完成蝕刻 後的剖面視圖。 第28K圖係表示根據第281中之結構在完成蝕刻步驟 後的剖面視圖。 ^ 第28L圖係表示根據第28J中之結構在完成蝕刻 後的剖面視圖。 ^ _ 之 之 第25頁 501159页 Page 24 V. Description of the invention (19) Figure 28β is a cross-sectional view according to one of the embodiments. The back plate has a bottom and a display on the back plate. The back plate includes a barrier layer and a dielectric layer. A gate comb electrode, and the back plated with a molybdenum layer and a dielectric layer. The vapor-deposited chrome layer, a vapor-deposited layer after completion of the mask and etching. Fig. 28C is a cross-sectional view showing the steps according to the knot in Fig. 28A. FIG. 28D is a cross-sectional view showing the surname broadcast— # 丄 ~ ,,, and verbally in the 28th section of the board after completing the steps such as setting the mo. Xana Thai and Fig. 28E are cross-sectional views after steps such as ☆ point w seedling according to the structure in 28C. 70mask and # 刻 Figure 28F shows a cross-sectional view after waiting for steps according to the structure in Figure 28D. Bone and Etching Fig. 28G is a cross-sectional view after completion of the structure according to 28E. &gt; ",,,,, .. Fig. 28H shows a cross-sectional view of the focus moxibustion completed according to the structure in 28F. Fig. 281 shows the structure after completion of the structure in 28G. Sectional view. Fig. 28J forming the remaining step shows a cross-sectional view after the etching according to the structure in 28H. Fig. 28K shows a cross-sectional view after the etching step according to the structure in 281. ^ Section 28L The drawing shows a cross-sectional view after the etching is completed according to the structure in No. 28J. ^ Of the 25th page 501159

五、發明說明(20) ㈣A圖係表示根據-實施例中之一多位準電極 (multilayer electrode)成型如門仏、丄 f 紙i朋間所沉積形成之一 金層(metal al loy layer)之剖面視圖。 变屬合 第2 9 B圖係表示根據第2 9 A中之姓二致士 —上、, 、、’口稱在元成一保+崔&amp; (protective layer)之沉積後的剖面視圖。 、邊層 第29C圖係表示於第29B中之社槿於二二、…六 (contaminants)之移除前的剖面視圖。 第2 9 D圖係表示於第2 9 C中之έ士椹私、# —、主* · 、 τ &lt;、、、°構於進仃清潔程庠 (cleaning process)之後的剖面視圖。 ^ 第29E圖係表示於第29C中之結構上設置_光 (layer of photoresist)之後的剖面視圖。 e 第29F圖係表示於第29E中之結構上設置# (P-e^ layer 〇f Photo.esiso,::^ ;;^ 的剖係表™中之結構於進糊工後 面視ΓΗ圖係表示根據一實施例中之一多位準電極之剖 第30圖係表示根據—實施例中之 流程圖。 干电位之成型 第31 Α圖係表示根據一實施例中之於位 成型期間所沉積形点夕—筮 A ®人A B 干电極的 第川圖係表金屬合金層之剖面視圖。 衣不將一阻層(barrier layer)形成; 31A中之結構上的剖面視圖。 ⑽成於第 第31C圖係表示將一第二金屬合金層沉積於第3ib之結V. Description of the invention (20) ㈣A is a metal al loy layer formed by depositing a multi-layer electrode such as a door 仏, 丄 f paper, and the like according to one of the embodiments. Section view. Figure 2 9B is a cross-sectional view showing the deposition of Yuancheng Yibao + Cui &amp; Figure 29C is a cross-sectional view of the hibiscus in Figure 29B before the removal of contaminants. Fig. 29D is a cross-sectional view showing the cleaning process, #-, main *, τ &lt;, ..., in Fig. 2C after the cleaning process. ^ Figure 29E is a cross-sectional view after the layer of photoresist is placed on the structure in Figure 29C. e Figure 29F shows the structure set up in 29E # (Pe ^ layer 〇f Photo.esiso, :: ^ ;; ^ The structure in the profile table ™ is viewed from the back of the plasterer, and the figure shows the basis Section 30 of a multi-level electrode in an embodiment shows the flow chart in accordance with the embodiment. The forming of the dry potential Figure 31A shows the shape points deposited during the in-position molding in accordance with an embodiment. Xi— 筮 A ® Human AB dry electrode is a cross-sectional view of a surface metal alloy layer. A barrier layer is not formed; 31A is a cross-sectional view on the structure. The figure shows the deposit of a second metal alloy layer on the 3ib

1012-4065-PF : ALEX.ptd 第26頁1012-4065-PF: ALEX.ptd Page 26

五、發明說明(21) 構上的剖面視圖。 之結構於進行污染物之移除 第31D圖係表示於第31C中 前的剖面視圖。 結構於進行清潔程序之後 結構上設置一光阻層 剖面視圖。 結構上設置一光阻圖樣層 第31E圖係表示於第31D中之 的剖面視圖。 第31F圖係表示於第31E中之 (layer of photoresist)之後的 第31G圖係表示於第31F中之 之後的剖面視圖。 第31H圖係表示於第31G中之結構於進行蝕刻步驟之後 的剖面視圖。 、第3 1 I圖係表示根據一實施例中之一多位準電極之剖 面視圖。 第32圖係表示根據一實施例中之一多位準電極之成型 流程圖。 符號說明 1〇1 、 102 、 103 、 104 110、111、112、113〜步驟 11〜金屬合金層; 14〜頂部電極; 1 6 0 1〜閘極結構; 1620〜1621〜開口; 1653〜錐體材料; 1 6 5 6〜開口; 、106、1〇7、108、109 f 1 2〜夾合層; 1 5〜鈍化層; · 1 6 0 2〜鈍化層; 1 640〜鉻; 1 6 5 4〜介電材料; 1 8 0 1〜閘極層;5. Description of the invention (21) A cross-sectional view of the structure. The structure is used for the removal of contaminants. Figure 31D is a cross-sectional view shown in front of Figure 31C. The structure is provided with a photoresist layer cross-sectional view after the cleaning process. A photoresist pattern layer is provided on the structure. Fig. 31E is a sectional view shown in Fig. 31D. Fig. 31F is a cross-sectional view showing a layer after the layer of photoresist in Fig. 31E. Figure 31H is a cross-sectional view showing the structure in Figure 31G after the etching step. Fig. 31 is a cross-sectional view showing a multi-level quasi-electrode according to an embodiment. Fig. 32 is a flow chart showing the formation of a multi-level quasi-electrode according to an embodiment. Explanation of symbols 10, 102, 103, 104 110, 111, 112, 113 ~ step 11 ~ metal alloy layer; 14 ~ top electrode; 16 0 1 ~ gate structure; 1620 ~ 1621 ~ opening; 1653 ~ cone Material; 1 6 5 6 ~ opening;, 106, 107, 108, 109 f 1 2 ~ sandwich layer; 1 5 ~ passivation layer; 1 6 0 2 ~ passivation layer; 1 640 ~ chromium; 1 6 5 4 ~ dielectric material; 1 0 0 1 ~ gate layer;

1012-4065-PF ; ALEX.ptd 第27頁 5011591012-4065-PF; ALEX.ptd page 27 501159

1 802〜鈦層; 1 8 11〜閘極金屬層; 1 820- 1 82 1 〜開口; 1 8 2 3〜底部接觸墊; 1 8 2 5〜凹部; 1 8 2 6〜錐體; 1 8 3 0〜鈍化層; 1 8 5 3〜錐體材料; 1856〜底部接觸墊; 1 8 91、1 8 9 2〜結構物 2 0〜閘極金屬; 1 8 1 0〜頂部電極; 1 8 1 2〜鈦結構; 1 8 2 2〜頂部接觸墊; 1 8 2 4〜聚醯亞胺; 1 8 2 6〜錐狀物; 1 827〜聚焦袼子金屬; 1840〜絡區段; 1 854〜介電材料; 1 8 5 7〜頂部接觸墊; ;2〜金屬合金層;1 802 ~ titanium layer; 1 8 11 ~ gate metal layer; 1 820- 1 82 1 ~ opening; 1 8 2 3 ~ bottom contact pad; 1 8 2 5 ~ recess; 1 8 2 6 ~ cone; 1 8 3 0 ~ passivation layer; 1 8 5 3 ~ cone material; 1856 ~ bottom contact pad; 1 8 91, 1 8 9 2 ~ structure 2 0 ~ gate metal; 1 8 1 0 ~ top electrode; 1 8 1 2 ~ titanium structure; 1 8 2 2 ~ top contact pad; 1 8 2 4 ~ polyimide; 1 8 2 6 ~ cone; 1 827 ~ focused raccoon metal; 1840 ~ network section; 1 854 ~ Dielectric material; 1 8 5 7 ~ top contact pad; 2 ~ metal alloy layer;

201 、 202 、 203 204 、205 、206 、207 、208 、209〜步 2 1〜閘極結構; 2 2〜攔接觸墊; 22卜凹部; 2222、2 223〜接觸墊; 2 2 2 4〜聚醯亞胺聚焦結構; 2226〜錐體; 2227〜聚焦格子金屬; 2250〜介電材料層;2252〜鉬結構; 2253〜錐體材料; 2254〜介電層; 2256-2257〜開口; 23〜列接觸塾; 2301 、 2302 、 2303 、 2304 、 2305 、 2306 、 2307 、 2308 、2309、2310、2311 〜步驟; 24〜聚酿亞胺; 2401〜錢鐘銦層; 2402〜蒸鍍鉬層; 2403〜濺鍍鉬層;201, 202, 203, 204, 205, 206, 207, 208, 209 ~ step 2 1 ~ gate structure; 2 2 ~ block contact pads; 22 recesses; 2222, 2 223 ~ contact pads; 2 2 2 4 ~ poly醯 imine focusing structure; 2226 ~ cone; 2227 ~ focus grid metal; 2250 ~ dielectric material layer; 2252 ~ molybdenum structure; 2253 ~ cone material; 2254 ~ dielectric layer; 2256-2257 ~ opening; 23 ~ column Contact thallium; 2301, 2302, 2303, 2304, 2305, 2306, 2307, 2308, 2309, 2310, 2311 ~ steps; 24 ~ polyimide; 2401 ~ qianzhong indium layer; 2402 ~ evaporated molybdenum layer; 2403 ~ Sputtered molybdenum layer;

1012-4065-PF I ALEX.ptd 第28頁 2422〜開口 ; 2424〜聚醯胺聚焦結構 2 4 2 6〜錐體材料; 2440〜介電層; 246卜2463〜開口; 501159 五、發明說明(23) 2422〜接觸墊; 2423〜底部接觸墊; 2425〜凹部; 2430-2431〜銦結構; 2 4 4 1〜鈍化層; 25〜凹部; 250 1、2502、250 3、2504、25 0 5、25 0 6 〜步驟; 2552、2554〜濺鍍錮層; 2 5 5 3〜蒸鍍鉬層; 2 6〜射極; 26〜錐體; 2600〜介電層; 2 6 2 4〜聚焦結構; 2 6 4 2〜接觸塾; 2643〜接觸墊; 27〜聚焦格子金屬; 2701 、2702 、2703 、2704 、2705 、2706 、2707 、2708 〜步驟; 2727〜聚焦格子金屬;2823〜接觸塾; 2824〜聚焦結構; 2827〜聚焦袼子金屬; 2830〜蒸鍍鉻層; 2831〜蒸鍍鉬層; 2832〜介電層; 2900〜基底; 2902〜金屬合金層;2904〜保護層; 2906〜多層疊狀物;2908〜污染物; 2910〜光成像材料;3〜爽合層; 3002、3004、3006、3008〜步驟; 3100〜基底, 3102〜第一金屬合金層; 3104〜第二金屬合金層;1012-4065-PF I ALEX.ptd Page 28 2422 ~ opening; 2424 ~ polyamide focusing structure 2 4 2 6 ~ cone material; 2440 ~ dielectric layer; 246 2463 ~ opening; 501159 5. Description of the invention ( 23) 2422 ~ contact pad; 2423 ~ bottom contact pad; 2425 ~ recess; 2430-2431 ~ indium structure; 2 4 4 1 ~ passivation layer; 25 ~ recess; 250 1,2502, 250 3, 2504, 25 0 5, 25 0 6 ~ steps; 2552, 2554 ~ sputtered hafnium layer; 2 5 5 3 ~ evaporated molybdenum layer; 2 6 ~ emitter; 26 ~ cone; 2600 ~ dielectric layer; 2 6 2 4 ~ focusing structure; 2 6 4 2 ~ contact 塾; 2643 ~ contact pad; 27 ~ focus grid metal; 2701, 2702, 2703, 2704, 2705, 2706, 2707, 2708 ~ step; 2727 ~ focus grid metal; 2823 ~ contact 塾; 2824 ~ Focusing structure; 2827 ~ focusing metal; 2830 ~ evaporated chrome layer; 2831 ~ evaporated molybdenum layer; 2832 ~ dielectric layer; 2900 ~ substrate; 2902 ~ metal alloy layer; 2904 ~ protective layer; 2906 ~ multi-layer 2908 ~ contaminants; 2910 ~ photoimaging materials; 3 ~ combination layer; 3002, 3004, 3006, 3008 ~ steps; 3100 ~ Substrate, 3102 ~ first metal alloy layer; 3104 ~ second metal alloy layer;

1012-4065-PF; ALEX.ptd 第29頁1012-4065-PF; ALEX.ptd Page 29

3106〜多層疊狀物; 3110〜光成像材料;32〇2、32〇3、32〇4、32〇6〜 4〜底部電極; 5〜阻層; ’ 6〜介電層。 施例揭露如上,然其並非用以 技藝者,在不脫離本發明之精 潤飾’因此本發明之保護範圍 界定者為準。 雖然本發明已以較佳實 限制本發明,任何熟習此項 神和範圍内,當可做更動與 當事後附之申請專利範圍所3106 ~ multi-layers; 3110 ~ photoimaging materials; 3202, 3203, 3204, 3206 ~ 4 ~ bottom electrode; 5 ~ resistive layer; '6 ~ dielectric layer. The embodiment is disclosed as above, but it is not intended for a craftsman, without departing from the refined decoration of the present invention, therefore, the scope of protection of the present invention is defined. Although the present invention has limited the present invention with better practice, anyone who is familiar with this god and scope, can make changes

請參閱第1圖,第1圖係表示根據本發明之一實施例中 之顯示裝置(display device)之電極結構(electr〇de structure)的形成方法,其中,步驟1〇1係表示進行一金 屬曰金層之 &gt;儿積。第2圖係表示一金屬合金層2沉積於一玻 璃面板1之上。 於本貫施例中’該金屬合金層2係為一鋁合金,並且 該金屬合金層2的厚度為50 0-5000埃。於一特定實施例中 ’上述銘合金係主要由鋁(A1)及鈥(Nd)所構成,並且該鋁 合金中之鈦(Nd)濃度為〇·5至6原子百分比。於另一實施例 中’銘合金之鈥(Nd)濃度為〇· 5至6原子百分比,鈦(Ti)濃 度為0至5原子百分比。 _ 請仍參閱第1、2圖,於另一實施例中之該金屬合金層 2係為一銀合金(siiver alloy),該銀合金中包括有銀 (Ag)、麵(Pd)濃度為〇· 5至2原子百分比、銅(Cu)濃度為0. 5至2原子百分比。於本實施例中,鋁合金中之鈥(Nd)濃度Please refer to FIG. 1. FIG. 1 shows a method for forming an electrode structure of a display device according to an embodiment of the present invention, wherein step 101 refers to performing a metal Said the layer of gold &gt; child product. FIG. 2 shows a metal alloy layer 2 deposited on a glass panel 1. As shown in FIG. In this embodiment, the metal alloy layer 2 is an aluminum alloy, and the thickness of the metal alloy layer 2 is 50-5000 angstroms. In a specific embodiment, the above-mentioned alloy is mainly composed of aluminum (A1) and (Nd), and the titanium (Nd) concentration in the aluminum alloy is 0.5 to 6 atomic percent. In another embodiment, the (Nd) concentration of the alloy is 0.5 to 6 atomic percent, and the titanium (Ti) concentration is 0 to 5 atomic percent. _ Please refer to FIGS. 1 and 2 again. In another embodiment, the metal alloy layer 2 is a siiver alloy. The silver alloy includes silver (Ag) and surface (Pd) concentration. 5 to 2 atomic percent, with a copper (Cu) concentration of 0.5 to 2 atomic percent. In this example, the “(Nd) concentration in the aluminum alloy

501159 五、發明說明(25) 為〇 · 5至6原子百分比。於又一實施例中,該銀合金之鉑 (Pd)濃度為〇· 5至2原子百分比,鈦(Ti)濃度為〇· 〇至2· 〇原 子百分比。於另一實施例中,鋁合金之鈥(Nd )濃度為〇 · 5 至6原子百分比,鈦(Ti)濃度為〇至5原子百分比。 菖糟由該銀合金做為^一黏著層時,該銀合金係可提高 與该玻璃面板1之間的黏著性。於一實施例中,錮黏著層 (molybdenum adhesion layer)的厚度約為 50 0- 1 〇〇〇 埃。 請再參閱第1圖,步驟102係進行一夾合層(cladding 1 ay er)3之沉積。第3圖係表示根據第2圖中之該夾合層3於 完成沉積之後的結構,由圖中可看出該夾合層3係直接發 置於该金屬合金層2之上。 於一實施例中,於第3圖中之該夾合層3係採用鉬(M〇) 鎢(W)合金。於本實施例中,該夾合層3的厚度約為5〇〇 一 4000埃,並且藉由該夾合層3所形成之接觸墊(c〇ntact pad)係可以維持穩定且理想的電性接觸,同時更可減少凸 起物(hi 1 lock)的產生。於本實施例之鉬合金中的鎢濃度 為5-30原子百分比。 雖然於本實施例中採用了以沉積所形成之該夾合層 3、,本發明亦可在不使用該夾合層3的情況下藉由鋁合金層 或銀合金層來減少凸起物的形成,同時亦可藉由鋁合金層 或銀合金層產生相當理想的導電性。 於一實施例中係形成有一擴散阻層(di f fusi〇n barrier layer),该擴散阻層係可採用鈦、氮化鈦 (titani· nitride)或鈦鎢合金(Utanium ^叫^⑼)等501159 V. Description of the invention (25) is 0.5 to 6 atomic percent. In yet another embodiment, the silver alloy has a platinum (Pd) concentration of 0.5 to 2 atomic percent, and a titanium (Ti) concentration of 0.00 to 2.0 atomic percent. In another embodiment, the (Nd) concentration of the aluminum alloy is from 0.5 to 6 atomic percent, and the titanium (Ti) concentration is from 0 to 5 atomic percent. When the silver alloy is used as an adhesive layer, the silver alloy can improve the adhesion with the glass panel 1. In one embodiment, the thickness of the molybdenum adhesion layer is about 50-1000 Angstroms. Referring to FIG. 1 again, step 102 is performed by depositing a cladding 1 ayer 3. FIG. 3 shows the structure of the sandwich layer 3 after the deposition is completed according to FIG. 2. It can be seen from the figure that the sandwich layer 3 is directly placed on the metal alloy layer 2. In an embodiment, the sandwich layer 3 in FIG. 3 is made of molybdenum (M0) tungsten (W) alloy. In this embodiment, the thickness of the sandwich layer 3 is about 500-4000 angstroms, and the contact pad formed by the sandwich layer 3 can maintain stable and ideal electrical properties. Contact, while reducing the generation of bumps (hi 1 lock). The tungsten concentration in the molybdenum alloy of this embodiment is 5-30 atomic percent. Although the sandwich layer 3 formed by deposition is used in this embodiment, the present invention can also reduce the protrusions by using an aluminum alloy layer or a silver alloy layer without using the sandwich layer 3. Formed, at the same time, the aluminum alloy layer or the silver alloy layer can also be used to generate fairly ideal conductivity. In one embodiment, a diffusion barrier layer is formed. The diffusion barrier layer may be titanium, titanium nitride or titanium tungsten alloy (Utanium ^^).

501159 五、發明說明(26) 直接形成於该銀合金之上。於一實施例中,該擴散阻層之 厚度約為5 0 0 - 2 0 0 0埃。值的注意的是,該擴散阻層係可以 不包括有上述之夾合層。 於一實施例中,該金屬合金層2與該夾合層3之沉積作 業係藉由單一濺鑛工具(single sputtering ΐ〇〇1)而達 成,亦即,藉由於該單一濺鍍工具之中依序進行該金屬合 金層2、該夾合層3之沉積。更特別的是,該玻璃面板i係 放置於该濺鍍工具之濺鍍室(sputtering chamber)之中, 於該濺鍍室依序進行該金屬合金層2、該夾合層3的沉積作 業’ Ik後便將该玻璃面板1移出該錢鍍室。相較於習知技 術中藉由兩次個別的濺鍍程序而言,本實施例中所提出的 方法係可以有效降低成本、提高物料通過量(thr〇ughpass )及增加良率(yield)。 不論採用鋁合金或是銀合金接鄰於該夾合層係均可以 得到理想的導電性能,i且藉由此—理想導電性能係可應 用於大型平面顯示器之製作上。相較於習知技術之下,本 發明除了可以防止凸起物之形成及避免在使用鋁金屬時所 可能產生的短路現象之外,同時也可以得到具有平整性之 .疊層及有效地提高生產之良率。 一請再參閱第1圖,步驟103係表示進行遮罩、蝕刻作 $。:本貝施例中’於該玻璃面板i上係以沉積方式形成 有「先^(Photoresist),並且對於該光阻進行圖樣化。501159 V. Description of the invention (26) Formed directly on the silver alloy. In one embodiment, the thickness of the diffusion barrier layer is about 500-200 Angstroms. It is important to note that the diffusion barrier layer may not include the above-mentioned sandwich layer. In one embodiment, the metal alloy layer 2 and the sandwich layer 3 are deposited by a single sputtering tool (single sputtering ing〇〇1), that is, by the single sputtering tool The metal alloy layer 2 and the sandwich layer 3 are sequentially deposited. More specifically, the glass panel i is placed in a sputtering chamber of the sputtering tool, and the metal alloy layer 2 and the sandwich layer 3 are sequentially deposited in the sputtering chamber. After Ik, the glass panel 1 is removed from the coin plating chamber. Compared with two separate sputtering processes in the conventional technology, the method proposed in this embodiment can effectively reduce the cost, increase the throughput (throughpass), and increase the yield. Whether the aluminum alloy or the silver alloy is adjacent to the sandwich layer system, the ideal conductive property can be obtained, and by this, the ideal conductive property system can be applied to the production of large flat displays. Compared with the conventional technology, in addition to preventing the formation of protrusions and avoiding the short-circuit phenomenon that may occur when using aluminum metal, it can also achieve flatness. Lamination and effective improvement Yield of production. Please refer to FIG. 1 again. Step 103 means performing masking and etching for $. : In the present embodiment, “Photoresist” is formed on the glass panel i in a deposition manner, and the photoresist is patterned.

Ik後藉由一溼蝕刻方式對於該玻璃面板1進行蝕刻程序 ,如此以得到所需之列電極(r〇w electr〇des)。於第乜一After Ik, an etching process is performed on the glass panel 1 by a wet etching method, so as to obtain a desired row of electrodes (rww electrodes). Yu Yiyi

五、發明說明(27) 時據二3:中結構在藉由遮罩,作“ 相較於習知枯^ i 。 , ( 筏神了由於本發明係可在單一圖樣步驟 了不+ 及單一餘刻步驟下完成該列電極,除 用如==個!1圖樣步驟來完成之外&quot;亦可不必採 ^ ° 忖中之藉由鉬罩(molybdenum cap)以進行兩 便可有效地降低製作成本、提高物料通 過篁及增加產品之良率。 Ύ &lt; U由於本發明並不需採用乾#刻程序來進行列電極之成 1 _除了 了以省去相關於乾钱刻設備之外,於製作過程中 不S對於底部鋁層產生腐蝕現象,同時亦不會造成該玻璃 面板I的損傷(例如:針孔(pinholes)),並且更不必進行 聚合物帶程序(p〇lymer strip pr〇cess),如此係有助於 物料通過量之增加及良率之提昇。 於一實施例中,蝕刻程序係會形成具有角度之邊緣 (angled edges)。於本實施例中所採用之蝕刻劑係包括有 銷酸(nitric acid)、攝酸(phosphoric acid)、醋酸 (acetic acid)及水,如此便可在該蝕刻劑的作用下形成 該光阻及於該底部電極4之側邊上形成具有角度的邊緣。 在具有角度之邊緣的作用下係可以得到均勻的疊層結構, 並且可以降低各疊層於成型過程中所可能產生的脆裂。 請再參閱第I圖’步驟104係表示進行一阻層之沉積作 業。於第5A-5B圖中,阻層5係疊置於底部電極4之上,並 且該阻層5之厚度約為2 0 0 0 - 4 0 0 〇埃。於本實施例中,該阻V. Explanation of the invention (27) According to the second 2: the structure is made by masking, "compared to the conventional dry ^ i., () The god of rafts because the present invention can be done in a single pattern step + and a single Complete the column of electrodes in the remaining steps, in addition to using the == one! 1 pattern step to complete &quot; You can also use the molybdenum cap (molybdenum cap) in the ^ ° 忖 to perform two can effectively reduce Production cost, increase material passing rate and increase product yield. Ύ U Because the present invention does not require the use of dry # engraving procedures for the formation of column electrodes 1 _ In addition to eliminating the related equipment for dry money engraving In the manufacturing process, no corrosion of the bottom aluminum layer is caused, and the glass panel I will not be damaged (for example, pinholes), and it is not necessary to perform a polymer strip process. 〇cess), which is helpful to increase the throughput and improve the yield. In one embodiment, the etching process will form angled edges. The etchant used in this embodiment Departments include nitric acid, phosp horic acid), acetic acid and water, so that the photoresist can be formed under the action of the etchant and an angled edge can be formed on the side of the bottom electrode 4. Under the effect of the angled edge It can obtain a uniform layered structure, and can reduce the brittle cracks that may occur during the forming process of each layer. Please refer to FIG. I. 'Step 104 indicates that a resistive layer deposition operation is performed. In pages 5A-5B In the figure, the resistive layer 5 is stacked on the bottom electrode 4, and the thickness of the resistive layer 5 is about 2000-4000 angstroms. In this embodiment, the resistive layer 5 is

1012-4065-PF ; ALEX.ptd 第33頁 501159 五 發明說明(28) 層5係由厚度約為2000 - 4000埃之碳化矽(Sic)戶/ 方式係可藉由濺鍍程序或化學沉積程序來達成所形成,其 隨後’ ϋ由第1圖中之步驟105以沉積 二 6,並且於一實施例中之介電層係可採用二氧_=曰 而製成。於本實施例中,由二氧切所形成 2 採用電聚輔助化學氣相沉積法(plasma enhaneed 係 chemical vapor dep〇siti〇n pr〇cess)而形社 6A-,圖’第6A-6B圖係表示第5A,圖中之實施例月於乡完成第 々;丨電層6之沉積後之結構圖。 積r η之戈驟106係表示進行一金屬合金層11之沉 ’該金屬合金層11之厚度約為500-:夕第7ΑΓΒ圖係表示該金屬合金層11沉積於該介電 :之上的結構圖,於一實施例中之該金屬合金層i ,合金所形成。於特定的實施例中,該銘合金中包括有 1、钕濃度為0.5至2原子百分比、鈦濃度為〇至5原子百分 比0 參斤卜,“金屬曰金層u力、1採用銀合金來完成。於一 中’該:屬合金層11包括有銀、翻濃度為0.5至2原 子百分比、銅濃度為〇.〇至2原子百分比。 當藉由該銀合金做為—^ . ^ Α • 又為黏耆層時,該銀合金係可提高 與该玻璃面板1之間的黏著性。 ^ ^ , 今m — 沾耆性於一實施例中,鉬黏著層 之厚度約為500- 1 000埃。1012-4065-PF; ALEX.ptd page 33 501159 Five invention descriptions (28) Layer 5 is made of silicon carbide (Sic) with a thickness of about 2000-4000 Angstroms / method can be by sputtering process or chemical deposition process To achieve the formation, it is subsequently performed by step 105 in FIG. 1 to deposit two 6 and the dielectric layer in one embodiment may be made of dioxin. In the present embodiment, 2 formed by dioxygen cutting is applied to the plasma-assisted chemical vapor deposition method (plasma enhaneed system chemical vapor dep〇siti〇n pr〇cess), and the shape of the company 6A-, Figure '6A-6B It is shown in Figure 5A. The example in the figure completes the first step in the township; the structure diagram after the deposition of the electrical layer 6. The step 106 of the product r η indicates that a metal alloy layer 11 is settled. The thickness of the metal alloy layer 11 is about 500-: 7. The 7AΓB diagram shows that the metal alloy layer 11 is deposited on the dielectric: Structure diagram, the metal alloy layer i, an alloy is formed in an embodiment. In a specific embodiment, the Ming alloy includes 1, a neodymium concentration of 0.5 to 2 atomic percent, and a titanium concentration of 0 to 5 atomic percent. Finished. In one of the 'this: metal alloy layer 11 includes silver, the concentration is 0.5 to 2 atomic percent, and the copper concentration is 0.00 to 2 atomic percent. When the silver alloy is used as-^. ^ Α • When it is an adhesive layer, the silver alloy can improve the adhesion with the glass panel 1. ^ ^, this m — Adhesiveness In one embodiment, the thickness of the molybdenum adhesive layer is about 500-1 000 Aye.

501159 五、發明說明(29) 積之後的結構, 金屬合金層1 1之 於一實施例 (Mo)嫣(W)合金( 50 0-40 00 埃,並 維持穩定且理想 成。 雖然於本實 ’本發明亦可在 或銀合金層來減 或銀合金層產生 係藉由一銀合金 例中之擴散阻層 於該銀合金之上 埃。 由圖中可看出該夾合層12係直接疊置於 上。 中,於第3圖中之該夾合層丨2係採用鉬 於本實施例中,該失合層丨2的厚度約為 且藉由该夾合層1 2所形成之接觸墊係可以 的電性接觸,同時更可減少凸起物的形 施例中採用了以沉積所形成之該夾合層12 不使用該夾合層12的情況下藉由鋁合金層 少凸起物的形-成,同時亦可藉由鋁合金層 相當理想的導電性。於一實施例之結構中 及一擴散阻層取代該夾合層丨2。於一實施 係採用鈦、氮化鈦或鈦鎢合金等直接形成 ’並且该擴散阻層之厚度約為5〇〇_2〇〇〇 實ί例中,該金屬合金層11與該夾合層12之沉積 /、’、精由單一濺鍍工具而達成。相較於習知技術中藉由 2個別的濺鍍程序而t ’本實施例中所提出的方法係可 放降低成本、提南物料通過量及增加良率。501159 V. Description of the invention (29) After the product, the metal alloy layer 11 is an embodiment of the (Mo) Yan (W) alloy (50 0-40 00 Angstroms), and it is stable and ideal. 'The present invention can also reduce or produce a silver alloy layer on the silver alloy layer by diffusing a silver alloy layer on the silver alloy, as shown in the figure. The sandwich layer 12 is directly In the above figure, the sandwich layer 2 in FIG. 3 is made of molybdenum. In this embodiment, the thickness of the mismatch layer 2 is about and formed by the sandwich layer 12. The contact pads can be electrically contacted, and at the same time, the shape of the protrusions can be reduced. In the embodiment, the sandwich layer 12 formed by deposition is used. The aluminum alloy layer is less convex when the sandwich layer 12 is not used. The formation and formation of the object can also be achieved by the aluminum alloy layer with a relatively ideal conductivity. In the structure of an embodiment and a diffusion resistance layer to replace the sandwich layer 丨 2. In an implementation system using titanium, nitride Titanium or titanium-tungsten alloy, etc. are formed directly, and the thickness of the diffusion barrier layer is about 500-2 00. In the example, the metal compound The deposition of the gold layer 11 and the sandwich layer 12 is achieved by a single sputtering tool. Compared with the conventional technology, the method proposed in this embodiment is t '2 separate sputtering procedures. It can reduce the cost, increase the throughput of the material and increase the yield.

請參閱第1圖,步驟108係表示藉由遮罩、蝕刻步驟以 &gt;成頂部電極(upper electr〇de),並且於本實施例中係 溼蝕刻方式來進行電極之成型。第9Α —9β圖係表示根 yA 8B中之結構於在藉由遮罩、蝕刻步驟完成該頂部 ' 4的成型之後的結構。於一實施例中所採用之蝕刻劑Referring to FIG. 1, step 108 indicates that the upper electrode is formed by masking and etching steps, and the electrode is formed by a wet etching method in this embodiment. Figures 9A to 9β show the structure of the structure in the root yA 8B after the forming of the top portion 4 is completed by the masking and etching steps. Etchant used in an embodiment

1012-4065-PF (.ptd 第35頁 501159 五、發明說明(30) Ξ = : 磷酸、醋酸及水,如此便可在該钮刻劑的 在具有角度之邊緣的作用下係ΐ以 的脆裂。 民各豎層於成型過程中所可能產生 不°w採用鋁δ金或疋銀合金接鄰於該夾合層係均可以 電性能’並且藉由此-理想導電性能= 之製作1。相較於習知技術之下,本 =了可…凸起物之形成及避免在使用紹金屬時所 二:產生的姐路現象之外’ @時也可以得到具有平整性之 :層及有效地提高良率。再者,由於本發明係可在單一圖 ΐ步驟及單一蝕刻步驟下完成該列電極1了不需藉由兩 的個別圖樣步驟及兩次㈣步驟,#此便可有效地降低 製作成本、提高物料通過量及增加產品之良率。 ,請參閱第1圖之步驟109,該步驟係表示藉由沉積步驟 形成一鈍化層(passivation layer)15。於一實施例中, 該鈍化層15係藉由氮化矽材料在電漿辅助化學氣相沉積法 所形成。請參閱第10A-10B圖,第10A-10B圖係表示第 •9 A 9 B圖中所示之結構於完成該鈍化層丨5之沉積後的結構 圖0 請參閱第1圖之步驟1 〇 9,該步驟係表示進行遮罩、蝕 刻步驟。第11A-11B圖係表示第1〇A-1〇b圖中所示之結構於 在藉由遮罩、#刻步驟以形成開口(〇peningS)lH8後的 結構圖,其中,於該開口 1 7 —丨8位置之外的該鈍化層丨5係1012-4065-PF (.ptd Page 35 501159 V. Description of the invention (30) Ξ =: Phosphoric acid, acetic acid and water, so that the button engraving agent can be made brittle under the action of angled edges It is possible that the vertical layers in the forming process do not adopt aluminum δ gold or rhenium-silver alloy adjacent to the sandwich layer, which can have electrical properties', and from this-ideal conductive properties = production 1. Compared with the conventional technology, Ben = can ... the formation of protrusions and avoiding the use of Shao metal Second: the phenomenon of the sister road can be obtained when the @ @ can also have a flatness: layer and effective In addition, since the present invention can complete the row of electrodes 1 in a single patterning step and a single etching step, there is no need to use two separate pattern steps and two stepping steps. #This can effectively Reduce production cost, increase material throughput and increase product yield. Please refer to step 109 in FIG. 1. This step means forming a passivation layer 15 by a deposition step. In an embodiment, the Passivation layer 15 is a plasma-assisted chemical gas Formed by phase deposition method. Please refer to Figs. 10A-10B. Figs. 10A-10B show the structure of the structure shown in Fig. 9 A 9 B after the deposition of the passivation layer. Step 1 of Fig. 1 is a step of performing masking and etching. Figs. 11A-11B show the structure shown in Figs. 10A-10b. In order to form an opening (〇peningS) lH8 structure diagram, the passivation layer 丨 5 series outside the opening 17-8 position

501159501159

延伸至該頂部電極1 4的上側。 合厲隨V藉二第1圖中之步驟111以沉積方式形成-問極 ϋ m ),並且於一實施例中係採用路做為閘極 金屬。第12A-12B圖係表示第llA-11B圖中所示之壯構於在 藉由沉積方式形成該閘極金屬20。於另—實施例中,該 極金屬20的成型係先藉由沉積方式形成—鈦層,隨後^二 &gt;儿積方式於該鈦層上形成一鉻層,藉由該鈍化層1 5於沉積 過程中對於該頂部電極1 4進行保護。 、 明參閱第1圖之步驟112 ’該步驟係表示藉由遮罩、餘Extends to the upper side of this top electrode 14. Heli is formed by the deposition method of step 111 in FIG. 2 with the V-electrode 问 m), and in one embodiment, a road is used as the gate metal. Figures 12A-12B show the structure shown in Figures 11A-11B in forming the gate metal 20 by deposition. In another embodiment, the forming of the electrode metal 20 is first formed by a deposition method—a titanium layer, and then a two-layer method is used to form a chromium layer on the titanium layer, and the passivation layer 15 is formed on the titanium layer. The top electrode 14 is protected during the deposition process. For details, please refer to step 112 in FIG. 1 ′ This step means that

刻步驟以形成一陈極結構(gate structure)。第13A- 13B 圖係表示第11 A-11 B圖中所示之結構於在藉由遮罩、餘刻 步驟以形成該閘極結構21之後的結構圖,其中,攔接觸墊 (column contact pad)22係可用以接觸於該頂部電極!4, 並且藉由該鈍化層1 5於該閘極結構2 1之遮罩、蝕刻過程中 對於該頂部電極1 4進行保護。 於一般的製程中係可藉由第1圖中之步驟11 3以形成一 陰極結構(cathode structure)。第14A-14B圖係表示根據 一實施例中之完整的陰極結構,藉由一般製程步驟係可形 成凹部(cavi ty )221及在該凹部221中形成射極26,並且利 用遮罩、蝕刻步驟係用以對於第11 B圖中之開口 1 6進行延 伸’如此便可將列接觸墊(row contact pad)23進行曝 光。此外,藉由一般製程步驟(process steps)亦可形成 聚焦結構24及聚焦格子金屬(focus waffle metal)27,於 一實施例中之聚焦格子金屬27係由鋁所形成。於本實施例Carving steps to form a gate structure. Figures 13A-13B are structural diagrams showing the structure shown in Figures 11A-11B after forming the gate structure 21 by masking and remaining steps. Among them, the column contact pad (column contact pad) ) 22 series can be used to touch the top electrode! 4. The top electrode 14 is protected by the passivation layer 15 during masking and etching of the gate structure 21. In a general process, a cathode structure can be formed by step 11 3 in FIG. 1. Figures 14A-14B show a complete cathode structure according to an embodiment. A cavity 221 and an emitter 26 can be formed in the cavity 221 by a general process step, and a mask and an etching step are used. It is used to extend the opening 16 in FIG. 11B so that the row contact pad 23 can be exposed. In addition, the focus structure 24 and the focus waffle metal 27 can also be formed through general process steps. In one embodiment, the focus grid metal 27 is formed of aluminum. In this embodiment

1012-4065-PF ; ALEX.ptd 第37頁 501159 五、發明說明(32) 中之違製程步驟係包括離子撞擊(i〇n bombardment)、凹 部蝕刻(cavity etch)、錐體沉積(c〇ne dep〇siti〇n)、介 電》儿積(dielectric deposition)、介電層之遮罩與餘 刻、聚醯亞胺沉積等。 在陰極結構之成型期間,該頂部電極丨4係藉由該鈍化 f 1 5所保護,如此可避免該頂部電極丨4於一般製程步驟中 文到破壞,並且可以防止該頂部電極丨4之短路及凹陷的產 生。此外,由於該頂部電極丨4受到該鈍化層丨5的保護,如 此則可避免於溶塊密封區域(frit seal regi〇n)之中形成 欄短路(column shorts),並且本實施例在相較於習知技 少的曝光金屬,同時也可以減少攔相對於該 t焦札子金屬的短路現象。 請參閱第15a-f圖,箆於生一 口 弟15a_i圖係表不用以形成一平面 i :二〜ί :電極結構方法的第二實施例。步驟101係 屬合金層之沉積,隨後藉由步驟1 〇2進行- 成;I邱之二積。步驟1 〇3係表示藉由遮罩、蝕刻作業以形 步驟m係表示藉由沉積仃-阻層之沉積作業’ 步驟1〇6進行一金屬人一介電層。隨後,藉由 •禆i隹扞一 tα 金層之孔積程序,進而藉由步驟107 之沉積。步驟108係表示藉由遮罩、蚀刻 全相同於mi FI + e a 本貝例中之步驟10卜1 08係完 王相同於第1圖中之步驟10卜108, 1〇卜108以形成·Α_9Β圖所示之叮猎由。玄步驟 請參閱第1 5圖,步驟11 i传声_ /哪1 i i係表不以沉積方式形成一閘1012-4065-PF; ALEX.ptd page 37 501159 V. The process steps in the invention description (32) include ion bombardment, cavity etch, and cone deposition. deposition), dielectric "dielectric deposition", masking and etching of dielectric layer, polyimide deposition, etc. During the formation of the cathode structure, the top electrode 丨 4 is protected by the passivation f 1 5, so that the top electrode 丨 4 can be prevented from being destroyed in the general process steps, and the short circuit of the top electrode 丨 4 can be prevented. The generation of depressions. In addition, since the top electrode 丨 4 is protected by the passivation layer 丨 5, column shorts can be prevented from being formed in the frit seal regiron. In this embodiment, The exposure of the metal with little know-how can also reduce the short-circuit phenomenon of blocking the metal with respect to the t. Please refer to FIGS. 15a-f. The figure 15a_i is not used to form a plane i: 二 〜ί: The second embodiment of the electrode structure method. Step 101 is the deposition of an alloy layer, followed by step 102. I Qiu Zhiji. Step 10 is a step of forming a mask and an etching step. Step m is a step of depositing a samarium-resistive layer. Step 10 is a metal man and a dielectric layer. Subsequently, the pore product procedure of a tα gold layer is defended by 禆 i 隹, and then deposited by step 107. Step 108 means that masking and etching are all the same as step 10 in the FI FI + ea example. The 08 series is the same as steps 10 in step 108 and 10 in step 1 to form A_9B. The picture shows the sting hunting. Mysterious steps Please refer to Fig. 15, step 11 i sound _ / Which 1 i i form does not form a gate by deposition

五、發明說明(33) 極金屬,隨後並B p 成-閘極結$。^由步驟112進行遮罩、姓刻步驟以形 Qh 明參閱第16a-b圖,第I6a-b圖係表示於第 ya - 9b圖中之牡播+朴 夕你μ级摄、°攝在精由步驟11卜1 12以形成閘極結構1601 ^ ^ 於一貫施例中之該閘極結構1 60 1係由鉻所 ^。’、’且該間極結構1601亦可由沉積有鈦層之鉻層所構 万爲=ΪΙ!圖中之步驟10 9-110係表示以藉由沉積、罩幕 ^ V以形成一鈍化層。第16c-16d圖係表示於第 a έ +圖中之結構在藉由步驟10 9—11 〇形成該鈍化層1 6 0 2 2 L !! ί構圖。於一實施例中之該鈍化層1 602係藉由氮化 電名辅助化學氣相沉積法所形成,並且在該鈍化 \ 02 ^形成複數開口 1 6 2 0 - 1 6 2 1,該開口 1 6 2 0 - 1 6 2 1係延 伸通過忒鈍化層16〇2,並且除了於該開口162〇-1621位置 之外,該鈍化層16〇2係延伸至該閘極結構1601的上側。 藉由第15圖中之步驟113便可完成該陰極結構。於第 16E-16J圖中係表示根據本發明之另一實施例中之用以形 成陰極結構之方法,其中,第16E-16F圖係表示第16C-16D 圖中所示之結構係表示在蝕刻步驟形成凹部25之後的結構 圖。其方式係先進行蝕刻步驟,並且利用蒸鍍方式於完成 錐體材料之沉積、介電材料層之沉積後的結構上形成一鉻 層’於一實施例中之鉻層厚度採用約為5〇〇埃。隨後,在 名、纟《構上進行圖樣化及|虫刻化以形成如第1 6 G _ 1 g Η圖中之 結構。於第16G-16Η圖中所示之結構包括有介電材料 16 54、錐體26、錐體材料1 653及鉻1 640。於一實施例中,V. Description of the invention (33) Electrode metal, and then B p -gate junction $. ^ Mask by step 112, the step of engraving the last name is Qh. Refer to Figures 16a-b. Figures I6a-b are shown in Figure 9-9b. The steps 11 to 12 are used to form the gate structure 1601 ^ In the conventional embodiment, the gate structure 1 60 1 is made of chromium ^. ′, ’And the inter-electrode structure 1601 may also be formed of a chromium layer deposited with a titanium layer. Step 10 9-110 in the figure indicates that a passivation layer is formed by deposition and masking. Figures 16c-16d show the structure in Figure a + and the passivation layer 1 6 0 2 2 L !! is patterned in steps 10 9-11. In one embodiment, the passivation layer 1 602 is formed by a nitride-assisted chemical vapor deposition method, and a plurality of openings 1 6 2 0-1 6 2 1 are formed in the passivation. The opening 1 The 6 2 0-1 6 2 1 series extends through the hafnium passivation layer 160 2, and the passivation layer 160 2 extends to the upper side of the gate structure 1601 except for the positions 1620-1621 of the opening. The cathode structure can be completed by step 113 in FIG. 15. 16E-16J shows a method for forming a cathode structure according to another embodiment of the present invention, wherein 16E-16F shows a structure shown in 16C-16D shown in the etching The structural diagram after forming the recessed part 25 in a step. The method is to first perform an etching step, and use a vapor deposition method to form a chromium layer on the structure after completing the deposition of the cone material and the deposition of the dielectric material layer. In one embodiment, the thickness of the chromium layer is about 50%. 〇Angels. Subsequently, patterning and worm-carving were performed on the structures of Ming and Qing to form the structure as shown in Figure 16 G _ 1 g. The structures shown in Figures 16G-16 (a) include a dielectric material 16 54, a cone 26, a cone material 1 653, and chromium 1 640. In one embodiment,

501159 五、發明說明(34) 錐體材料1 653係由蒸鍍的鉬層所形成,並且錐體26宜採用 其它材料來形成。隨後,利用罩幕、蝕刻步驟形成複數開 口 1 6 5 6以對該底部電極4之部分區域進行曝光,如此便可 形成底部接觸墊23。在完成了聚醯亞胺24及聚焦格子金屬 2 7的成型之後’便可對於該結構進行介電移除步驟 (dielectric removal steps)及環型蝕刻(halo etch)。 於第1 6 I - 1 6 J圖中係表示一完整陰極結構,該陰極結構包 括有聚醯亞胺24、聚焦格子金屬27及頂部接觸墊22。 在陰極結構之成型期間,該頂部電極丨4係藉由該閘極501159 V. Description of the invention (34) The cone material 1 653 is formed by vapor-deposited molybdenum layer, and the cone 26 should be formed of other materials. Subsequently, a plurality of openings 1 6 5 6 are formed by using a mask and an etching step to expose a part of the bottom electrode 4 so that the bottom contact pad 23 can be formed. After the polyimide 24 and the focus grid metal 27 are formed, the structure can be subjected to dielectric removal steps and halo etch. A complete cathode structure is shown in Figures 16 I-16 J. The cathode structure includes polyimide 24, focusing grid metal 27, and top contact pad 22. During the formation of the cathode structure, the top electrode

金屬結構1 60 1及鈍化層丨5所保護,如此可避免該頂部電極 1 4於一般製程步驟中受到破壞,並且可以防止該頂部電極 1 4之紐路及凹陷的產生。此外,由於該頂部電極丨4受到該 鈍化層1 5的保護,如此則可避免於熔塊密封區域之中形成 攔短路,並且本實施例在相較於習知技術下係具有較少的 曝光金屬,同時也可以減少攔相對於該聚焦格子金屬的短 路現象。The metal structure 1 60 1 and the passivation layer 5 are protected. In this way, the top electrode 14 can be prevented from being damaged in the general process steps, and the button and the depression of the top electrode 14 can be prevented. In addition, since the top electrode 4 is protected by the passivation layer 15, a short circuit can be prevented from being formed in the frit sealing area, and the present embodiment has less exposure than the conventional technology. Metal can also reduce short-circuiting with respect to the focusing grid metal.

凊參閱第17圖,第17圖係表示形成一平面顯示裝置用 之一電極結構的另一方法。步驟2〇1係表示形成底部電極 於一基底之上,隨後藉由步驟2 〇2-203將一阻層及一介電 層,儿積於该底部電極之上。於一實施例中之步驟2〇2_2〇 3 係完全相同於第1圖中之步驟1〇1—丨。 請仍參閱第17圖,步驟204係用以沉積形成一問極金 屬,於-實施例中之閘極金屬係可採用鉻來形成。 藉由步驟205係可形成一上部電極’於一實施例中之凊 Refer to FIG. 17, which shows another method of forming an electrode structure for a flat display device. Step 201 refers to forming a bottom electrode on a substrate, and then a resistive layer and a dielectric layer are stacked on the bottom electrode by step 2002-203. In one embodiment, the step 202- 02 is exactly the same as the step 101- 丨 in the first figure. Referring still to FIG. 17, step 204 is used to deposit an interrogation metal, and the gate metal system in the embodiment can be formed using chromium. An upper electrode ’can be formed in step 205 in an embodiment.

501159501159

忒上,,極係可採用第i、15圖中之步驟1〇6-1〇8來形成。 於一實轭例中,該上部電極係藉由對於一金屬合金層(鋁 合金)進行沉積、對於該金屬合金層進行罩幕及蝕刻後而 形成。於了特定實施例中,金屬合金層之厚度約為500-5000埃,並且於該金屬合金層中包括鋁(Ai)及鈥(Nd),其 中,鈥(Nd)/辰度為〇 · 5至β原子百分比。於另一實施例之鋁 。金中之鉉(Nd)濃度為〇.5至6原子百分比,而鈦濃度 為0至5原子百分比。 第18A-18B圖係表示在完成步驟2〇卜2〇5之結構圖,於 第18A- 18B圖中之結構係包括有設置於該基底^上的底部 電極4、阻層5、介電層6、閘極金屬層1801及頂部電極 靖丹翏閲弟1『圖,藉由步驟20 6之罩幕及蝕刻步驟 ,於第1 8A-18B圖中之閘極金屬層丨8〇1進行選擇性蝕 並且在將光阻沉積於該背板之後便可對於該光阻進行圖 =,隨後再以湮蝕刻方式對於該背板進行蝕刻。On the other hand, the pole system can be formed by using steps 106-108 in Figs. In a real yoke example, the upper electrode is formed by depositing a metal alloy layer (aluminum alloy), masking and etching the metal alloy layer. In a specific embodiment, the thickness of the metal alloy layer is about 500-5000 angstroms, and aluminum (Ai) and “(Nd)” are included in the metal alloy layer, where “(Nd) / Chen is 0.5. To β atomic percent. In another embodiment of aluminum. The concentration of osmium (Nd) in gold is 0.5 to 6 atomic percent, and the concentration of titanium is 0 to 5 atomic percent. Figures 18A-18B are structural diagrams showing the completion of steps 20b-205. The structures in Figures 18A-18B include a bottom electrode 4, a barrier layer 5, and a dielectric layer disposed on the substrate 6. The gate metal layer 1801 and the top electrode Jing Dan 翏 弟 1 "Figure, through the mask and etching steps of step 20 6, select the gate metal layer in Figures 18A-18B 丨 801 After the photoresist is deposited on the backplane, the photoresist can be patterned, and then the backplane is etched by etch-back.

圖係表示於第18A 一 18B圖中之結構在藉 驟以形成閘極金屬結構1811之後的結構圖。 蝕J 第17圖之步驟207係表示藉由沉積方 ,於一實施例中之該鈍化層係可採用二氧化矽,而复; 方式係可採用電漿輔助化學氣相沉積法來進行。/、形 第17圖之步驟208係表示進行罩幕、丁这 =18E-18F圖m18F圖係表示於第勝⑽圖;j 、,、。構在經由沉積、罩幕及蝕刻步驟所形成之具有複數開The diagram is a structural diagram of the structure shown in Figs. 18A-18B after the step of forming the gate metal structure 1811. Step 207 of FIG. 17 shows that the passivation layer in one embodiment may be made of silicon dioxide, and the method is performed by plasma-assisted chemical vapor deposition. / 、 Shape Step 208 in Fig. 17 indicates that the mask is performed. Ding this = 18E-18F Fig. M18F is shown in the first victory diagram; j ,,,. The structure has multiple openings formed by deposition, masking, and etching steps.

501159 五、發明說明(36) 1 8 20-1821之一鈍化層的結構圖,其中,該開口182〇1821 係延伸通過該鈍化層1 8 3 0,並且除了於該開口丨8 2 〇 —丨8 2 ! 位置之外的該鈍化層1 830係延伸至該頂部電極181〇的上 側。 fk後’藉由第1 7圖中之步驟2 〇 9便可完成該陰極結構 之成型。第18G-18N圖係表示形成該陰極之另一方法。於 第18G圖中之凹部1 825係藉由罩幕及蝕刻方式而形成,並 f在,成該錐體材料之沉積、該介電材料層之沉積之後, 藉由蒸鍍方式將一鉻層形成於上述之結構上,隨後再進行 圖樣化及蝕刻化以形成如同第丨8丨—丨8】圖中所示之結構。 於第181-18J圖包括有錐狀物1826及結構物1891、1892, 其中,該結構物1891、1 892係包括有錐體材料1 853、鉻材 料1840及介電材料丨854。隨後,藉由罩幕及蝕刻步驟以形 成複數開口,藉由這些開口對於該底部電極4之部件進行 曝光,如此便可形成如第18K-18L圖中之底部接觸墊MM 。在完成了聚醯亞胺及聚焦格子金屬的成型之後,便可 於該結構進行介電移除步驟及環型蝕刻。於第18m—i8N圖 广』表陰極結構’該陰極結構包括有頂部接觸塾 18 7、聚焦結構1 824及聚焦格子金屬1 827。於另一 而夫未开圖:右)t僅藉由罩幕及蝕刻步驟形成該結構物1891, 而未形成有該結構物1 8 9 2。 化,之成型期間’該頂部電極181°係藉由該鈍 :Γ 如此可避免該頂部電極1810於製程步驟 中文到破壞,並且可以防止該頂部電極1810之短路及凹陷 第42頁 1012-4065-PF ; ALEX.ptd 501159 五、發明說明(37) 的產生。此外,由於該頂部電極1 8 1 0受到該鈍化層1 8 3 0的 保護,如此則可避免於熔塊密封區域之中形成攔短路,並 且本實施例在相較於習知技術下係具有較少的曝光金屬, 同時也可以減少欄相對於該聚焦格子金屬的短路現象。 請參閱第19圖,第19圖係表示用以形成一平面顯示裝 置用之一電極結構之另一方法。步驟20 1係表示形成底部 電極於一基底之上,隨後藉由步驟202-203將一阻層及一 介電層沉積於該底部電極之上。 清仍參閱第1 9圖’步驟2 0 4係用以進行閘極金屬之沉 積作業,並且於一實施例中之該閘極金屬係可藉由鉻來形 成0 於第19圖中之步驟250係用以進行一鈦層之沉積作業 &gt;,並且藉由步驟205以形成該頂部電極。於本實施例中, 該頂部電極係由鋁合金所製成,並且於一實施例中之該金 屬合金層的厚度約為500_5000埃。 一第18a —18b圖係表示在藉由步驟2〇卜2〇5、25〇完成了 、一鈦層1 802及複數頂部電極1810之後的I ::複i頂::實施例t,底部電極4係用以做為列電極 ^ ^ ^ ^ f 〇 ^ , Γ,, 為列電極之用攔電極’並J藉由複數頂部電極181〇做 «月再參閱第ig圖,藉由步 可選擇性地對於第20Α_2 及蝕刻步驟名 _進行μ作業,並 中^鈦層聰、該閘㈣ 在將先阻沉積於該背板之後便501159 V. Description of the invention (36) 1 8 20-1821 Structure diagram of a passivation layer, in which the opening 18201821 extends through the passivation layer 1 8 3 0 and except for the opening 丨 8 2 〇-丨The passivation layer 1 830 outside the 8 2! Position extends to the upper side of the top electrode 1810. After fk ′, the formation of the cathode structure can be completed by step 209 in FIG. 17. Figures 18G-18N show another method of forming the cathode. The recess 1 825 in FIG. 18G is formed by a mask and an etching method, and after the deposition of the cone material and the deposition of the dielectric material layer, a chromium layer is deposited by evaporation. It is formed on the above structure, and then patterned and etched to form the structure as shown in FIG. Figures 181-18J include a cone 1826 and a structure 1891, 1892. The structure 1891, 1 892 includes a cone material 1 853, a chromium material 1840, and a dielectric material 854. Subsequently, a plurality of openings are formed through the mask and etching steps, and the parts of the bottom electrode 4 are exposed through these openings, so that the bottom contact pads MM as shown in Figs. 18K-18L can be formed. After the polyimide and focused grid metal have been formed, a dielectric removal step and a ring etch can be performed on the structure. In the 18m-i8N figure, the "table cathode structure" includes a top contact 塾 18 7, a focusing structure 1 824, and a focusing grid metal 1 827. On the other side, the figure is not opened: right) t The structure 1891 is formed only by the mask and the etching steps, and the structure 1 8 9 2 is not formed. During the molding, 'the top electrode 181 ° is through the blunt: Γ This can prevent the top electrode 1810 from being damaged during the process steps, and can prevent the short circuit and depression of the top electrode 1810. Page 42-1012-4065- PF; ALEX.ptd 501159 V. Creation of invention description (37). In addition, since the top electrode 18 1 0 is protected by the passivation layer 18 3 0, a short circuit can be prevented from being formed in the frit sealing area, and the present embodiment has the advantages compared with the conventional technology. Less exposure metal can also reduce the short circuit of the column relative to the focus grid metal. Please refer to FIG. 19, which illustrates another method for forming an electrode structure for a flat display device. Step 20 1 indicates that a bottom electrode is formed on a substrate, and then a resistive layer and a dielectric layer are deposited on the bottom electrode by steps 202-203. Qing still refer to FIG. 19 'Step 2 0 4 is used to perform the gate metal deposition operation, and in an embodiment, the gate metal system can be formed by chromium 0 in step 250 in FIG. 19 It is used to perform a deposition operation of a titanium layer, and the top electrode is formed in step 205. In this embodiment, the top electrode is made of aluminum alloy, and the thickness of the metal alloy layer in an embodiment is about 500-5000 angstroms. A figure 18a-18b shows the I :: complex i after the completion of steps 20b, 2050, a titanium layer 1 802, and a plurality of top electrodes 1810 :: Example t, bottom electrode 4 is used as a column electrode ^ ^ ^ ^ f 〇 ^, Γ, is used as a column electrode for the column electrode ', and J is made by a plurality of top electrodes 1810. «Refer to Figure ig again, you can choose by step Perform the μ operation on the 20A_2 and the name of the etching step, and then ^ Titanium layer Satoshi and the gate will be deposited after the first resistance is deposited on the back plate.

501159 五、發明說明(38) 對=該光阻進行圖樣化,隨後再以溼蝕刻方式對於該背板 ,行蝕刻。第20C-20D圖係表示於第2〇a-20B圖中之結構在 藉由罩幕、蝕刻步驟以形成閘極金屬結構丨811、鈦結構 1 8 1 2之後的結構圖。 ' … 第19圖之步驟20 7係表示藉由沉積方式形成一鈍化層 ,於一實施例中之該鈍化層係可採用二氧化矽,而直形成 方式係可採用電漿輔助化學氣相沉積法來進行。/ 請參閱第19圖,步驟208係表示進行罩幕及蝕刻步驟 。請參閱第20E-20F圖係表示於第2〇c_2〇D圖中之結構在經 由沉積、罩幕及蝕刻步驟所形成之具有複數開口 ^2〇之一 =層1 830的結構圖’該開口182〇係延伸通過該純化層 〇。於本實施例中係藉由環型蝕刻以形成凹部1 825。由 183以1看出山除了於該開口 1 820-1 82 1位置之外的該純化層 至該頂部電極1810的上側,並且在後續製程中 係了,由该鈍化層1 830以保護該頂部電極181〇不被破壞。 20G 1由同第Λ圖中之步驟2〇9便可完成該陰極結構。於第 Λ 示根據本發明之另一實施例中之用以形 法,其方式係先進行_步驟,並且利用 •結構上“、一 it Ϊ材4積、介電材料層之沉積後的 / 9 ’隨後在該結構上進行圖樣化及餘刻化 以形成如第20G-20Η圖中:^ έ士嫌 认哲 結槿句杯古八带,中構。於第2〇G — 20H圖中所示之 區h /1才料1 854、錐體1 8 26、錐體材料1 853及鉻 1°85;係:。:1:&quot;!/“11161110184。。於—實施例中’錐體材料 ,、η的鉬層所形成,並且錐體26宜採用其它材料501159 V. Description of the invention (38) The photoresist is patterned, and then the back plate is etched by wet etching. Figures 20C-20D are the structural diagrams of the structure shown in Figures 20a-20B after the mask and etching steps are performed to form the gate metal structure 811 and the titanium structure 1 8 1 2. '… Step 20 7 in FIG. 19 indicates that a passivation layer is formed by a deposition method. In an embodiment, the passivation layer may be silicon dioxide, and the straight formation method may be plasma-assisted chemical vapor deposition. Method to proceed. / Please refer to FIG. 19, step 208 represents performing the masking and etching steps. Please refer to FIGS. 20E-20F. The structure shown in FIG. 20c_2D has a plurality of openings formed through deposition, masking, and etching steps. One of ^ 20 is a structural diagram of layer 1 830. The opening The 1820 series extended through the purification layer 0. In this embodiment, the recess 1 825 is formed by ring-type etching. It can be seen from 183 to 1 that the purification layer except the position of 1 820-1 82 1 at the opening is above the top electrode 1810, and is tied in the subsequent process. The passivation layer 1 830 is used to protect the top electrode. 181〇 is not destroyed. 20G 1 can complete the cathode structure by step 209 in the same figure. Figure Λ shows the method of forming in another embodiment according to the present invention. The method is to perform the _ step first, and use the "structure", a material, a product, and a dielectric material layer after the deposition of / 9 'Subsequent patterning and post-cutting on the structure to form the figure 20G-20Η: ^ 士士 suspected philosopher Jieju Cup ancient eight belts, the middle structure. In Figures 20G-20H The area h / 1 is shown as 1 854, cone 1 8 26, cone material 1 853, and chromium 1 ° 85; Department:.: 1: &quot;! / "11161110184. . In the embodiment, the ‘cone material’ is formed by a molybdenum layer of η, and the cone 26 is preferably made of other materials.

來形成。隨後,利用罩幕蝕 對該底部電極4之部八罩^、隹㈣翼步驟形成複數開口 1 656以 20I-20J ® ^ ^刀區域進仃曝光,如此便可形成如第 20 1 20J圖之底部接觸墊1 823、頂 了聚醯亞胺及聚隹柊子今屬 接觸墊1 822在70成 進行介電移牛二σ子金屬的成型之後,便可對於該結構 -完敫吟極二環型蝕刻。於第20K-20L圖中係表示 格子:il82;。’遠陰極結構包括有聚醯亞胺1 824及聚焦 在陰 層1 8 3 0所 驟中受到 陷的產生 保護,如 且本實施 同時也可 請參 置用之一 電極於一 介電層沉 極結構 保護, 破壞, 。此外 此則可 例在相 以減少 閱第21 電極結 基底之 積於該 之成型期間, 如此可避免該 並且可以防止 ,由於該頂部 避免於熔塊密 較於習知技術 攔相對於該聚 圖,第21圖係 構之另一方法 上,隨後藉由 底部電極之上 該頂部電極1 8 1 0係藉由鈍介 頂部電極1 8 1 0於一般製程歩 5亥頂部電極1 81 〇之短路及氏 電極1 81 0受到該鈍化層1 5 # 封區域之中形成攔短路,潘 下係具有較少的曝光金屬, 焦格子金屬的短路現象。 表示用以形成一平面顯示襄 。步驟201係表示形成底部 步驟202-203將一阻層及一To form. Subsequently, a plurality of openings are formed on the bottom electrode 4 by the mask etching to form a plurality of openings 1 656, and a plurality of openings 1 656 are exposed with a knife region of 20I-20J ® ^ ^. The bottom contact pad 1 823, topped with polyimide and polysacral contact pad 1 822. After the formation of the dielectric shifting sigma metal by 70%, the structure can be completed. Type etching. In the figure 20K-20L, the grid is: il82 ;. 'The far-cathode structure includes polyimide 1 824 and focusing protection in the negative layer 1 830. If this embodiment is implemented at the same time, please use one of the electrodes to deposit on a dielectric layer. Polar structure protection, destruction,. In addition, this example can be used to reduce the product of the 21st electrode junction substrate during the molding process, so that it can be avoided and can be prevented, because the top is prevented from being denser than the frit compared to the conventional technique to the polygraph. Figure 21 shows another method of constructing the structure. Subsequently, the top electrode 1 8 1 0 above the bottom electrode is short-circuited by the passivation top electrode 1 8 1 0 in the general process 歩 5 Hai top electrode 1 81 〇. A short circuit is formed in the sealed region of the 5's electrode 1 81 0 by the passivation layer 1 5 0, and the Panxia system has a short circuit phenomenon of less exposed metal and focal grid metal. The display is used to form a flat display. Step 201 means forming the bottom. Steps 202-203 put a resist layer and a

_ 明仍參閱第2 1圖,步驟2 0 4係用以進行閘極金屬之沉 積作業’並且於一實施例中之該閘極金屬係可藉由鉻來形 成&gt;,隨後藉由步驟205以形成該頂部電極。於本實施例中^ 之忒頂部電極係由鋁合金所製成。於一實施例中之步驟 2〇卜205係完全相同於第17圖中之步驟2〇1一2〇5。 請參閱第22A-22B圖,於第22A-22B圖中之結構係表示_ Still referring to FIG. 21, step 204 is used to perform the gate metal deposition operation 'and the gate metal system in one embodiment can be formed by chromium>, and then by step 205 To form the top electrode. In this embodiment, the top electrode is made of aluminum alloy. The steps 205 to 205 in one embodiment are exactly the same as the steps 205 to 205 in FIG. 17. Please refer to Figures 22A-22B for the structure shown in Figures 22A-22B.

5ϋ11595ϋ1159

藉由步驟20 1 -205以形成具有一閘極金屬層18〇1及複數頂 部電極1810之一基底1,於該基底1之上係疊置有介電層6 、阻層5、底部電極4。 /清再參閱第21圖,藉由步驟20 7係表示藉由沉積方式 形成一純化層,於_實施例中之該鈍化層係可採用二氧化 石夕’而其形成方式係可採用電漿輔助化學氣相沉積法來進 行0 請再參閱第21圖,隨後藉由步驟26〇進行罩幕、蝕刻 步驟。於一實施例中係採用兩次蝕刻步驟(第一次蝕刻、 第二次蝕刻)來分別進行該鈍化層(第一次蝕刻)及該閘極 丨_ 金屬層(第二次蝕刻)之成型,藉由第一罩幕、蝕刻步驟以 對於該鈍化層、該閘極金屬層進行貫穿性蝕刻。 第22C-22D圖係表示於第22Α-22Β圖中之結構在經由沉 積、罩幕及餘刻步驟形成該閘極金屬結構1811及該鈍化層 1 8 3 0的結構圖。 隨後,藉由第21圖中之步驟2〇9便可完成該陰極結構 之成型。第22Ε-22Ν圖係表示形成該陰極之另一方法。一 介電材料層2250係沉積於第22C-22D圖所示之結構上,隨 •後對於該介電材料層2250進行圖樣化及蝕刻化以形成如第 22Ε-22F圖中之結構。在上述的|虫刻過程中,該鈍化層 1藝 1 830係用以做為一 I虫刻播(etch stop),隨後便進行一凹 部蝕刻(cavity etch)。第22G-22H圖中係表示於第22E- 22F圖之結構中的凹部蝕刻在完成凹部1 825後之結構圖。 隨後,藉由濺鍍沉積方式進行一鉬層之沉積,並且將Steps 20 1 -205 are used to form a substrate 1 having a gate metal layer 1801 and a plurality of top electrodes 1810. A dielectric layer 6, a resistive layer 5, and a bottom electrode 4 are stacked on the substrate 1. . / Refer to FIG. 21 again. Step 20 7 indicates that a purification layer is formed by a deposition method. In the embodiment, the passivation layer can be made of stone dioxide, and the formation method can be made of plasma. Auxiliary chemical vapor deposition method is performed. Please refer to FIG. 21 again, and then perform masking and etching steps by step 26. In one embodiment, two etching steps (first etching and second etching) are used to separately form the passivation layer (first etching) and the gate electrode __ metal layer (second etching) Through the first mask and the etching step, penetrating etching is performed on the passivation layer and the gate metal layer. Figures 22C-22D are structural diagrams of the structure shown in Figures 22A-22B in which the gate metal structure 1811 and the passivation layer 1830 are formed through deposition, masking, and remaining steps. Subsequently, the formation of the cathode structure can be completed by step 209 in FIG. 21. Figures 22E-22N show another method of forming the cathode. A dielectric material layer 2250 is deposited on the structure shown in Figs. 22C-22D, and then the dielectric material layer 2250 is patterned and etched to form the structure shown in Figs. 22E-22F. In the above-mentioned insect etch process, the passivation layer 1 830 is used as an etch stop, and then a cavity etch is performed. Figures 22G-22H are structural diagrams showing the recesses etched in the structure of Figures 22E-22F after the completion of the recesses 1,825. Subsequently, a molybdenum layer is deposited by sputtering deposition, and

1012-4065-PF ; ALEX.ptd 第 4β 頁 :&gt;un:)y1012-4065-PF; ALEX.ptd page 4β: &gt; un:) y

錐體材料沉積於該銦層之上。於_實施 =由翻來進行蒸鑛,並且於該錐體材料:行 礼積而上述錐體材料宜採用其它材料來形成。 圖中所不之結構。於第22I-22J圖中所示之蛀 ^##2252 &gt; |,Μ2226 . |,H##2253 ^^t^ 2254^piiA pyramid material is deposited on the indium layer. Yu_Implementation = steaming by turning over, and the cone material: salute product and the above cone material should be formed using other materials. Structure not shown in the picture.蛀 ## 2252 &gt; |, Μ2226. |, H ## 2253 ^^ t ^ 2254 ^ pii

後’精由餘刻步驟形成如同第22K—22L圖之開口“⑼一 2257。請參閱第22M —22N圖,隨後便對於該結構進行介 移除步驟及環型蝕刻以形成複數接觸墊2222、2223,並且 對於聚醯亞胺聚焦結構2224及聚焦格子金屬2227進行成型 在陰極結構的成型期間,該頂部電極丨81 〇係藉由鈍化 層18 3 0所保護,如此可避免該頂部電極丨8丨〇於一般製程步 ,中文到破壞,並且可以防止該頂部電極丨8丨〇之短路及凹 陷的產生。此外,由於該頂部電極181〇受到該鈍化層的保 護,如此則可避免於熔塊密封區域之中形成攔短路,並且 本實施例在相較於習知技術下係具有較少的曝光金屬,同 時也可以減少攔相對於該聚焦格子金屬的短路現象。 請參閱第23-24圖,第23-24圖係表示用以形成一平面 顯示裝置用之一電極結構之另一方法。步驟2〇1係表示形 成底部電極於一基底之上,隨後藉由步驟2〇2_2〇3將_ ‘ 層及一介電層沉積於該底部電極之上。在藉由步驟2〇4以 沉積方式形成一閘極金屬之後,便可藉由步驟2 〇 5對於頂 部電極進行成型。隨後,藉由步驟2〇6之蝕刻步驟以形成The post-finish step is followed by the opening to form an opening like the 22K-22L picture, "a 2257. Please refer to the 22M-22N picture, and then the structure is subjected to a media removal step and a ring-type etching to form a plurality of contact pads 2222. 2223, and the polyimide focusing structure 2224 and the focusing grid metal 2227 are molded. During the forming of the cathode structure, the top electrode 丨 81 〇 is protected by a passivation layer 18 3 0, so that the top electrode 丨 8 can be avoided.丨 〇 In the general process steps, Chinese is destroyed, and the short circuit and depression of the top electrode 丨 8 丨 〇 can be prevented. In addition, since the top electrode 1810 is protected by the passivation layer, it can be avoided from the frit A short circuit is formed in the sealed area, and in this embodiment, compared with the conventional technology, there is less exposed metal, and at the same time, the short circuit of the short circuit with respect to the focusing grid metal can be reduced. Please refer to FIGS. 23-24. Figures 23-24 show another method for forming an electrode structure for a flat display device. Step 201 shows forming a bottom electrode on a substrate, and then borrowing Step 022_2 03 is to deposit a _ 'layer and a dielectric layer on the bottom electrode. After a gate metal is formed by the deposition method in step 204, the step 2 can be used for the top The electrode is formed. Then, an etching step of step 206 is performed to form the electrode.

1012-4065-PF; ALEX.ptd 第 47 頁 五、發明說明(42) &quot; ------- 閘極結,,並且藉由蝕刻步驟23 〇丨以形成一凹部。 於本實施例中,該頂部電極係藉由對於—金屬合金層 J =積及蝕刻步驟而形成,並且於一實施例中之該金屬 二的厚度約為500〜50 0 0埃。於一特定的實施例中之該 金屬a金層中包括铭(A1)及鈹(Nd),其中,歛(Nd)濃度為 你6原子百分比。於另一實施例之鋁合金中之鈦(Nd )濃 度為〇·5至6原子百分比,而鈦(Ti)濃度為〇至5 分 比。 一請參閱第24A-24B圖,第24a — 24b圖係表示在完成步驟 20 206後之基底1的結構圖,該基底1包括有底部電極 4、阻層5、介電層6、閘極金屬層1811及頂部電極181〇, 並且於蝕刻步驟2301中形成凹部2425。 ”請再參閱第23圖,隨後藉由步驟2302進行濺鍍鉬層之 沉積三並且在藉由步驟2303完成了蒸鍍鉬層的沉積之後, 便可藉由步驟2304進行濺鍍鉬層的沉積。請參閱第 24C-24D圖,第24C-24D圖係表示在藉由步驟23〇2 —23〇4完 成了該濺鍍鉬層240 1、該蒸鍍鉬層24〇2、該濺鍍錮層24〇3 及該錐體材料2426之後的結構圖。 曰 • 請仍參閱第23圖,隨後藉由步驟2305以進行罩幕、餘 刻步驟。第24E-24F圖係表示於第24C-24D圖中之結構在藉 由罩幕、蝕刻步驟以形成鉬結構24 30-243 1及一開口 2422曰 之後的結構圖,其中,該開口 2422係延伸至底部電極4之 頂部。於一實施例中,罩幕及蝕刻步驟23〇5係包括兩次個 別的罩幕及蝕刻步驟,其中,第一次罩幕及蝕刻步驟係用1012-4065-PF; ALEX.ptd page 47 V. Description of the invention (42) &quot; ------- Gate junction, and a recess is formed by etching step 23 〇 丨. In this embodiment, the top electrode is formed by a step of forming a metal alloy layer and a step of etching, and in one embodiment, the thickness of the metal two is about 500˜500 angstroms. In a specific embodiment, the metal a gold layer includes indium (A1) and beryllium (Nd), wherein the concentration of Nd is 6 atomic percent of you. In another embodiment, the titanium (Nd) concentration in the aluminum alloy is from 0.5 to 6 atomic percent, and the titanium (Ti) concentration is from 0 to 5 percent. First, please refer to FIGS. 24A-24B, and FIGS. 24a to 24b are structural diagrams of the substrate 1 after completing steps 20 to 206. The substrate 1 includes a bottom electrode 4, a barrier layer 5, a dielectric layer 6, and a gate metal. The layer 1811 and the top electrode 1810, and a recess 2425 is formed in the etching step 2301. Please refer to FIG. 23 again, and then deposit a sputtered molybdenum layer by step 2302. After completing the deposition of the evaporated molybdenum layer by step 2303, the molybdenum layer can be deposited by step 2304. Please refer to Figures 24C-24D. Figures 24C-24D show that the sputtered molybdenum layer 240, the evaporated molybdenum layer 2402, and the sputtered hafnium were completed in steps 2302-2304. The structure diagram after layer 24〇3 and the cone material 2426. Please refer to FIG. 23, and then perform the masking and remaining steps by step 2305. The 24E-24F diagram is shown in 24C-24D The structure in the figure is a structure diagram after forming a molybdenum structure 24 30-243 1 and an opening 2422 through a mask and an etching step, wherein the opening 2422 extends to the top of the bottom electrode 4. In an embodiment The masking and etching step 2305 includes two separate masking and etching steps, of which the first masking and etching step is used

501159 五、發明說明(43) 以對於該濺鍍鉬層2403、該蒸鍍鉬層2402及該濺鍍銦層 240 1進行蝕刻作業,而第二次罩幕及蝕刻步驟係用以對於 該介電層6、該阻層5進行蝕刻作業以形成開口 2 4 2 2。 請參閱第23圖,步驟2306係用以進行一介電層的沉積 作業。於一實施例中,該介電層係採用二氧化矽來製成。 第23圖之步驟2307係用以進行一鈍化層之沉積。於一 貫加例中’该純化層係猎由氮化石夕材料在電漿輔助化學氣501159 V. Description of the invention (43) An etching operation is performed on the sputtered molybdenum layer 2403, the evaporated molybdenum layer 2402, and the sputtered indium layer 2401, and the second mask and etching steps are used for the interface. The electrical layer 6 and the resist layer 5 are etched to form openings 2 4 2 2. Referring to FIG. 23, step 2306 is used to perform a dielectric layer deposition operation. In one embodiment, the dielectric layer is made of silicon dioxide. Step 2307 of FIG. 23 is used for depositing a passivation layer. In the conventional additions, the purification layer is made of a nitride-assisted chemical gas in a plasma-assisted chemical gas.

相沉積法所形成。請參閱第24G-24H圖,第24G-24H圖係表 示第24E-24F圖中所示之結構於完成該介電層2440、該鈍 化層2 4 4 1之沉積後的結構圖。 請參閱步驟2308,隨後藉由步驟2308進行蝕刻、沉積 步驟。由第24I-24J圖中之步驟2308所形成之開口 2450-2452係延伸通過該鈍化層244 1。Formed by phase deposition. Please refer to Figs. 24G-24H, which is a diagram showing the structure shown in Figs. 24E-24F after the deposition of the dielectric layer 2440 and the passivation layer 2 4 4 1. Please refer to step 2308, and then perform the etching and deposition steps in step 2308. The openings 2450-2452 formed by steps 2308 in Figures 24I-24J extend through the passivation layer 2441.

步驟2 3 0 9係用以形成聚焦結構,隨後藉由步驟2 3 1 〇以 進行乾敍刻作業。請參閱第2 4 K - 2 4 L圖,步驟2 3 0 9 - 2 3 1 0係 用以形成聚醯胺聚焦結構2424及開口 246 1 -2463,其中, 該開口2461-2463係延伸通過該鈍化層2440,並且藉由該 開口 2462延伸至該底部接觸墊4之頂面係可以形成底部接 觸墊2423。請參閱第24M圖,於本實施例中之聚焦格子金 屬2 727係形成於該聚醯胺聚焦結構2424之上。 明參閱第24M-24N圖,步驟2311係用以將第24K- 24L·圖 中之開口 246 1、2463以蝕刻的方式延伸通過該濺鍍鉬層 2403、該蒸鍍鉬層2402,如此以形成接觸墊2422,並且在 該步驟2311的蝕刻作用下係可將位於該錐體材料以“上之Step 2309 is used to form a focusing structure, and then step 2310 is used to perform the dry engraving operation. Please refer to FIG. 2 4 K-2 4 L. Step 2 3 0 9-2 3 1 0 is used to form the polyamide focusing structure 2424 and the opening 246 1-2463, wherein the opening 2461-2463 extends through the The passivation layer 2440 can extend to the top surface of the bottom contact pad 4 through the opening 2462 to form a bottom contact pad 2423. Please refer to FIG. 24M. In this embodiment, the focusing grid metal 2727 is formed on the polyamide focusing structure 2424. Refer to Figures 24M-24N. Step 2311 is used to extend the openings 246 1 and 2463 in Figures 24K-24L · through the sputtered molybdenum layer 2403 and the evaporated molybdenum layer 2402, so as to form Contact pad 2422, and under the etching effect of step 2311, the cone material

501159501159

該濺鍍鉬層2 4 0 3、該蒸鍍鉬層2 4 0 2進行移除。 於第23-24圖中,該頂部電極181〇係可藉由該介 2 440、該鈍化層2441的保護以防止在製程中受到損傷。曰此 外’由於該頂部電極1 4受到該鈍化層丨5的保護,如此則可 避免於熔塊密封區域之中形成攔短路,並且本實施例在相 較於習知技術下係具有較少的曝光金屬,同時也可以減少 欄相對於該聚焦格子金屬的短路現象。 /少 請參閱第25-26圖,第25-26圖係表示用以形成一平面 顯示裝置用之一電極結構之另一方法。於第25圖中之步驟 2 0 1係表示形成複數底部電極於一基底之上,隨後藉由步 驟202-203將一阻層及一介電層沉積於該底部電極之上: 步驟204係用以進行閘極金屬之沉積作業,並且於一實施 例中之該閘極金屬係可藉由鉻來形成,隨後藉由步驟2〇6 之罩幕、蝕刻步驟以形成一閘極結構,進而藉由步驟23〇1 進行#刻步驟以形成一凹部。 隨後,藉由步驟230 2-2 304以沉積形成一第一濺鍛翻 層、一蒸鍍鉬層及一第二濺鍍鉬層。於一實施例中,步驟 20 1 -206與步驟230 1 -2304係完全相同於第23圖中之步 20 1 -206 與步驟230 1 -2304。 請參閱第25圖,步驟250 1係以可選擇性的方式對於該 濺鍍鉬層、該蒸鍍鉬層進行罩幕及蝕刻步驟。於本實施例 中,藉由步驟250 1之罩幕及蝕刻步驟係可將頂部電極所預 定疊置之區域上的該濺鍍鉬層、該蒸鍍鉬層完全地移除, 亦即,於本實施例中之蝕刻步驟2 5 0 1係同樣對於鉬結構The sputtered molybdenum layer 2 40 3 is removed. In Figures 23-24, the top electrode 1810 can be protected by the dielectric 2 440 and the passivation layer 2441 to prevent damage during the process. In addition, because the top electrode 14 is protected by the passivation layer 5, short-circuit blocking can be prevented from forming in the frit sealing area, and the present embodiment has less than the conventional technology. Exposing the metal can also reduce the short circuit of the column relative to the focusing grid metal. / Less Refer to FIGS. 25-26, which illustrate another method for forming an electrode structure for a flat display device. Step 201 in FIG. 25 indicates that a plurality of bottom electrodes are formed on a substrate, and then a resistive layer and a dielectric layer are deposited on the bottom electrodes by steps 202-203: step 204 is used The gate metal is deposited. In one embodiment, the gate metal can be formed by chromium, and then a gate structure and an etching step in step 206 are used to form a gate structure. Step # 201 is performed to form a recessed portion. Subsequently, a first sputtering forging layer, a vapor-deposited molybdenum layer, and a second sputtering-molybdenum layer are formed by deposition in steps 230 2-2 304. In one embodiment, steps 20 1 -206 and steps 230 1 -2304 are exactly the same as steps 20 1 -206 and steps 230 1 -2304 in FIG. 23. Referring to FIG. 25, step 2501 is a step of selectively masking and etching the sputtered molybdenum layer and the vapor-deposited molybdenum layer. In this embodiment, the masking and etching steps of step 250 1 can completely remove the sputtered molybdenum layer and the vapor-deposited molybdenum layer on the area where the top electrode is intended to be stacked, that is, in The etching step 2 5 0 1 in this embodiment is also the same for the molybdenum structure.

1012-4065-PF : ALEX.ptd1012-4065-PF: ALEX.ptd

501159 五、發明說明(45) 2431進行移除作業。 請參閱第25圖,步驟2502係用以進行一介電層之沉積 ’並且於一實施例中之該鈍化層係可採用二氧化矽來形 成0 請參閱第26A-26B圖,第26A-26B圖係表示在完成 第25圖中之步驟2501-2502後之一基底1的結構圖,該基底 1包括有介電層2600、鉬層2401、蒸鍍鉬層2402及濺鍍鉬 層2403,如此便可繼而形成錐體材料181〇,並且於該介電501159 V. Description of the invention (45) 2431 Carry out the removal operation. Please refer to FIG. 25. Step 2502 is used to deposit a dielectric layer. In one embodiment, the passivation layer may be formed using silicon dioxide. See FIGS. 26A-26B and 26A-26B. The figure shows the structure of one of the substrates 1 after completing steps 2501-2502 in FIG. 25. The substrate 1 includes a dielectric layer 2600, a molybdenum layer 2401, a vapor-deposited molybdenum layer 2402, and a sputtered molybdenum layer 2403. Can then form a cone material 1810, and the dielectric

層6、5亥阻層5及該底部電極4之上係疊置有該閘極金屬層 1 8 11、該頂部電極丨8丨〇。 曰The gate metal layer 1 8 11 and the top electrode 丨 8 丨 are stacked on the layer 6 and the resistance layer 5 and the bottom electrode 4. Say

請參閱第25圖,隨後藉由步驟2305以進行罩幕、飴刻 步驟。於一實施例中,罩幕及蝕刻步驟2503係包括有三次 罩幕及餘刻步驟(第一次罩幕及蝕刻、第二次罩幕及茲一 刻、第三次罩幕及蝕刻),其中,第一次罩幕及蝕刻係用 以形成第26C-26D圖中之結構,第二次罩幕及蝕刻係用以 形成第26E-26F圖中之結構,以及第三次罩幕及蝕刻係用 以形成第26G-26H圖中之結構。請參閱第26G-26H圖,該第 一〜人罩幕及蝕刻係用以形成一開口,該開口係延伸至該底 部電極4,如此以形成接觸墊2643。於本實施例中,該第一 一〕二次罩幕及蝕刻係採用乾蝕刻,而該第三次罩幕及蝕 刻係採用溼蝕刻。此外,本發明亦可適用於藉由其它罩幕 及餘刻方式以形成第26G —26H圖中所示之結構。 步驟2504係用以形成複數聚焦結構2624。請參 261圖,聚焦格子金屬2627係形成於該聚焦結構“^之Please refer to FIG. 25, and then perform the masking and engraving steps by step 2305. In an embodiment, the masking and etching step 2503 includes three masking and etching steps (the first masking and etching, the second masking and one moment, and the third masking and etching), wherein The first mask and etching are used to form the structure in Figure 26C-26D, the second mask and etching are used to form the structure in Figure 26E-26F, and the third mask and etching are Used to form the structure in Figures 26G-26H. Please refer to FIGS. 26G-26H. The first mask and the etching are used to form an opening, and the opening extends to the bottom electrode 4 so as to form a contact pad 2642. In this embodiment, the first and second masks and etching are dry etching, and the third mask and etching are wet etching. In addition, the present invention can also be applied to form the structure shown in Figures 26G-26H by other masks and time-cutting methods. Step 2504 is used to form a complex focusing structure 2624. Please refer to Figure 261. The focusing grid metal 2627 is formed in the focusing structure "^ 之

1012-4065-PF; ALEX.ptd 第51頁 5011591012-4065-PF; ALEX.ptd page 51 501159

五、發明說明(46) 上’並且藉由第25圖中之步驟2505之蝕刻步驟以對於剩餘 的介電層進行更進一步的蝕刻作業。於一實施例中,蝕刻 步驟2504係採用乾蝕刻方式來進行。請參閱第26I—26J 圖,在藉由步驟2504形成該聚焦結構2624之後,藉由步驟 2505以形成接觸墊2642。 如第26K-26L圖所示’本實施例中係藉由步驟25〇6將 該蒸鍍鉬層2553、該濺鍍鉬層2 552及2 5 54進行移除。5. Description of the invention (46) on 'and further etching operation is performed on the remaining dielectric layer by the etching step of step 2505 in FIG. 25. In one embodiment, the etching step 2504 is performed by a dry etching method. Please refer to FIGS. 26I-26J. After the focusing structure 2624 is formed in step 2504, the contact pad 2642 is formed in step 2505. As shown in FIGS. 26K-26L, in this embodiment, the vapor-deposited molybdenum layer 2553, the sputtered molybdenum layers 2 552, and 2 5 54 are removed in step 2506.

該頂部電極181 0係可藉由該介電層26〇〇的保護下以防 止在製程中受到損傷,並且可以防止該頂部電極181〇形成 不當的短路及開路-。此外,由於該頂部電極181〇受到該介 電層2600的保護,如此則可避免於熔塊密封區域之中形成 欄短路,並且本實施例在相較於習知技術下係具有較少的 曝光金屬’同時也可以減少攔相對於該聚焦格子金屬的短 路現象。 請參閱第27-28圖,第27-28圖係表示用以形 =ΓΛ置用之—電極結構之另—方法。於第27圖之步驟 201係表示形成底部電極於一基底之上,後 2 0 2-203將一阻層及一介電層沉積於該底部電=驟The top electrode 1810 can be protected by the dielectric layer 2600 to prevent damage during the process, and the top electrode 1810 can be prevented from forming an improper short circuit and open circuit. In addition, since the top electrode 1810 is protected by the dielectric layer 2600, the formation of a short circuit in the frit sealing area can be avoided, and the present embodiment has less exposure than the conventional technology. At the same time, 'metal' can also reduce short-circuiting with respect to the focusing grid metal. Please refer to Figs. 27-28. Figs. 27-28 show another method for forming an electrode structure. Step 201 in FIG. 27 indicates that a bottom electrode is formed on a substrate, and then a resistive layer and a dielectric layer are deposited on the bottom electrode.

極金屬牛之沉積作業,隨後藉由步㈣ 一閘極結構,並且藉由钱=3罩〇1 幕以:^ 實施例中,步驟2(Π-206與230 1係完全相π於赞凹#。於 步驟20卜2〇6與230 1。 f -王相冋於第23圖中之 請參閱第2 7圖 步驟2 70 1係用 以’儿積形成一蒸艘鉻The deposition operation of the polar metal cow is followed by a step-gate structure and a coin = 3 cover. The screen is: ^ In the embodiment, step 2 (Π-206 and 230 1 are completely in phase with Zan concave. #。 In step 20, 2206 and 230 1. f-Wang Xiangyu in Figure 23, please refer to Figure 2 7 Step 2 70 1 is used to form a steamer chromium

501159 五、發明說明(47) 層’並且於步驟2702以沉積形成一蒸鍍|目層,隨後藉由步 驟2703以沉積形成一介電層。 凊參閱第28A-28B圖’第26A-26B圖係表示在完成步驟 20 1 -202後之一基底1的結構圖,該基底1包括有底部電極 4、阻層5、介電層6、閘極金屬層1 8 1 1及頂部電極1 8 1 〇, 並且精由餘刻步驟2301以形成凹部2425。步驟2701-2703 係用以形成該蒸鍍鉻層2 8 3 0、該蒸鍍鉬層2 8 3 1及該介電層 2832。 曰501159 V. Description of the Invention (47) Layer 'and deposit a vapor deposition layer in step 2702, and then form a dielectric layer by depositing in step 2703.凊 Refer to Figures 28A-28B 'Figures 26A-26B are structural diagrams of one of the substrates 1 after completing steps 20 1 -202, the substrate 1 includes a bottom electrode 4, a barrier layer 5, a dielectric layer 6, a gate The electrode metal layer 1 8 1 1 and the top electrode 1 8 1 0 are formed in the remaining step 2301 to form a recess 2425. Steps 2701-2703 are used to form the vapor-deposited chromium layer 2 8 30, the vapor-deposited molybdenum layer 2 8 31, and the dielectric layer 2832. Say

請再參閱第27圖,隨後藉由步驟2704以進行罩幕、# 刻步驟。請參閱第28C-28D圖,步驟2704係藉由蝕刻方式 對於該介電層2832、該蒸鍍鉬層28 31、該蒸鍍鉻層283〇及 部分頂部電極1 8 1 0進行貫穿性的蝕刻作業。 步驟2705係用以再一次對於該介電層6、該阻層5進行 蝕刻作業,如此以形成如同第28E-28F圖中所示之、^構, 並且藉由步驟2706對於該底部電極4之部分位置進行曝光 作業以形成接觸墊2823。 +Please refer to FIG. 27 again, and then perform step 2704 to perform the mask and # etch steps. Please refer to FIGS. 28C-28D. In step 2704, the dielectric layer 2832, the vapor-deposited molybdenum layer 28 31, the vapor-deposited chrome layer 2830, and part of the top electrode 1 8 1 0 are etched by etching. . Step 2705 is used to perform an etching operation on the dielectric layer 6 and the resistive layer 5 again, so as to form a structure as shown in FIGS. 28E-28F, and through step 2706 for the bottom electrode 4 The exposure operation is performed at a part of the position to form a contact pad 2823. +

請仍參閱第27圖,步驟270 6係用以形成一聚焦結構。 請參閱第28G-Η圖,於第28G-H圖中係形成有一聚構 2 824,並且於第28G圖中之該聚焦結構2824上係形成右一 聚焦格子金屬2827。 請再參閱第27圖,步驟2707係用以進行蝕刻作業。往 參閱第28I-28J圖,步驟2707係用以進行該介電層2832明 移除、進行該介電層6之部分移除。 曰 步驟2708係用以對於上述結構進行再一次蝕刻以形成Still referring to FIG. 27, step 270 6 is used to form a focusing structure. Referring to FIG. 28G-Η, a cluster 2 824 is formed in FIG. 28G-H, and a right focus grid metal 2827 is formed on the focusing structure 2824 in FIG. 28G. Referring to FIG. 27 again, step 2707 is used to perform the etching operation. Referring to FIGS. 28I-28J, step 2707 is used to remove the dielectric layer 2832, and to partially remove the dielectric layer 6. Step 2708 is used to etch the above structure again to form

1012-4065-PF ; ALEX.ptd 第53頁1012-4065-PF; ALEX.ptd page 53

501159 五、發明說明(48) 一完整電極結構。第28K-28L圖係表示第28I-28J圖中之結 構在完成步驟2708後之圖示。於本實施例中,步驟2708係 採用蝕刻方式對於該蒸鍍鉬層283 1進行移除作業。 於步驟2704-2708進行期間,該頂部電極1810係藉由 該蒸鍍鉻層2 8 3 0所保護,如此可避免該頂部電極1 § 1 〇於一 般製程步驟中受到破壞,並且可以防止該頂部電極丨8丨〇之 短路及凹陷的產生。此外,由於該頂部電極丨8丨〇受到該蒸 鍍鉻層2830的保護,如此則可避免於熔塊密封區域之中形 成攔短路,並且本實施例在相較於習知技術下係具有較少 的曝光金屬,同時也可以減少欄相對於該聚焦格子金屬的 短路現象。 第2 9 A - 2 9 Η圖係表示根據一實施例中之一多位準電極 於成型期間所沉積形成之一金屬合金層之剖面視圖。本1 轭例中所提出之該多位準電極係可應用做為一頂部電極 一底部電極、一閘極電極、一攔電極、一列電極或是其1 性質之電極的使用。請參閱第29Α圖,首先係將一金屬、人 金層2902沉積於_基底2900之上。於本實施例中,該金^ 合金層2902係由鋁及鈮所構成,並且該金屬合金層29〇2 ^ &gt;儿積厚度約為2500埃。此外,本發明所提出之金屬合金^ 亦可抓用大於或小於本實施例的厚度值,或是藉1 屬來製作。 〃匕4 請參閱第29Β圖,在完成第m圖中所示之 保護層2904沉積於該金屬合金層29〇2上以形成一= 層豐狀物2906。力一實施例中,該保護層29〇4係由銷及鶴501159 V. Description of the invention (48) A complete electrode structure. Figures 28K-28L show the structure in Figures 28I-28J after completing step 2708. In this embodiment, step 2708 is an etching operation to remove the vapor-deposited molybdenum layer 2831. During steps 2704-2708, the top electrode 1810 is protected by the vapor-deposited chrome layer 2 8 3 0. This prevents the top electrode 1 from being damaged during the general process steps and prevents the top electrode from being damaged.丨 8 丨 〇 short circuit and the generation of depressions. In addition, since the top electrode 丨 8 丨 〇 is protected by the vapor-deposited chrome layer 2830, short-circuit blocking can be prevented from forming in the frit sealing area, and the present embodiment has less than the conventional technology. The exposure metal can also reduce the short circuit of the column relative to the focusing grid metal. Figures 2 9 A-2 9 are cross-sectional views of a metal alloy layer formed by a multi-level quasi-electrode deposited during molding according to an embodiment. The multi-level quasi-electrode system proposed in this yoke example can be used as a top electrode, a bottom electrode, a gate electrode, a blocking electrode, a row of electrodes, or an electrode of its nature. Referring to FIG. 29A, first, a metal, human gold layer 2902 is deposited on the substrate 2900. In this embodiment, the gold alloy layer 2902 is composed of aluminum and niobium, and the metal alloy layer 2902 ^ &gt; has a thickness of about 2500 angstroms. In addition, the metal alloy ^ proposed by the present invention can also be made by using a thickness value larger or smaller than this embodiment, or by using a metal. Please refer to FIG. 29B. After the completion of the protective layer 2904 shown in FIG. M, the metal alloy layer 2902 is deposited to form a layer 2906. In one embodiment, the protective layer 2904 is made of pins and cranes.

501159 五、發明說明(49) 所構成,並且該保護層29〇4之沉積厚度約為12〇〇埃。 本發明以較佳實施例揭露如上,然其並非用以限制 …、 明,本發明所提出之保護層亦可採用大於或小於本^ 之厚度值的其它厚度值,或是藉由其它金屬來製作。 請參閱第29C圖,在製程中之污染物29〇8係通 於該多層叠狀物290 6之上,並且在特定的場合中之該芦 $狀物2906上將會文到水模(^1;6]^龍1^3)的污染,這此 染物除了會於後續蝕刻製程中造成不必要的過氧化現象產 生、降低後續餘刻製程的可操控性(c 〇 n t r 〇 1 1 a b i 1 i t y )及 其所形成之該多層疊狀物之結構的完整性之外,並且在蝕 刻程序中將嚴重影響該電極的成型,以及於該多層電極之 結構中將可能會形成’’開路(opening)”或破裂現象的產 生。 請參閱第29D圖,於本實施例中係藉由一清潔程序 (cleaning process)對於該多層疊狀物29〇6進行氧化誘發 污染物(oxidation-inducing contaminants)之清除。於 一實施例中係可將該多層疊狀物2 9 〇 6放置於一化學溶劑中 以進行清潔程序。於一特定實施例中,用以清潔程序用之 化學/谷劑選自Ν Η* 0 Η,H F,T M A Η所組成之族群。由第2 9 D圖 可看出,该結構中於貫質上並不包含有氧化誘發污染物, 如此便不需在後續蝕刻過程中進行一般的過氧化處理。雖 然本發明所提出之化學溶劑係選自NH4〇H、HF及ΤΜΑΗ所組 成之族群,然其並非用以限制本發明,本發明亦可採用其 它的化學溶劑來進行清潔程序。501159 V. Description of the invention (49), and the protective layer 2904 has a deposition thickness of about 12,000 Angstroms. The present invention is disclosed in the preferred embodiment as above, but it is not intended to limit ..., the protective layer proposed by the present invention may also adopt other thickness values greater than or less than this thickness value, or by other metals Production. Please refer to FIG. 29C. In the manufacturing process, the pollutant 2908 is passed on the multi-layered object 2906, and on a specific occasion, the reed 2906 will be written to the water model (^ 1; 6] ^ 龙 1 ^ 3) pollution, in addition to this dye will cause unnecessary peroxidation in the subsequent etching process, reducing the controllability of the subsequent etching process (c 〇ntr 〇1 1 abi 1 ity) and the structural integrity of the multi-layer structure formed by it, and will seriously affect the formation of the electrode in the etching process, and `` opening '' may be formed in the structure of the multi-layer electrode ) ”Or the occurrence of cracking phenomenon. Please refer to FIG. 29D. In this embodiment, a cleaning process is used to perform oxidation-inducing contaminants on the multi-layered article 2906. Clearing. In one embodiment, the multi-layered article 2 906 can be placed in a chemical solvent to perform a cleaning process. In a specific embodiment, the chemical / cereal used for the cleaning process is selected from N Η * 0 Η, HF, TMA Η It can be seen from Fig. 29D that the structure does not contain oxidation-induced pollutants in the mass, so there is no need to perform a general peroxide treatment in the subsequent etching process. Although the present invention proposes The chemical solvent is selected from the group consisting of NH4OH, HF, and TMAA, but it is not intended to limit the present invention, and the present invention may also use other chemical solvents to perform the cleaning process.

(•ptd 第55頁 501159(Ptd p. 55 501159

五、發明說明(50) 請參閱第29E圖,當該多層疊狀物2906在完成上述清 潔程序之後,於該多層疊狀物2 9 0 6之表面上係具有良好毒占 著性及形狀均勻性,因而在藉由沉積將一光成像材料 ^ (photoimagable material)2910(例如:光阻)形成於該多 層疊狀物2 9 0 6之上時,該多層疊狀物2 9 0 6與該光成像材才斗 2 9 1 0之間係可達到相當具有理想的黏著效果,如此在實施 例中係可以完全免除習知技術中因污染物所可能造成的問 題0 請參閱第29F圖,於第29F圖中之該多層疊狀物29〇6上 係僅沉積有部分的該光成像材料29 1 0,其結構係藉由進行 罩幕及光成像材料移除程序(masking and photoimagable material removal process)而得 ° 請參閱第29G圖,第29G圖中所示之該多層疊狀物29〇6 係對於第29F圖中之結構進行蝕刻程序後而得,該多層疊 狀物2j06係位於部分殘留之該光成像材料291〇的下側^如 此可藉由部分殘留之該光成像材料29丨〇對於該多層疊狀物 2906進行保護,亦即,蝕刻作業係對於未設置有部分殘留 之該光成像材料2910之下的該多層疊狀物29〇6進行處理。 ^本實施例中係藉由溼蝕刻方式對於該多層疊狀物29〇6進 行蝕刻作業,更特別的是溼蝕刻所採用的溼蝕劑(wet etch’tj 包括有H3p〇4、HN〇3、CH3C〇〇H&amp;H2。。於本實施例 4溼蝕劑之組成係包括:約7〇—8〇%的H3P〇4、1〇 — 15%的 3 7 12/0的CH3C00H及2-8%的112〇。雖然本實施例中所提 之溼蝕劑係採用包括有1^04、hno3、CH3C00H及1120等來V. Description of the invention (50) Please refer to FIG. 29E. After the multi-layered object 2906 has completed the cleaning process described above, the surface of the multi-layered object 2 9 0 6 has good poison occupation and uniform shape. Therefore, when a photoimagable material 2910 (eg, a photoresist) is formed on the multi-layered object 2 9 0 6 by deposition, the multi-layered object 2 9 0 6 and the The photoimaging material can achieve a quite ideal adhesion effect between 2 9 1 0, so in the embodiment, it can completely eliminate the problems caused by pollutants in the conventional technology. 0 Please refer to FIG. 29F. Only a part of the photo-imaging material 29 1 0 is deposited on the multi-layered object 29 06 in FIG. 29F, and its structure is performed by a masking and photoimagable material removal process. ) Please refer to Figure 29G. The multi-layered object 2906 shown in Figure 29G is obtained by performing an etching process on the structure in Figure 29F. The multi-layered object 2j06 is located in a part of the residue. The lower side of the light imaging material 291〇 The multi-layered object 2906 can be protected by partially remaining the photo-imaging material 29. That is, the etching operation is performed on the multi-layered object 29 under the photo-imaging material 2910 which is not provided with a partial residue. 〇6Processing. ^ In this embodiment, the multi-layered article 29〇6 is etched by wet etching. More specifically, the wet etchant used in wet etching (wet etch'tj includes H3p〇4, HN〇3 CH3COOH &amp; H2 ... The composition of the etchant in this Example 4 includes: about 70-80% of H3P04, 10-15% of 3 7 12/0 CH3C00H and 2- 8% of 112%. Although the wet etchant mentioned in this example uses 1 ^ 04, hno3, CH3C00H, 1120, etc.

501159 五、發明說明(51) ’然其並非用以限制本發明,本發明亦可採 用八匕成伤的溼蝕劑來進行钱刻作業。 才木 =參閱第29G圖,於本實施例中所提出之姓 係匕括有兩部分:首先係以用包括 序501159 V. Description of the invention (51) ′ Although it is not intended to limit the present invention, the present invention can also use a wet etchant that is damaged by eight daggers to carry out money carving operations.才 木 = Refer to Figure 29G, the surname proposed in this embodiment has two parts: first, use the order

及扎0等之溼蝕劑對於兮夕盛ft 4 3 CH3C〇〇H 畔in 多層疊狀物290 6進行氧化處理, 2後便對於該多層疊狀物290 6之上的氧化部分進行蝕 處理、。亡,渥I虫劑中之HN〇3係主要用以對於該多層疊狀 290&gt;6進行氧化處理,而溼蝕劑中之⑶〆⑽η係主要用以 於該多層疊狀物2906之上的氧化部分進行#刻化處理。、 土,::二第29D圖中所示之多層叠狀物上於實質上係不 曰形成有乳化誘發污染物,並且該多層疊狀物29〇6在 包含有HJO4、HN〇3、CH3C00H及等之溼蝕劑進行氧化曰處 理夺忒夕層豎狀物2 9 0 6係可不必進行如同習知技術中之 過,化,理。因此,該多層疊狀物2906便可在良好的監控 下完成氧化及蝕刻程序,並且於該多層電極之結構中將 會形成”開路&quot;或斷路現象的產生。 除了於上述所提出之優點外,於其它實施例中係可藉 由蝕刻形成一完整多層電極用之一理想斜輪廓(sl〇ped &quot; prof lie),其形成方式係藉由對於兩金屬層(亦即,鉬/鎢 層及銘/銳層)之餘刻速率及對於該兩金屬層之個別的韻刻 深度而得。 請參閱第29H圖,第29H圖係表示一完整多層電極2912 之剖面圖。在清潔程序及溼蝕刻的作用下,該完整多層電 極2912除了可以具有相當理想的錐度(tape angle)之外,Wet etchants such as Zirconium and Zan 0 are used to oxidize Xi Xisheng ft 4 3 CH3C00HH in the multi-layered object 2906, and after 2, the oxidized part above the multi-layered object 2906 is subjected to etching treatment. . The HN03 in the Worm I insecticide is mainly used to oxidize the multilayer 290 &gt; 6, and the ⑶〆⑽η in the wet etchant is mainly used on the multilayer 2906. The oxidized part is subjected to #lithography. Soil: Emulsion-induced contaminants are formed on the multilayers shown in Fig. 29D, and the multilayers 29〇6 contain HJO4, HN〇3, and CH3C00H. Oxidation of the etchant and the like can be used to treat the vertical layer 2 9 0 6 series, and it is not necessary to perform the chemical, physical, and chemical treatments as in the conventional technology. Therefore, the multi-layered object 2906 can complete the oxidation and etching procedures under good monitoring, and an "open circuit" or open circuit phenomenon will be formed in the structure of the multilayer electrode. In addition to the advantages mentioned above, In other embodiments, an ideal slant profile (soloped &quot; proflie) for forming a complete multilayer electrode can be formed by etching, and the formation method is performed for two metal layers (ie, molybdenum / tungsten layer). And inscription / sharp layer) are obtained from the remaining engraving rate and the individual engraving depth for the two metal layers. Please refer to Fig. 29H, which is a cross-sectional view of a complete multilayer electrode 2912. During the cleaning process and wet In addition to the effect of etching, the complete multilayer electrode 2912 can have a rather ideal tape angle.

501159 五、發明說明(52) &quot; ---—----- 經由溼触後的輪廓表面係具有相當的平整性及 時於該多層電極之結構中更不會形成” 冋 產生。 紙開路或斷路現象的 請參閱第30圖,第30圖係表示根據一實施 夕 位準電極之成型流程圖。 』T &lt; 夕 步驟3002係表示進行一金屬合金層之沉積作業。 在完成該金屬合金層之沉積作業後,藉由步驟3〇〇4將 一保護層沉積於該金屬合金層以形成一多層疊狀物。 步驟3006係表示藉由一清潔程序對於該多層疊狀物 行污染物之清除。 步驟3008係表示對於該多層疊狀物進行蝕刻以形成一 多層電極。 因此’由本實施例中所提出之多層電極及其成型方法 係並不需要進行過氧化處理,並且於該多層電極之結構中 更不會形成”開路”或斷路現象的產生。 請參閱第31Α-31Ι圖,第31Α-311圖係藉由剖面視圖說 明利用一金屬間化合物(intermetal 1 ic compound)之約化 成型以形成一多層電極之製程步驟,並且藉由一剖面視圖 說明利用一金屬間化合物之約化成型以形成一平板顯示裝 置。本實施例中所提出之該多位準電極係可應用做為一頂 部電極、一底部電極、一閘極電極、一欄電極、一列電極 或是其它性質之電極的使用。請參閱第3丨A圖,首先係將 一第一金屬合金層3102沉積於一基底3100之上。於本實施 例中,該第一金屬合金層3丨〇 2係由鋁及鈮所構成,並且該501159 V. Description of the invention (52) &quot; ---------- The contoured surface surface after wet contact has considerable flatness, and it will not form in the structure of the multilayer electrode. Please refer to FIG. 30 for the phenomenon of disconnection. FIG. 30 is a flowchart showing the formation of a level electrode according to the implementation. “T &lt; Step 3002 represents the deposition of a metal alloy layer. After completing the metal alloy After the layer deposition operation, a protective layer is deposited on the metal alloy layer in step 3004 to form a multi-layered object. Step 3006 indicates that the multi-layered object is contaminated by a cleaning process. Step 3008 indicates that the multilayer is etched to form a multilayer electrode. Therefore, the multilayer electrode and the molding method proposed in this embodiment do not need to be subjected to a peroxidation treatment, and the multilayer electrode In the structure, there will be no "open circuit" or open circuit phenomenon. Please refer to Figure 31A-31I, Figure 31A-311 is a cross-sectional view illustrating the use of an intermetallic compound (intermetal 1 ic compound) to form a multi-layer electrode, and a cross-sectional view is used to illustrate the use of the reduction of an intermetallic compound to form a flat-panel display device. The level electrode system can be used as a top electrode, a bottom electrode, a gate electrode, a column electrode, a column electrode or other types of electrodes. Please refer to Figure 3 丨 A. A metal alloy layer 3102 is deposited on a substrate 3100. In this embodiment, the first metal alloy layer 3 is composed of aluminum and niobium, and the

1012-4065-PF* ALEX.Ptd 第明頁 5011591012-4065-PF * ALEX.Ptd p. 501159

第金屬e金層3102之 &gt;儿積厚度約為25〇〇埃。 明所提出之金屬合金層亦可採用士於七,、 Γ 冬發 译佶十s朴山* —人j 用大於或小於本實施例的厚 度值,或是猎由其它金屬來製作。 于 清參閱第3 1 A圖,本實施例中之該第一金屬合金声 3102的成型係於一真空環境中進行,並且同樣在 ^ 境中係將第二金屬合金層(於此稱為 一工衣 曰此%之為保蠖層)沉積於該第 一金屬合金層3102之上。上述 · · k具工咏丨兄之壓力值係大約維 持在 1-5 inilliTorr。 請參閱第31B圖,在完成第31A圖中所示之結構後,利 用一阻層3103形愈於該第一金屬合金層31〇2之上,藉由該 =層31 03以防止在該第一金屬纟金層31〇2中形成金屬間化 泛^ w於本貝施例中係將該第一金屬合金層3 1 0 2設置於一 3 氧環支兄(oxygen containing environment)中,如此便 可使得自然氧化層形成於該第一金屬合金層31〇2之上。更 特別的是,含氧環境係可利用在該第一金屬合金層31〇2於 沉積過程中進入一真空環境中而形成,並且使得空氣接觸 於該第一金屬合金層31〇2。於一實施例中,用以進行該第 一金屬合金層3 1 0 2之沉積作業的所在疏散環境的壓力值係 ,似於一大氣壓力(一大氣),並且於該環境中係充滿了空 氣’如此便可在空氣中之氧氣與該第一金屬合金層31〇2的 ,應作用下开&gt; 成了 一自然氧化層。於本實施例中,該自然 氧化層的厚度約為1 Q 〇埃。雖然於本實施例中藉由壓力值 係近似於一大氣壓力之空氣環境來進行阻層之形成,然其 並非用以限制本發明,本發明亦可採用其它的含氧氣體所 501159 五、發明說明(54) 形成的環境來進行該阻層之成型 請仍參閱第3 1 B圖,於另一實施例中係可藉由將氧氣 引入該第一金屬合金層3 1 02之沉積環境中以形成該阻層 3103,而於一特定實施例中之該氧氣注入於該第一金屬合 金層3102之沉積環境中的速率約為卜5 sccm (standard cublc cent imeters per minute)。雖然於本實施例中藉 由速率約為卜5 seem之空氣注入於該第一金屬合金層31〇2 之/儿積%境中,然其並非用以限制本發明,本發明亦可採 用其它的含氧氣體及/或其它不同的速率注入於該第一金 屬合金層3102之沉積環境中,如此以進行該阻層之成型' 請仍參閱第31B圖,本發明係於一實施例中將一目椤 材料(target material)指定於一預濺鍍清潔程序(pre^ setter cleaning process)中,如此以進行一第二金屬 i么人於第31B圖中並未圖示)之沉積作業。在完成該第 ,,&amp;金層3102之沉積、該阻層31〇3之成型後所產生的 箱Ιί ϊ的靶材(target)或其它不需要的污染物係可藉由 預濺鑛清潔程序加以去除。 :參閱第3K圖。隨後’將—第二金屬合金層(或稱之 • ^,4層)31 0 4沉積於該第一金屬合金層3丨〇 2之上以形 及二:物3106。&amp; 一實施例中,該保護層31 04係由鉬 m 並且該保護層3104之沉積厚度約為12〇〇埃。 2本:明以較佳實施例揭露如i,然其並非用以限制 X ’發明所提出之保護層亦可採用大於或小於本實A 例之厚度值的其它厚度值,或是藉由其它金屬來製The thickness of the second metal e gold layer 3102 is about 2500 angstroms. The metal alloy layer proposed by the Ming Dynasty can also be made of Shi Yuqi, Dong Dong 佶 s, Pu Shan * — person j uses a thickness value greater than or less than this embodiment, or is made of other metals. Yu Qing refers to FIG. 31A. In this embodiment, the forming of the first metal alloy sound 3102 is performed in a vacuum environment, and the second metal alloy layer (herein referred to as a The work clothes is said to be a protective layer) deposited on the first metal alloy layer 3102. The pressure value of the above k-workers is maintained at about 1-5 inilliTorr. Please refer to FIG. 31B. After completing the structure shown in FIG. 31A, a resistance layer 3103 is used to shape over the first metal alloy layer 3102, and the layer 31 03 is used to prevent the An intermetallic pan is formed in a metallic gold layer 3102. In this embodiment, the first metal alloy layer 3 1 0 2 is disposed in a 3 oxygen containing environment, so Then, a natural oxide layer can be formed on the first metal alloy layer 3102. More specifically, the oxygen-containing environment can be formed by entering the first metal alloy layer 3102 into a vacuum environment during the deposition process, and allowing air to contact the first metal alloy layer 3102. In an embodiment, the pressure value of the evacuation environment where the first metal alloy layer 3 1 0 2 is deposited is similar to an atmospheric pressure (an atmosphere), and the environment is filled with air. 'In this way, the oxygen in the air and the first metal alloy layer 3102 can be opened under the action of> a natural oxide layer. In this embodiment, the thickness of the natural oxide layer is about 1 Q Angstrom. Although in this embodiment, the formation of the barrier layer is performed by an air environment with a pressure value close to an atmospheric pressure, it is not intended to limit the present invention, and the present invention may also use other oxygen-containing gas 501159. V. Invention Explanation (54) The formation of the resistive layer is performed by referring to FIG. 3 1B. In another embodiment, oxygen can be introduced into the deposition environment of the first metal alloy layer 3 1 02 to The resist layer 3103 is formed, and in a specific embodiment, the rate of the oxygen injection into the deposition environment of the first metal alloy layer 3102 is about 5 sccm (standard cublc cent imeters per minute). Although in the present embodiment, air at a rate of about 5 seem is injected into the / 100% area of the first metal alloy layer 3102, it is not intended to limit the present invention, and the present invention can also use other Oxygen-containing gas and / or other different rates are injected into the deposition environment of the first metal alloy layer 3102, so as to perform the formation of the resistive layer 'Please refer to FIG. 31B again. The present invention is an embodiment in which A target material is designated in a pre ^ setter cleaning process, so as to perform a second metal deposition operation (not shown in Fig. 31B). After the completion of this step, the &amp; gold layer 3102 deposition, the resistance layer 3103 formed after the box Ι ϊ target (target) or other unwanted pollutants can be cleaned by pre-spattering The program is removed. : See Figure 3K. Subsequently, a second metal alloy layer (also referred to as “^, 4 layers”) 31 0 4 is deposited on the first metal alloy layer 3 and 2 to form a second object 3106. &amp; In an embodiment, the protective layer 31 04 is made of molybdenum m and the protective layer 3104 has a deposited thickness of about 12,000 Angstroms. 2: This is to use a preferred embodiment to disclose such as i, but it is not intended to limit the protective layer proposed by the X 'invention. Other thickness values greater than or less than the thickness value of this example A may also be used, or by other Made of metal

501159 五、發明說明(55) ^-- 請仍參閱第3 1C圖,該阻層3 1 0 3的功能係用、 該第二金屬合金層3 1 〇4中形成金屬間化合物,以防止,在 阻層3103以防止兩分離金屬層(亦即,第一金’、人P藉由 3102、第二金屬合金層31〇4)之間產生原子及分&quot;&quot;金層玉 以形成新的化合物。相較於習知技術,本實子的擴政 成型過程中將不會產生金屬間化合物,並且可f於電2的 經常使用的氧化及蝕刻速率來進行該多層疊狀2由目鈾所 如此使得本實施例中之該多層疊狀物可在穩 ^成型、, 行後續之氧化及#刻過程,同時藉由上述方式所==二= 多層疊狀物3106係可適用於一平面顯示裝置中」夕=501159 V. Description of the invention (55) ^-Please also refer to FIG. 31C. The function of the resistance layer 3 103 is to form an intermetallic compound in the second metal alloy layer 3 1 04 to prevent, Atoms and components are generated between the barrier layer 3103 to prevent the two separated metal layers (ie, the first gold ', the P through 3202, and the second metal alloy layer 3104) to form a new layer of gold. compound of. Compared with the conventional technology, the Shikoko will not produce intermetallic compounds during the expansion molding process, and the multi-layered 2 can be carried out at the commonly used oxidation and etching rate of electricity 2 In this embodiment, the multi-layered object in this embodiment can be formed in a stable manner, and the subsequent oxidation and # engraving processes are performed. At the same time, the above-mentioned method == two = multi-layered object 3106 is applicable to a flat display device Mid "evening =

請參閱第31D-31I圖,第31D_31I圖係根據—實施例中 所新增之一另一步驟,該另一步驟係根據該多層疊狀物 31 06於進行蝕刻程序以形成該電極結構之前所進行之步 驟。如第31D圖所示,污㈣31〇8於正冑的情況下係會沉 積於該多層疊狀物3106之上’並且在特定的場合中之該多 層疊狀物31 06上將會受到水模的污染,這些污染物除了會 於後續㈣製程中造成不必要的過氧化現象產生、降低後 續蝕刻製程的可操控性及其所形成之該多層疊狀物之結構 的完整性之外,並且在蝕刻程序中將嚴重影響該電極的成 型,以及於該多層電極之結構中將可能會形成”開路&quot;或斷 路現象的產生。 凊參閱第3 1 E圖,於本實施例中係藉由一清潔程序對 於該多層疊狀物3106進行氧化誘發污染物之清除。於一實Please refer to Figs. 31D-31I, which are based on one of the steps added in the embodiment. The other step is based on the multi-layer structure 31 06 before the etching process is performed to form the electrode structure. Steps to proceed. As shown in FIG. 31D, the fouling 308 is deposited on the multi-layer 3106 in the case of being positive, and the multi-layer 31 06 will be subjected to a water mold in a specific occasion. Pollution, these pollutants will cause unnecessary peroxidation in the subsequent sintering process, reduce the controllability of the subsequent etching process and the structural integrity of the multilayer structure formed, and The etching process will seriously affect the formation of the electrode, and the "open circuit" or open circuit phenomenon may be formed in the structure of the multilayer electrode. 凊 Refer to Figure 3 1E, in this embodiment, a The cleaning procedure performs the removal of oxidation-induced pollutants on the multilayer 3106. Yu Yishi

)υιΐ59 五、發明說明(56) ,1 ^係可將該多層疊狀物3 106放置於一化學溶劑中以進 =清潔程序。於一特定實施例中,用以清潔程序用之化學 &gt;谷劑選自ΝΗβΗ,HF,TMAH所組成之族群。由第31E圖可^ 出’ 2結構中於實質上並不包含有氧化誘發污染物,如此 便不需在後續餘刻過程中進行一般的過氧化處理。雖然本 ,明所提出之化學溶劑係選自NH4〇h、HF &amp;TMAH所組成之 族群,然其並非用以限制本發明,本發明亦可採用其它的 化學溶劑來進行清潔程序。) υιΐ59 5. Description of the invention (56), 1 ^ means that the multilayer 3106 can be placed in a chemical solvent to perform a cleaning procedure. In a specific embodiment, the chemistry used for the cleaning procedure is selected from the group consisting of NΗβΗ, HF, and TMAH. It can be seen from Fig. 31E that the '2 structure does not substantially contain oxidation-induced pollutants, so that it is not necessary to perform general peroxidation treatment in the subsequent remaining processes. Although the chemical solvents proposed in the present and the present invention are selected from the group consisting of NH40h, HF &amp; TMAH, it is not intended to limit the present invention, and the present invention may also use other chemical solvents for cleaning procedures.

•請參閱第31F圖,當該多層疊狀物31〇6在完成上述清 f程序之後’於該多層疊狀物3 1〇6之表面上係具有良好黏 著性及形狀均勻性,因而在藉由沉積將一光成像材料 3110(例如:光阻)形成於該多層疊狀物31〇6之上時,該多 層疊狀物3106與該光成像材料311〇之間係可達到相當具有 理想的黏著效果,如此在實施例中係可以完全免除習知技 術中因污染物所可能造成的問題。 乂請參閱第31(^圖,於第31G圖中之該多層疊狀物3106上 係僅沉積有部分的該光成像材料3丨丨〇,其結構係藉由進行 罩幕及光成像材料移除程序而得。• Please refer to FIG. 31F. After the multi-layered article 3106 has completed the above-mentioned cleaning procedure, it has good adhesion and uniform shape on the surface of the multi-layered article 3 106. When a photo-imaging material 3110 (for example, a photoresist) is formed on the multi-layered object 3106 by deposition, the multi-layered object 3106 and the photo-imaging material 3110 can be quite ideal. The adhesion effect, in this embodiment, can completely eliminate the problems caused by pollutants in the conventional technology.乂 Please refer to FIG. 31 (^). In the multilayered object 3106 in FIG. 31G, only a part of the photoimaging material 3 is deposited. The structure is performed by performing a mask and photoimaging material removal. Divided by procedures.

' 請參閱第31H圖,第31H圖中所示之該多層疊狀物3106 係對於第2 9F圖中之結構進行蝕刻程序後而得,該多層疊 狀物3 106係位於部分殘留之該光成像材料311〇的下侧,如 此可藉由部分殘留之該光成像材料311〇對於該多層疊狀物 31 0 6進行保遵’亦即,蝕刻作業係對於未設置有部分殘留 之该光成像材料3 11 0之下的該多層疊狀物3丨〇 6進行處理。'Please refer to FIG. 31H. The multi-layered object 3106 shown in FIG. 31H is obtained by performing an etching process on the structure in FIG. 29F. The multi-layered object 3 106 is located in a part of the remaining light. The lower side of the imaging material 311〇, so that the multi-layered article 3106 can be guaranteed to be partially retained by the optical imaging material 311〇. That is, the etching operation is to image the light that is not provided with a partial residue. The multi-layered product 3101 under the material 3110 is processed.

1012-4065-PF; ALEX.ptd 501159 &gt;1012-4065-PF; ALEX.ptd 501159 &gt;

於本實施例中係藉由溼蝕刻方式對於該多層疊狀物3 1〇6進 行蝕刻作業,更特別的是溼蝕刻所採用的溼蝕劑包括有 h3po4、hno3、CH3C00H及H20。於本實施例中,該溼|虫劑之 組成係包括:約 70-80% 的 Η3Ρ04、10-15% 的 〇03、7-12% 的 C Ha C Ο Ο Η及2 - 8 %的&amp; 0。雖然本實施例中所提出之渔钕劑係 採用包括有HJO4、HN〇3、CH3COOH及1120等來進行蝕刻作 業’然其並非用以限制本發明,本發明亦可採用其它成份 的溼蝕劑來進行蝕刻作業。In this embodiment, the multi-layered article 3 106 is etched by wet etching. More specifically, the wet etchants used in wet etching include h3po4, hno3, CH3C00H, and H20. In this embodiment, the composition of the wet insecticide includes: about 70-80% of Η3Ρ04, 10-15% of 〇03, 7-12% of C Ha C 〇 〇 Η and 2-8% of &amp;; 0. Although the neodymium fishery agent proposed in this embodiment uses HJO4, HN03, CH3COOH, 1120, etc. to perform the etching operation, it is not intended to limit the present invention, and the present invention may also use other components of the etchant To perform an etching operation.

請仍參閱第31 Η圖,於本實施例中所提出之蝕刻程序 係包括有兩部分:首先係以用包括有Η3ρ〇4、0化、CH3⑶〇Η 及40等之溼蝕劑對於該多層疊狀物3 1〇6進行氧化處理,Please refer to FIG. 31 again. The etching procedure proposed in this embodiment includes two parts: firstly, we use a wet etchant including Η3ρ〇4, 0 化, CH3⑶〇Η and 40 etc. The laminate 3 106 is oxidized,

Ik後便對於該多層疊狀物3 1 〇 6之上的氧化部分進行餘刻化 處理。上述溼蝕劑中之.Os係主要用以對於該多層疊狀物 3106進行氧化處理,而溼蝕劑中之CHgCOOH係主要用以對 於該多層疊狀物3 1〇6之上的氧化部分進行蝕刻化處理。由 上述可知’第29D圖中所示之多層疊狀物上於實質上係不 會形成有氧化誘發污染物,並且該多層疊狀物3 1 0 6在藉由 包含有IPO4、HN〇3、CHgCOOH及H20等之溼蝕劑進行氧化處 理,’該多層疊狀物3 1 0 6係可不必進行如同習知技術中之 過=化,理。因此,該多層疊狀物3 106便可在良好的監控 下元成氧化及蝕刻程序,並且於該多層電極之結構中 會形成開路&quot;或斷路現象的產生。 ^與11 了於上述多層疊狀物3 106所具有的優點之外,於其 匕貝&amp;例中係可藉由蝕刻形成一完整多層電極用之一理想After Ik, the oxidized portion on the multilayered product 3 10 6 was subjected to a post-etching treatment. The above Os etchant is mainly used to oxidize the multilayer laminate 3106, and the CHgCOOH in the etchant is mainly used to perform oxidation on the multilayer laminate 3 106 Etching. It can be seen from the foregoing that substantially no oxidation-induced pollutants are formed on the multilayers shown in FIG. 29D, and the multilayers 3 1 0 6 contain IPO4, HN03, The wet etchant such as CHgCOOH and H20 is subjected to oxidation treatment, and the multilayer structure 3 1 0 6 is not required to be subjected to chemical treatment as in the conventional technology. Therefore, the multilayer laminate 3 106 can form an oxidation and etching process under good monitoring, and an open circuit or open circuit phenomenon will be formed in the structure of the multilayer electrode. ^ And 11 In addition to the advantages of the multi-layered product 3 106 described above, in its dagger & example, it is an ideal for forming a complete multilayer electrode by etching.

五、發明說明(58) 斜輪廓,其形成方式係藉由對於兩 及鋁/鈮層)之蝕刻速率及對於該兩 度而得。 請參閱第3 1 I圖,第3 1 I圖係表 之剖面圖。在清潔程序及溼蝕刻的 極31 12除了可以具有相當理想的錐 輪廓表面係具有相當的平整性及均 極之結構中更不會形成&quot;開路”或斷 請參閱第32圖,第32圖係表示 約化金屬間化合物成型之一多位準 如上述之說明可知,步驟 合金層之沉積作業。 在完成該第一金屬合金層之沉 第二金屬合金層之沉積作業之前, 沉積於該第一金屬合金層之上。 在完成該阻層之沉積作業之後 二金屬合金層(可稱之為保護層)沉 ::層疊狀物,藉由該阻層係可防 .金層之間形成金屬間化合物。 ::320:係表示藉由 仃巧染物之清除。 1 金屬層(亦即,鉬/鎢層 金屬層之個別的蝕刻深 示一完整多層電極3112 作用下,該完整多層電 度之外,經由渔飿後的 勻性,同時於該多層電 路現象的產生。 根據一實施例中之具有 電極的成型流程圖。 係表示進行一第一金屬 積作業之後、在完成一 藉由步驟3203將一阻層 ,藉由步驟3204將一第 積於該阻層之上以形成 止於該第一、二金屬合 序對於該多層疊狀物進 狀物進行蝕刻以形成一 層電極及其成型方法中 多層係表示對於該多層叠 因此’藉由本發明所提出之多5. Description of the invention (58) The oblique contour is formed by the etching rate for the two layers and the aluminum / niobium layer and the two degrees. Please refer to Figure 3 I, which is a sectional view of the table. In the cleaning process and wet-etched poles 31 and 12, in addition to having a fairly ideal conical profile, the surface has a fairly flat and uniform structure, and will not form an "open circuit" or break. Please refer to Figure 32, Figure 32 It indicates that one of the levels of reducing the formation of the intermetallic compound is as described above. It can be known that the step of depositing the alloy layer is completed. Before completing the deposition of the first metal alloy layer and the second metal alloy layer, it is deposited on the first metal alloy layer. A metal alloy layer. After the deposition of the resistance layer is completed, the two metal alloy layer (which can be referred to as a protective layer) is deposited: a layered material, and the metal layer is formed between the gold layers. Intermetallic compound :: 320: It means the removal by the clever dyes. 1 The individual etching of the metal layer (that is, the molybdenum / tungsten metal layer) shows that a complete multi-layer electrode 3112 is responsible for In addition, the uniformity after fishing is generated at the same time as the occurrence of the multilayer circuit phenomenon. According to an embodiment, the molding flow chart with electrodes is shown after performing a first metal product operation, after completing a In step 3203, a resist layer is formed on the resist layer in step 3204 to form the first and second metal sequences. The multilayer laminate is etched to form a layer of electrodes and The multilayer method in the molding method means that for the multi-layer, therefore,

之多層電極#成型過程係不 雖然本發明已以較佳費二 屬間化合物的生成。 :制本㈣,任何熟習此露如上,然其並;用以 :和範圍内,當可做更動鱼:者’在不脫離本發明之精 备事後附之申請專利範圍所界定者::本發明之保護範圍The multi-layer electrode # molding process is not a matter of course, although the present invention has preferred the production of intermetallic compounds. : Make a copy of the book, any familiar with this disclosure as above, and the same; used: within the scope, as a change fish: those who are not limited by the scope of the patent application attached without departing from the essence of the present invention :: this The scope of protection of the invention

Claims (1)

501159 六、申請專利範圍 1· 一種用以形成一平面顯示裝置用之一多層電極的方 法,該方法包括以下步驟: , a) 沉積一金屬合金層; b) 沉積一保護層於該金屬合金層之上以形成一多層 疊狀物; c) 指定該多層疊狀物經由一清潔程序移除污染物; 以及 d) 蝕刻該多層疊狀物以形成該平面顯示裝置用之該 多層電極。 2. 如申請專利範圍第1項所述之用以形成一平面顯示 裝置用之一多層電極的方法,其中,該步驟a) 包括沉積 一銘歛金屬合金層。 3. 如申請專利範圍第1項所述之用以形成一平面顯示 裝置用之一多層電極的方法,其中,該步驟a) 包括沉積 該金屬合金層之厚度約為2500埃。 4. 如申請專利範圍第1項所述之用以形成一平面顯示 裝置用之一多層電極的方法,其中,該步驟b) 包括沉積 包括有鉬及嫣之一保護層。 5. 如申請專利範圍第1項所述之用以形成一平面顯示 裝置用之一多層電極的方法,其中,該步驟b) 包括沉積 該金屬合金層之厚度約為1200埃。 6. 如申請專利範圍第1項所述之用以形成一平面顯示 裝置用之一多層電極的方法,其中,該步驟c) 包括指定 該多層疊狀物至一化學溶劑。501159 VI. Application Patent Scope 1. A method for forming a multilayer electrode for a flat display device, the method includes the following steps: a) depositing a metal alloy layer; b) depositing a protective layer on the metal alloy Over the layers to form a multilayer; c) designating the multilayer to remove contaminants through a cleaning process; and d) etching the multilayer to form the multilayer electrode for the flat display device. 2. The method for forming a multi-layer electrode for a flat display device as described in item 1 of the patent application scope, wherein step a) includes depositing a metal alloy layer. 3. The method for forming a multi-layer electrode for a flat display device as described in item 1 of the scope of patent application, wherein the step a) includes depositing the metal alloy layer to a thickness of about 2500 angstroms. 4. The method for forming a multi-layer electrode for a flat display device as described in item 1 of the scope of patent application, wherein step b) includes depositing a protective layer including one of molybdenum and cyan. 5. The method for forming a multi-layer electrode for a flat display device as described in item 1 of the patent application scope, wherein step b) includes depositing the metal alloy layer to a thickness of about 1200 angstroms. 6. The method for forming a multi-layer electrode for a flat display device as described in item 1 of the scope of patent application, wherein step c) includes designating the multi-layered object to a chemical solvent. 1012-4065-PF ; ALEX.ptd 第66頁 5011591012-4065-PF; ALEX.ptd page 66 501159 六、申請專利範圍 7 ·如申請#利範圍第β項所述之用以形成一平面顯禾 裝置用之一多層電極的方法,其中,該化學溶劑係包括 ΝΗ40Η 、 HF 及ΤΜΑΗ 。 ^ 8 ·如申請專利範圍第1項所述之用以形成一平面顧示 裝置用— 之一多層電極的方法,其中,該步驟d)包括渔餘 刻該多層疊狀物以形成該平面顯示裝置用之該多層電極。 9 ·如申請專利範圍第7項所述之用以形成一平面顯示 裝置用之一多層電極的方法,其中,該步驟d)包括以渥 蝕劑溼蝕刻該多層疊狀物以形成該平面顯示裝置用之該多6. Scope of patent application 7 · The method for forming a multi-layer electrode for a planar display device as described in the application #profit range item β, wherein the chemical solvent includes ΝΗ40Η, HF, and TIMAΗ. ^ 8 The method for forming a flat electrode for a flat display device as described in item 1 of the scope of patent application, wherein step d) includes engraving the multi-layered object to form the flat surface The multilayer electrode is used in a display device. 9. The method for forming a multi-layer electrode for a flat display device as described in item 7 of the scope of patent application, wherein the step d) includes wet etching the multilayer stack with an etchant to form the flat surface The display device should be used 層電極,該溼蝕劑包括H3P04、HN03、CH3C00H及H20。 1 0 · —種於形成一平面顯示裝置用之一多層電極期間 以對於一多層疊狀物進行清潔及蝕刻的方法,該方法包括 -以下步驟: a)指定該多層疊狀物經由一清潔程序移除氧化誘發 污染物,如此以減少經由該氧化誘發污染物所形成之非x必 要之過度氧化;以及 # ' b)蝕刻該多層疊狀物及進行該步驟a)之該清潔程 以形成該平面顯示裝置用之該多層電極。 H ^Layer electrode, the etchant includes H3P04, HN03, CH3C00H and H20. 1 0 · A method for cleaning and etching a multi-layer object during forming a multi-layer electrode for a flat display device, the method includes the following steps: a) designating the multi-layer object through a cleaning process The procedure removes the oxidation-induced pollutants so as to reduce unnecessary excessive oxidation formed by the oxidation-induced pollutants; and # 'b) etching the multilayer and performing the cleaning process of step a) to form The flat display device uses the multilayer electrode. H ^ F Vf//J ^ ® ^ ^ ^ ® j置用之-多層電極期間以對於—多層#狀物進 蝕刻的方法,其中,該多層疊狀物包括— 保護層。 至屬合金層及. 12·如申請專利範圍第 _ 裝置用之 丄1 ,只厂/| 夕層電極期間以對於-义層叠狀物進行清潔^F Vf // J ^ ® ^ ^ ^ ® j is a method for performing etching on a multilayer electrode during a multilayer electrode, wherein the multilayer layer includes a protective layer. It belongs to the alloy layer and. 12 · If the patent application scope is _1 for the device, only the factory / | during the layer electrode cleaning to the-sense stack ^ 501159 六、申請專利範圍 餘刻的方法,其中,該金屬合金層包括銘、鈦。 1 3 ·如申請專利範圍第丨丨項所述之於形成一平面顯示 裝置用之一多層電極期間以對於〆多層疊狀物進行清潔及 蝕刻的方法,其中,該金屬合金層之沉積厚度約為250 0 , 埃。 1 4 ·如申睛專利範圍第11項所述之於形成一平面顯示 裝置用之一多層電極期間以對於〆多層疊狀物進行、清潔及 触刻的方法,其中,該保護層包括鉬、鎢。501159 6. Scope of Patent Application The remaining method, wherein the metal alloy layer includes metal and titanium. 1 3 · The method for cleaning and etching a multi-layer stack during the formation of a multilayer electrode for a flat display device as described in item 丨 丨 of the patent application scope, wherein the metal alloy layer has a deposited thickness About 250 0 Angstroms. 1 4 · A method for performing, cleaning, and engraving a plurality of stacked layers during the formation of a multilayer electrode for a flat display device as described in item 11 of the Shenjing patent scope, wherein the protective layer includes molybdenum , Tungsten. 1 5 ·如申請專利範圍第1 1項所述之於形成一平面顯示 裝置用之一多層電極期間以對於/多層疊狀物進行清潔及 餘刻的方法,其中,該保護層之沉積厚度約為2 5 0 0埃。 1 6 ·如申請專利範圍第11項所述之於形成一平面顯示 裝置用之一多層電極期間以對於〆多層疊狀物進行清潔及 飯刻的方法,其中,該步驟a)包括指定該多層疊狀物至 一化學溶劑。 1 7 ·如申請專利範圍第1 6項所述之於形成一平面顯示 裝置用之一多層電極期間以對於一多層疊狀物進行清潔及 蝕刻的方法,其中,該化學溶劑係包括有NH40H、HF及1 5 · The method for cleaning and multi-layering a multilayer electrode during the formation of a multilayer electrode for a flat display device as described in item 11 of the scope of patent application, wherein the thickness of the protective layer is deposited Approximately 2 500 Angstroms. 16 · The method for cleaning and engraving multiple stacked layers during the formation of a multi-layer electrode for a flat display device as described in item 11 of the scope of patent application, wherein step a) includes specifying the Multiple layers to a chemical solvent. 17 · The method for cleaning and etching a multi-layered object during the formation of a multilayer electrode for a flat display device as described in item 16 of the scope of patent application, wherein the chemical solvent includes NH40H , HF and 18. 如申請專利範圍第n項所述之於形成一平面顯开 ^ ^夕層電極期間以對於一多層疊狀物進行清潔 餘刻的方法,其中,兮丰瞒^ k^ B ” 甲5亥步驟b)包括溼蝕刻該多層疊狀 以形成s亥平面顯示裴置用之該多層電極。 19. 如申請專利範圍第11項所述之於形成一平面顯开18. A method for cleaning a multi-layered laminate during the formation of a planar display electrode as described in item n of the scope of application patent n ^^^, where Xifeng conceals ^ k ^ B ”A5 The step b) includes wet-etching the multi-layered shape to form the multi-layer electrode used in the s-plane display display device. 19. The method for forming a planar display device as described in item 11 of the scope of patent application. 501159 六、申請專利範圍 一 裝置用之一多層電極期間以對於一多層疊狀物進行清潔及 餘刻的方法,其中,該步驟b)包括以溼蝕劑渔蝕刻該多 層疊狀物以形成該平面顯示裝置用之該多層電極,該溼餘 劑包括H3P04、HN03、CH3C00H 及H20。 20· —種用於一平面顯示裝置之一多層電極,包括: 一金屬合金層; 一保護層,設置於該金屬合金層之上以形成一多層疊 狀物,該多層疊狀物經蝕刻而形成該多層電極。 2 1 ·如申請專利範圍第2 0項所述之用於一平面顯示裝 置之一多層電極,其中,該金屬合金層包括鋁、鈥。 22·如申請專利範圍第20項所述之用於一平面顯示裝 置之一多層電極,其中,該金屬合金層之沉積厚度約為 2500 埃。 2 3 ·如申請專利範圍第2 〇項所述之用於一平面顯示裝 置之一多層電極,其中,該保護層包括翻、鐫。 2 4 ·如申請專利範圍第2 〇項所述之用於一平面顯示裝 置之一多層電極,其中,該保護廣之’儿積厚度約為1 2 0 0 埃。 25· —種藉由一金屬間化合物之約化成型以形成一多 層疊狀物之方法,該方法包括以下步驟: a) 沉積一第^金屬合金層於/基底; 少 b) 形成一阻層於該第一金屬合金層之上,該阻層係 用以防止該第一金屬合金層内之〆金屬間化合物的形成; 以及501159 6. The scope of patent application: A method for cleaning and leaving a multi-layer laminate during a multilayer electrode for a device, wherein step b) includes etching the multi-layer laminate with a wet etchant to form The multi-layer electrode used in the flat display device, and the residual moisture agent includes H3P04, HN03, CH3C00H and H20. 20 · —A multilayer electrode for a flat display device, comprising: a metal alloy layer; a protective layer disposed on the metal alloy layer to form a multi-layered object, the multi-layered object being etched This multilayer electrode is formed. 2 1 · A multilayer electrode for a flat display device as described in item 20 of the scope of patent application, wherein the metal alloy layer includes aluminum, 22. The multi-layer electrode for a flat display device according to item 20 of the scope of the patent application, wherein the metal alloy layer is deposited to a thickness of about 2500 angstroms. 2 3 · The multi-layer electrode for a flat display device as described in item 20 of the scope of patent application, wherein the protective layer includes a flip-flop. 24. The multi-layer electrode for a flat display device as described in item 20 of the scope of patent application, wherein the thickness of the protective layer is approximately 12 Angstroms. 25 · —A method for forming a multi-layer object by reduction molding of an intermetallic compound, the method includes the following steps: a) depositing a third metal alloy layer on / substrate; less b) forming a resistance layer On the first metal alloy layer, the resistance layer is used to prevent the formation of a hafnium intermetallic compound in the first metal alloy layer; and 501159 六、申請專利範圍 、 C)沉積一第二金屬合金層於该阻層,該阻層係用以 防止該第二金屬合金層内之該金屬間化合物的形成。 2 6·如申請專利範圍第‘2 5項戶斤述之藉由一金屬間化合 物之約化成型以形成一多層疊狀物之方法’其中,該步驟 a)包括於沉積一第一金屬合金廣於該基底’該第一金屬‘ 合金層包括鋁、鈥。 •27·如申請專利範圍第25項所述之藉由一金屬間化合 物之約化成型以形成一多層疊狀物之方法,'其中,該步驟 a )包括沉積該第一金屬合金層之厚度約為2500埃。 2 8 ·如申請專利範圍第2 5項所述之藉由一金屬間化合 物之約化成型以形成一多層疊狀物之方法,其中,該步驟 b )包括將4第^ 金屬合金層指定於一含乳壤境中以形成 該阻層,使得於該第一金屬合金層上形成一自然氧化層。 29·如申請專利範圍第28項所述之藉由一金屬間化9合 物之約化成型以形成一多層疊狀物之方法,其中,該含&quot;氧 環境係利釋在該第一金屬合金層於沉積過程中進入一真处 而形成,並且使得空氣接觸於該第一金屬合金層。’ ' 30·如申請專利範圍第28項所述之藉由一金屬間化合 •物之約化成型以形成一多層疊狀物之方法,其中,該人 環境係藉由將氧氣導入該第一金屬合金層於沉積二, 一環境而形成。 、狂Τ之 31,如申請專利範圍第25項所述之藉由一金屬間 物之約化成型以形成一多層疊狀物之方法,更杠匕5 驟: ? 人匕秸有一步 501159 六、申請專利範圍 於該步驟b )之後、該步驟c)之前係將於該第二金屬 合金層之沉積過程中所利用之一目標材料指定於一預濺鍵 清潔程序。 3 2.如申請專利範圍第2 5項所述之藉由一金屬間化合 物之約化成型以形成一多層疊狀物之方法,其中,該步驟 c)包括沉積一第二金屬合金層於該阻層,該第二金屬合金 層包括鉬、鎢。 3 3.如申請專利範圍第2 5項所述之藉由一金屬間化合 物之約化成型以形成一多層疊狀物之方法,其中,該步驟 c)包括沉積該第二金屬合金層之厚度約為1200埃。 34. —種用以形成一平面顯示裝置用之一多層電極之 方法,該方法係於該多層電極之製程中減少一金屬間化合 物之生成,該方法包括以下步驟: a) 沉積一第一金屬合金層於一基底; b) 形成一阻層於該第一金屬合金層之上,該阻層係 用以防止該第一金屬合金層内之一金屬間化合物的形成; c) 沉積一第二金屬合金層於該阻層,該阻層係用以 防止該第二金屬合金層内之該金屬間化合物的形成; d) 指定該多層疊狀物經由一清潔程序移除污染物; 以及 e) 蝕刻該多層疊狀物以形成該平面顯示裝置用之該 多層電極。 3 5.如申請專利範圍第3 4項所述之用以形成一平面顯 示裝置用之一多層電極之方法,其中,該步驟a)包括沉501159 6. Scope of patent application, C) A second metal alloy layer is deposited on the resistance layer, and the resistance layer is used to prevent the formation of the intermetallic compound in the second metal alloy layer. 26. The method described in item 25 of the patent application for forming a multi-layered product by reduction molding of an intermetallic compound, wherein step a) includes depositing a first metal alloy Wider than the substrate 'the first metal' alloy layer includes aluminum. • 27. A method for forming a multi-layered product by reduction molding of an intermetallic compound as described in item 25 of the scope of patent application, 'wherein the step a) includes depositing the thickness of the first metal alloy layer About 2500 Angstroms. 2 8 · A method for forming a multi-layered product by reduction molding of an intermetallic compound as described in item 25 of the scope of the patent application, wherein step b) includes assigning the 4th metal alloy layer to A barrier layer containing milky soil is used to form the resistance layer, so that a natural oxide layer is formed on the first metal alloy layer. 29. The method for forming a multi-layered product by reduction molding of an intermetallic compound 9 as described in item 28 of the scope of the patent application, wherein the &quot; oxygen-containing environment is explained in detail The metal alloy layer is formed into a real place during the deposition process, and air is brought into contact with the first metal alloy layer. '' 30. The method for forming a multi-layered object by reduction molding of an intermetallic compound as described in item 28 of the scope of the patent application, wherein the human environment is by introducing oxygen into the first The metal alloy layer is formed in a deposition environment. 3. Mad T31, as described in item 25 of the scope of the patent application, the method of forming a multi-layered object by reduction molding of an intermetallic object is more complicated. 5 steps:? Human stalk has a step 501159 six The patent application scope is after the step b) and before the step c), a target material used in the deposition process of the second metal alloy layer is designated in a pre-sputter key cleaning process. 3 2. The method for forming a multi-layer object by reduction molding of an intermetallic compound as described in item 25 of the scope of patent application, wherein step c) includes depositing a second metal alloy layer on the Barrier layer, the second metal alloy layer includes molybdenum and tungsten. 3 3. The method for forming a multi-layered product by reduction molding of an intermetallic compound as described in item 25 of the scope of patent application, wherein step c) includes depositing a thickness of the second metal alloy layer About 1200 Angstroms. 34. A method for forming a multi-layer electrode for a flat display device, the method is to reduce the generation of an intermetallic compound in the process of the multi-layer electrode, the method includes the following steps: a) depositing a first A metal alloy layer on a substrate; b) forming a resistance layer on the first metal alloy layer, the resistance layer is used to prevent the formation of an intermetallic compound in the first metal alloy layer; c) depositing a first A two-metal alloy layer on the barrier layer, the barrier layer being used to prevent the formation of the intermetallic compound in the second metal alloy layer; d) designating the multilayer stack to remove contaminants through a cleaning process; and e ) Etching the multilayer to form the multilayer electrode for the flat display device. 3 5. The method for forming a multi-layer electrode for a flat display device as described in item 34 of the scope of patent application, wherein step a) includes sinking 1012-4065-PF ; ALEX.ptd 第71頁 -------- 申睛專利範圍 ----— 鉬 —第二金屬合金層於該基底,該 金屬么 、鎢。 1屬合金層包括 36·如申請專利範圍 :裝置用之-多層電極之方法,*中Λ/二成·;:面顯 積該第-金屬合金層之厚度約為25 0 0埃:^驟a)包括沉 37.如申請專利範圍第34項所述之甩以形成一 ί亥t f用之一多層電極之方法&quot;其中,該步驟b)包括沪 ;二:==定於一含氧環境中以形成該阻層,信 、名第一金屬合金層上形成一自然氧化層。 厂壯3 8 ·如申請專利範圍第3 7項所述之用以形成一平面顯 Γ裳置用之一多層電極之方法,其中,該步驟a)包括含 =環境係利用在該第一金屬合金層於沉積過程中進入一真 二而形成,並且使得空氣接觸於該第一金屬合金層。 3 9 ·如申凊專利範圍第3 γ項所述之用以形成一平面顯 示放置用之一多層電極之方法,,其中’該含氧環境係藉由 將氧氣導入該第一金屬合金層於沉積過程中之一環境而形 成0 4 0 ·如申請專利範圍第3 4項所述之用以形成一平面顯 •示裝置用之一多層電極之方法,更包括有一步驟: 於該步驟b)之後、該步驟c)之前係將於該第二金屬 合金層之沉積過程中所利用之z目梯材料指定於一預濺鍍 请潔程序。 41.如申請專利範圍第34項所述之用以形成一平面顯 示裝置用之一多層電極之方法,其中,該步螺c)包括該1012-4065-PF; ALEX.ptd page 71 -------- Shen Jing's patent scope -----Molybdenum-the second metal alloy layer on the substrate, the metal, tungsten. The first metal alloy layer includes 36. If the scope of the patent application: the method for the device-a multilayer electrode, the middle Λ / 20% · ;: the thickness of the first-metal alloy layer is about 25 0 0 Angstrom: ^ step a) Including Shen 37. The method described in item 34 of the scope of patent application to form a multi-layer electrode for a TFT, wherein the step b) includes Shanghai; To form the resistance layer in an oxygen environment, a natural oxide layer is formed on the first metal alloy layer. Factory Strong 3 8 · The method for forming a multi-layer electrode for planar display as described in item 37 of the scope of patent application, wherein step a) includes The metal alloy layer enters one and two during the deposition process, and makes air contact the first metal alloy layer. 3 9 · The method for forming a multi-layer electrode for flat display placement as described in item 3 γ of the patent scope, wherein 'the oxygen-containing environment is by introducing oxygen into the first metal alloy layer 0 4 0 is formed in an environment during the deposition process. The method for forming a multi-layer electrode for a flat display device as described in item 34 of the scope of patent application, further comprising a step: b) After that, before step c), the z-mesh ladder material used in the deposition process of the second metal alloy layer is designated in a pre-sputter cleaning process. 41. The method for forming a multilayer electrode for a flat display device as described in item 34 of the scope of patent application, wherein the step c) includes the 501159 六 &gt; 申請專利範圍 ' 步驟C )包括沉積一第二金屬合金層於該阻層,該第二金 屬合金層包括鉬、鎢。 42.如申請專利範圍第34項所述之用以形成一平面顯 示裝置用之一多層電極之方法,其中,該步驟c)包括沉 積該第二金屬合金層之厚度約為1200埃。 4 3.如申請專利範圍第3 4項所述之用以形成一平面顯 示裝置用之一多層電極之方法,·其中,該步驟d)包括在 一光阻層之沉積形成之前係將該多層疊狀物指定於一化’學 溶劑。 44.如申請專利範圍第43項所述之用以形成一平面顯 示裝置用之一多層電極之方法,其中,該化學溶劑係包括 有NH40H 、 HF 及TMAH 〇 4、5.如申請專利範圍第34項所述之用以形成一平面顯 示裝置用之一多層電極之方法,其中,該步驟d) 包括溼 蝕刻該多層疊狀物以形成該平面顯示裝置用之該多層電 極0 4 6.如申請專利範圍第34項所述之用以形成一平面顯 示裝置用之一多層電辑之方法,其中,該步驟d) 包括以 溼蝕劑溼蝕刻該多層疊狀物以形成該平面顯示裝置用之該 多層電極,該溼蝕劑包括H3P04、HN03、CH3COOH及H20。 47. —種用於一平面顯示裝置之一多層電極,包括: 一金屬合金層; 一阻層,形成於該金屬合金層之上;以及 一保護層-,設置於該金屬合金層之上以形成一多層疊501159 VI &gt; Scope of patent application 'Step C) includes depositing a second metal alloy layer on the resist layer, and the second metal alloy layer includes molybdenum and tungsten. 42. The method for forming a multi-layer electrode for a flat display device as described in claim 34, wherein step c) includes depositing a thickness of the second metal alloy layer of about 1200 angstroms. 4 3. The method for forming a multi-layer electrode for a flat display device as described in item 34 of the scope of patent application, wherein the step d) includes depositing a photoresist layer before forming Multilayers are specified in a chemical solvent. 44. The method for forming a multi-layer electrode for a flat display device as described in item 43 of the scope of patent application, wherein the chemical solvent includes NH40H, HF and TMAH 04, 5. If the scope of patent application is The method for forming a multi-layer electrode for a flat display device according to item 34, wherein the step d) includes wet etching the multi-layered object to form the multi-layer electrode for the flat display device 0 4 6 The method for forming a multilayer electromechanical for a flat display device as described in claim 34, wherein the step d) comprises wet etching the multilayer stack with a wet etchant to form the flat surface. The multi-layer electrode for a display device, and the wet etchant includes H3P04, HN03, CH3COOH and H20. 47. A multilayer electrode for a flat display device, comprising: a metal alloy layer; a barrier layer formed on the metal alloy layer; and a protective layer-disposed on the metal alloy layer To form a multiple stack 1012-4065-PF ; ALEX.ptd 第73頁 )υιΐ59 六、申請專利範闺 狀物’該多層疊狀物經蝕刻而形成該多層電極。 4 8 ·如申請專利範圍第4 7項所述之用於一平面顯千壯 置之-多層電極,其中,該金屬合金層包括紹、鈥貞。'袭 4一9、如申請專利範圍第47項所述之用於“平面顯示裝 之夕層電極,其中,該金屬合金層之、沉積厚度約A 5 0 ·如申請專利範圍第4 7項所述之用於一平面顯示裝 置之多層電極,其申,該阻層包括有該金屬合金層二 自然氧化層。 5 1 ·如申請專利範圍第47項所述之用於一平面顯示裝 置之一多層電極,其中,該阻層之沉積厚度約為1 〇 〇埃。 52·如申請專利範圍第47項所述之用於一平面顯示裝 置之一多層電極,其中,該保護層包括鉬、鎢。 53·如申請專利範圍第47項所述之用於一平面顯示裝 置之一多層電極,其中,該保護層之沉積厚度約為丨2 〇 〇 埃0 54·如申請專利範圍第47項所述之用於一平面顯示裝 置之一多層電極,其中,該多層疊狀物係藉由溼餘劑以蝕 刻成一既定斜輪廓,該溼蝕劑之組成係包括約7 〇 — 8 0 %的 H3P04 、 10-15% 的HN03 、 7-12% 的CH3C00H 及2-8% 的H20 。1012-4065-PF; ALEX.ptd p. 73) υιΐ59 6. Application for patent application: The multi-layered object is etched to form the multilayer electrode. 48. The multi-layer electrode for a planar display device as described in item 47 of the scope of the patent application, wherein the metal alloy layer includes a silicon substrate. 'To 4-9, as described in item 47 of the scope of patent application for the "layer display electrode," said metal alloy layer, the thickness of the deposition is about A 5 0 The multi-layer electrode for a flat display device as described, wherein the resistance layer includes the metal alloy layer and two natural oxide layers. 5 1 · The flat electrode for a flat display device as described in item 47 of the scope of patent application. A multi-layer electrode, wherein the thickness of the resist layer is about 100 angstroms. 52. The multi-layer electrode for a flat display device described in item 47 of the scope of patent application, wherein the protective layer includes Molybdenum and tungsten 53. The multilayer electrode for a flat display device as described in item 47 of the scope of patent application, wherein the protective layer has a deposition thickness of about 2,000 angstroms 0 54. The multilayer electrode for a flat display device according to item 47, wherein the multi-layered object is etched into a predetermined oblique contour by a wet residual agent, and the composition of the wet etchant includes about 70% 80% H3P04, 10-15% HN03, 7-12% CH3C00H and 2-8% of H20. 1012-4065-PF I ALB(.ptd 第74頁1012-4065-PF I ALB (.ptd p. 74
TW090113225A 2000-05-31 2001-05-31 Multilayer electrode structure and method for forming multilayer electrode structure for a flat panel display device TW501159B (en)

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