TW498531B - A wafer level packaging process for making flip chips - Google Patents

Abstract

A wafer level packaging process for making flip chips comprises in turn: providing a wafer, filling the protective material, lumping the wafer, removing the protective material, probing the wafer, laser repairing, dicing the wafer. The laser repairing procedure is after bumping and testing. While bumping and testing, the protective material such as photoresist is filled into the depression portion above the fuse for temporary protection of the fuse in the wafer level packaging process.

Description

498531

[Field of the Invention] The present invention relates to a flip-chip wafer-level packaging process, and particularly relates to a flip-chip wafer-level packaging process that temporarily protects a fuse. [Previous technology] Generally, the more complex the integrated circuit system has the fuse structure [fuse s ^ ti ^ uetuire], especially the high-capacity memory chip or the complex system single chip [Systein 〇n chip], the fuse is used Whether the structure is broken or not? Change the circuit path of the integrated circuit and the redundant circuit & 'After testing, find out some defective integrated circuits, and burn the t-wire structure with laser irradiation. The spare circuit replaces some of the defective integrated circuits, which is called "laser repair". In US Patent No. 5, 326, 709 "Wafer Test Flow for Semiconductor Devices with Standby Circuits" describes a test flow of a semiconductor device 'wherein the semiconductor device has a backup circuit and the steps are on a wafer Partially etch the phosphosilicate glass (PSG) and nitride film to open the solder joint, and then perform the pre-laser test "," laser repair "," test of the repaired wafer ", and" off-line marking "in sequence. Laser repair is usually performed after the bare chip is unpackaged, and then dicing is performed to package individual wafers. However, at present, f 1 ip-chip wafers In the wafer level packaging process, if the laser repair can be performed after the packaging, bumping and burn-in, the yield can be greatly improved. [Including the process of remedial packaging and burn-in Defective product], but because the protective layer above the fuse (fuse) is usually thinned and recessed [refer to the United States

V. Description of the Invention (2) Lee No. 6,121, 〇73], Eli Lei, Zhao Zhao, Shi Lishi and Pre-burning 卷 $ 卷 士 "】 Laser ... The shooting part is easy to make long bumps This == Through melting silk pollution and oxidation ... Due to the final ΐ: ίί: ϊ and pre-burning process, it is effective to protect the melting silk, and then it is urgently needed to be solved by laser irradiation for repair. In the US patent No. 5, 72q Π41 Spicy * "; harmianz a kind of alkane silk f Γ7 π β J 41 #U applied to the + conductive body circuit ^ protection film against crickets" describes a kind of smelting shishijiji A field oxide layer 12 [fieid 〇x ^ e] of insulating SiO2 is formed on the substrate Η to carry a fuse 13 such as tungsten or polycrystalline silicon, and a multi-layer insulation is formed on the silicon substrate 丨 and the emulsified layer 12 Layers, such as a silicon dioxide layer η, spin-on-glass 15 [Spin on giass], and a silicon dioxide layer 16, which form a recessed opening 1 at a position corresponding to the dazzling wire 13 7. Thin the insulating layer over the fuse 13 and form a protective layer 18 (pr〇tective Uyer) on the exposed surface of the silicon dioxide layer 6 and the opening 17 It has a laser light transmittance of more than 50%. Without affecting the laser repair, the wire 13 is properly protected to prevent pollution or metal oxidation. However, this south light-transmissive protective layer 1 8 After fabrication, it is permanently present on the integrated circuit J 〇 'The thickness, material and process conditions of the protective layer 18 must be precisely controlled' It was introduced into Shixi by Plasma Enhance Chemical Vapor Deposition (PECVD). Burning [silane] and ammonia [ammonia], the material of the protective layer 18 must be in a ratio of 1.2 to 1.6, and its thickness must be 3000 to 1 5000 angstrom In addition, for the fuse structure located under the deep recessed groove, it is necessary to form a uniform deposition on the surface of the deep recessed groove.

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Thick protective layers are quite difficult. [Objective and Summary of the Invention]

The main purpose of the present invention is to provide a flip-chip wafer-level packaging process to solve the above-mentioned problems. Before packaging and long bumps, the recesses above the dissolving wire are filled with a photoresist that is easy to remove. Substance, as a temporary protection agent for the melting wire structure, in subsequent operations such as plating long bumps, etc., to protect the fuse from pollution and oxidation, remove the easily removable substance in front of the laser repair to achieve the right The fuse has the function of temporary complete protection. According to the present invention, a flip-chip wafer-level packaging process includes the following steps: Length: Round for supply. The wafer is integrally formed and includes a plurality of wafers. Each f wafer has a pad, a fuse, and at least An insulating layer is used to route the solder pad and has a concave hole corresponding to the fuse; fill the concave hole with a protective agent; form a bump on the solder pad; remove the protective agent; test the wafer to distinguish Whether there are any defective products that can still be repaired;? Repair repair, which uses laser to irradiate the fuse without protective agent in the recess; cut the wafer under the knife. [Detailed description of the invention]

= Refer to the attached drawings' The present invention will list the following embodiments to explain the process flow of the wafer-level packaging process of the flip chip is shown in Figure 1: The steps of the agent 72 are: One wafer '' 41, `` Fill protection and burn 1+ to form bumps '' 43, `` Remove protective agent '' 44, `` (Pre-burn) test wafer '' 45, `` Laser repair '' 46, `` Test wafer '' 47

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"Cut wafer" 48 and "printing, optical inspection, shipment inspection" 4 g, etc., which will be described in detail later. First of all, in the step of “providing a wafer” 41, a wafer-body molding generally includes a plurality of [thousands] of wafers 20, as shown in FIG. 2, each wafer 20 has a silicon substrate 21, A first insulating layer 22, such as a field oxide, is formed on the silicon substrate 21, and it carries a molten wire 23 made of various conductive materials, such as tungsten, polycrystalline silicon, aluminum, or polycide. Change the path of the redundant circuit and the integrated circuit, and open on top of the silicon substrate 21 and the first insulating layer 22 to form a first insulating layer 24. Generally, the second insulating layer 24 has a multilayer composite structure, which makes melting The wire 23 is deeply trapped in the second insulating layer 24. The second insulating layer 24 has a recessed hole 27 or an exposed opening corresponding to the fuse 23, so that the thickness of the second insulating layer 24 above the fuse 23 becomes thinner. The molten wires 23 are irradiated with laser light, and each wafer 20 includes at least one bonding pad 25 exposed on the second insulating pad 25.

After that, in the step of “filling the protective agent” 42, as shown in FIG. 3, the recess 27 is filled with a material such as a photoresist 26 or other materials that can be easily removed by a manufacturing process, and is used as a fuse 23 process. As a temporary protective agent, it is preferable to form a shielding cap [cap] on the recessed hole 27 by a process to prevent substances that are easy to remove from being improperly dissolved. For the method for forming the above-mentioned photoresist 26, spin coating can be used. coating] method to form a layer of photoresist 26 (photoresist) on the outer surface of the second insulating layer 24. The photoresist 3 agent 26 can produce photochemical reactions and change the structure. The material can be phenol resin, Novolac

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Positive photoresist of polymethyl methacrylate or negative photoresist such as diazide, wherein the photoresist 26 is also filled in the recess 27, and if the photoresist 26 is negative photoresist Expose the photoresist 26 above the recessed hole 27 to cause a photoreactive change in its structure, so that it forms a shielding cover that is insoluble in the developer, and then wash off the outer surface of the second insulation layer with dimethylbenzene. The photoresist 26 in the recessed hole 27 is retained by the shielding cover, or when the photoresist 26 is a positive photoresist, except for the photoresist 26 above the recessed hole 27, Expose the other photoresist 26 on the outer surface of the second insulating layer 24, and then remove it with an alkali metal solution or an organic alkali solution, so that the structure with the photoresist 26 is directly formed in the recessed hole 27, and then Bake the photoresist 2 6 [hard bake] to make it harder and remove moisture. Next, before the step of "forming bumps" 43, it is necessary to "form a metal layer under the bump" first. The fourth figure is to form an under bump metallization by sputtering, hereinafter referred to as "under bump metallization". UBM layer 31, the material of the UBM layer 31 may be selected from the group consisting of chromium, copper, titanium,

Nickel, gold, vanadium, or other appropriate materials, and then, as shown in FIG. 5, in the step of “bump formation” 43, a mask 32 is covered on the UBM layer 31, and the mask 32 is provided with solder pads. An opening is formed at 25 locations, so that the UBM layer 31 at that location is exposed. The υβΜ layer 31 at this location is covered with a bump 33, such as lead-tin alloy or gold, and then removed. The UBM etching process is performed after the photomask 32 and the other non-bump metal layers 31 of the non-connection pads 28 are re-soldered. Next 'in the step of "removing the protective agent" 44 such as dry etching or wet

Page 9 498531 V. Description of the invention (6) = The photoresist layer 26 is removed in a engraved manner to form a cross-sectional view as shown in FIG. 6, "There is no photoresist 26 in the recess 27 for laser irradiation. After repairing, in the [pre-burning] test wafer "step 45, repairable wafers are identified by electrical testing. In addition, a preroll t may be added during or before the test of the wafer from [Μα-111] It is to place at least one wafer in a burn-in test. Generally, the burn-in environment of the wafer is 75 ~ 150 ° C and it lasts for 12 to ΛΛ, etc., which can eliminate the potentially defective wafer [or In order to use multiple daily films, they are classified as defective products that do not need to be repaired and cannot be repaired. _good. . 、 Defective products that can still be repaired and after the failure, the laser device 34 is irradiated to repair the above-mentioned laser repair that is still repairable after testing ”, and then the“ test wafer ”47, said after the performance or quality of the wafer. "Cut the wafer" 48 to obtain a [burn-in] test wafer with a flip-chip type, and finally. Such as: sub, optical inspection and shipping inspection "49, in the steps of recessed holes 2 == key long bumps, [burn-in] test, etc., the recessed holes 27 are still filled with photoresist 26, so the armor assembly process is Subsequent work processing, fuse] Said that the grading seal has the function of temporarily and completely protecting the fuse 23 'to reach the photoresist 26 in the recessed hole 27 for laser repair, so that: = The fuse 23 has no temporary protection problem. Therefore, the scope of protection of the present invention should be regarded as the attached application patent! Anyone who is familiar with this art without departing from the present invention: Any changes and modifications made within the scope of the criminal law are the sum of the present invention.

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Page 11 498531 Brief description of the drawings [Illustration of the drawings] Figure 1: The present invention overlays Figure 2 · Partial cross section according to the present invention Partial cross section according to the present invention Partial cross section according to the present invention Section 7 according to the present invention is shown in Figure 7: US Patent No. 1 [Solution of Drawing Numbers] 10 Integrated Circuit Silicon Substrate Silicon Dioxide Layer Silicon Dioxide Layer Chip Silicon Substrate Second Insulation Layer Under Hole Bump Metal Layer First 3 figure 4 figure 5 figure 6 figure 11 14 16 20 21 24 27 31 Flow chart of wafer-level packaging process for wafers; Wafer-level packaging process for flip-chips, schematic diagram of the provided wafers; Wafer-mounted crystals Round-level packaging process, no intention of filling the protective agent; flip-chip wafer-level packaging process to form a schematic cross-sectional view of the gold content under the bump; Wafer-level packaging process, the intention of laser repair; and Section No. 5,729,041 "protective film applied to semiconductor integrated wire window protection" cross-sectional view. 12 15 Field oxide layer Spin-coated glass 13 Fuse 17 Opening hole 18 Protective layer 22 First insulating layer 23 Fuse 25 Solder pad 26 Photoresist 32 Photomask 33 Bump

Page 12 498531 Brief description of the diagram 34 Laser device 41 Provide wafer 42 Fill protector 43 Form bump 44 Remove protector 45 [Burning] test 46 Laser repair 4 7 Test wafer 48 Cut wafer 49 Print , Optical inspection and shipping inspection

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Claims (1)

498531 6. Scope of patent application [Scope of application for patent application] 1. A flip-chip wafer-level packaging process includes the following steps: ^ For a wafer, the wafer is integrally formed to include a plurality of wafers, and each wafer has a A solder pad, a fuse, and at least one insulating layer, the insulating layer is exposed on the solder pad and has a recessed hole corresponding to the fuse; a protective agent is filled in the recessed hole; a bump is formed on the soldered pad; the protective agent is removed Test the wafer to distinguish if there are still defective products that can be repaired; Laser repair is to irradiate the fuse without protective agent in the recess with laser; and cut the wafer. 2. The flip-chip wafer-level packaging process described in item 1 of the scope of patent application, wherein in the step of filling a protective agent in the recess, the protective agent is a photoresist. 3. The flip-chip wafer-level packaging process described in item 1 of the scope of the patent application, in which a bump under metal layer [UBM] is formed before bumps are formed. 4. The flip-chip wafer-level packaging process described in item 3 of the scope of the patent application, wherein a metal layer under the bump [UBM] is formed by sputtering. 5. The flip-chip wafer-level packaging process described in item 1 of the scope of the patent application, wherein the bumps are formed by electroplating. 6. The flip-chip wafer-level packaging process described in item 1 of the scope of the patent application, wherein the wafer is pre-burned before the wafer is tested. 7. Wafer-level wafer-level packaging as described in item 1 of the scope of patent application 498531 6. Range of patent application, in which the wafer is pre-burned at the same time during the test of the wafer Φ page 15