TW502411B - A wafer level packaging process for protecting the fuses - Google Patents

Abstract

A wafer level packaging process for protecting the fuses comprises in turn: providing a wafer with RC fuses, depositing a metal layer for temporary protection, bumping the wafer, removing the metal layer, probing the wafer, laser repairing probing the wafer, and dicing the wafer. The laser repairing procedure is after bumping and probing. While bumping and probing, the metal layer in recess located on each fuse to temporarily protect the fuses in the wafer level packaging process.

Description

502411 V. Description of the invention (1) [Field of the invention] The present invention relates to a wafer-level packaging process for a protective fuse, and particularly relates to a wafer-level packaging process for preparing a protective fuse for a flip-chip structure. [Previous technology]; Usually more complex integrated circuits have a higher probability of defect occurrence in manufacturing, such as local short circuit or disconnection, so a redundant circuit [redundant clRUit] and a fuse structure of the connected standby circuit [redundant c ^ rjuit fuse structure, hereinafter referred to as 眈 fuse], especially high-capacity memory chips or complex system-on-chips (System On Same ChlP), use the break of the RC fuse to change the circuit of the integrated circuit.

Sida [redundant circuit, RC] circuit path, after testing = part of the defective integrated circuit, blow the RC fuse with laser irradiation, can replace some of the defective integrated circuit with the circuit, and can Remedial, laser repair. In the US Patent No. 5, 326, 709, the test procedure for preparing a semiconductor device is described below. The test method is as follows: The semiconductor device has a backup circuit. The steps are as follows: The first step was to etch the phosphorous-silicon glass (PSG) and nitride films to open the solder pads. Then, the lasers were ordered in accordance with the thickness of the bed, the "M & M", and the wide film. Speculation 5 "," Testing of Laser Repairing Repaired Wafers "," Offline Marking ", ^ λ Crystal's wafer-level test system is under analysis and analysis Yong = uncovering a bare repair, laser repairing, * analysis Laser repair should be performed immediately after the laser repair is usually performed in the form of tbare chin Ί χ τ 1 before unpacking, and then cut to advance

Page 5 502411 V. Description of the invention (2) The packaging of individual wafers is not applicable to the current wafer-level packaging process [wafer level packaging], which does not involve long bumps [bumping] and The connection relationship between burn-in and other manufacturing processes and laser repair, and the aforementioned flip chip refers to the formation of conductive bumps on the surface of the wafer for flipping the wafer for surface bonding. It is known that there are various types of RC refining yarns. For example, deep penetration type RC fuses are formed with thinned pits in the protective layer above the dazzling wire [refer to U.S. Patent No. 6,1 21, 07]. Laser irradiation, but it is easy to cause problems such as "fuse fouling and oxidation" during the process of long bumps and burn-in in flip-chip wafer-level manufacturing. Therefore, how to During the process of burn-in and other processes, effectively protecting the fuse and finally providing laser irradiation for repair is an urgent problem to be solved. In U.S. Patent No. 5,729,041, "Reverse Protective Film for Melting Wire Protection of Semiconductor Integrated Circuits" describes an integrated circuit with a fuse structure. As shown in Figure 7, the integrated circuit The 10 series has a stone substrate 11 and a field oxide layer 2 [field o ^^ de] is formed on the silicon substrate 11 to carry a fuse 13 such as tungsten or polycrystalline silicon on the silicon substrate. A plurality of insulating layers, such as a silicon dioxide layer, a spin on glass, and a silicon dioxide layer 16, are formed on the oxide layer 12 and the insulating layer corresponding to the fuse 13 A recessed opening 17 is formed at the position, so that the insulating layer above the wire 13 is thinned, and a high-transparency protective layer 18 is formed on the exposed surface of the dioxide layer 16 and the opening. It has laser light transmittance of more than 50%. Under the condition that it does not excessively affect the field radiation compensation, the fuse 13 is properly protected to prevent pollution or gold.

502411 V. Description of the invention (3) belongs to oxidation, however, this highly transparent protective layer 18 exists permanently on the integrated circuit 10 after it is manufactured. The layer 18 must be precisely controlled for its degree, material and process. Conditions, which are promoted by electropolymerization: = II

Enhance Chemical Vapor Deposition (PECVD) is used to introduce silane and ammonia [ammonia]. The material of the protective layer 18 must have a silicon to nitrogen ratio of 1: 1.2 to 1: 1.6, and its thickness must be controlled. 3,000 to 15,000 angstroms (angstrom) in order to avoid affecting the subsequent, two-shot repair effect. In addition, the fuse junction f 'located under the recessed trench shape should be deposited on the surface of the recessed trench. It is quite difficult to form a transparent protective layer with uniform thickness. η [Objective and Summary of the Invention]

The main purpose of the Ibci invention is to provide a wafer-level packaging process for protecting fuses to solve the above problems. A cavity that can be moved = RC fuse is deposited in the cavity above the package i and RC fuse. Temporary protection, processed in subsequent operations, such as ㊁: long: Baozun metal ^ 'to achieve temporary complete protection of the fuse = remove this = the wafer-level packaging process of the protective fuse of the present invention, 1: step Provide a wafer. The wafer is integrally formed. The wafer has a plurality of solder pads, a plurality of fuses, and at least a wafer. The insulating layer exposes the solder pads and is above the fuses. Forming an edge layer, depositing a protective metal layer in the recess; a cavity; forming a bump on the pad; removing the protective metal layer;

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Test the crystal Bi to distinguish whether it is still repairable. Laser repair is to cut the wafer by irradiating the laser on the recess: Liangkou. The fuse of r, and the [detailed description of the invention] ί! the Γ! type, the present invention will enumerate the following examples: Figure _ it: 4 fuse m-level package 1-pass flow chart is as the first 1 :: ' The steps involved are: "Provide 41," Shen J Bao Er metal layer "42," Bump formation "43," Remove protective metal "" 44 ", [pre-burned] test wafer" 45 , "Laser repair" 46, "test wafer" 47, "diced wafer" 48, and "printing, optical inspection, output inspection" 49, etc., which will be described in detail later. First of all, in the step of “providing a wafer” 41, a wafer-to-mould generally includes a plurality of [about several hundreds to thousands of] wafers 20, as shown in FIG. It has a silicon substrate 21, and a first insulating layer 22, such as a field oxide layer, formed on the silicon substrate 21. It bears RC fuses 23 made of various conductive materials, such as tungsten, polycrystalline silicon, and aluminum. Or polycide, which is connected to a redundant circuit (RC) to change the path of the standby circuit and the integrated circuit, and forms a second insulating layer 2 on the silicon substrate 21 and the first insulating layer 22 4. Generally, the second insulating layer 24 has a multilayer composite structure, including at least a conventional bare-crystal protective layer and a flip-chip protective layer, and contains a multilayer integrated circuit structure. The RC fuse 23 is deeply trapped in the first Within the two insulating layers 24, the second insulating layer 24 has a recess 27 corresponding to the RC fuse 23, so that the thickness of the second insulating layer 24 above the RC fuse 23 becomes thinner so that the fuse is illuminated by laser light.

Page 502411 V. Description of the invention (5) 23 'and each wafer 20 includes a plurality of bonding pads 25 exposed to the second insulating layer 24. In addition, in this embodiment, the wafer 2 The solder pad 25 is especially a flip chip bonding pad, which is arranged in a matrix and interconnected with corresponding redistribution metal wires on the same layer, and is conducted to a bare die bond originally in the middle or periphery of the wafer. [Bare chip bonding pad] [not shown], however, the bonding pads 25 of the wafer 20 should not be limited to a matrix arrangement, and the bonding pads thereof can also be distributed in the middle of one surface of the wafer. Afterwards, in the step of “depositing a protective metal layer” 4 2, as shown in FIG. 3, a protective metal layer 26 is deposited in the cavity 27 as a temporary protective property in the process of the fuse 23. The metal layer 26 is usually deposited by physical vapor deposition, chemical vapor deposition, plasma-assisted chemical vapor deposition, or even sputtering deposition. A metal layer is first formed on the second insulating layer 24. 'Then lithographic development and etching are used to remove other metal layers not in the cavity 27 to form the protective metal layer 26, wherein the protective metal layer 26 is selected from titanium, chromium or nickel, Preferably, the protective metal layer 26 should match the material in the UBM layer 31 [Under Bump Metallization] to facilitate removal.

The next step of "forming bumps" 43 is to "form the metal layer under the bumps". The figure 4 shows the formation of a metal layer under the bumps by vapor deposition or SpUftering (Under Bump).

Metallization] A kind of composite multi-layered gold hereinafter referred to as UBM layer 31. The UBM layer 31 is a metal layer, such as copper-copper, copper-copper alloy-copper, copper-coated titanium,

Titanium-copper-nickel or selected from chromium, copper, titanium, nickel, tungsten, gold, palladium, vanadium

502411 V. Description of the invention (6) and other appropriate laminated materials, it is known that a gold layer is deposited thinner on the uppermost layer of the UBM layer 31 to avoid copper oxidation. Then, as shown in FIG. In the step of the "bump" 43, a mask 32 is covered on the UBM layer 31, and the mask 32 forms an opening at a portion with a pad 25, so that the UBM layer 31 at the portion with the pad 25 is exposed. A bump 33, such as lead-tin alloy or gold, is applied to the UBM layer 31 of the opening by plating, and then the connecting pad 28 is removed by an etching method after removing the photomask 32. The outer UBM layer 31, and the _ layer 31 remaining under the bump 33 is naturally retained. After the bump 33 is reflowed, the UM etching is completed. Then, the wafer is etched or wet to form a sexual metal layer 2 6 Test wafers ”4 5 In addition, this“ protective metal layer or previously attached to a pre-fired 7 5 ~ 1 5 0 0c Bingliang wafer [for analysis after it can still be repaired, remove the protection In step "44", the material metal layer 26 is removed in a manner such that the wafer is shown in Fig. 6 The cross-section type, at this time, the cavity is' repairable by laser irradiation, and then, in the [pre-tick] step, the repairable chip is identified by electrical testing. It can also be in the step of "Remove" 44 steps. At this moment, in the bucket and test machine, it is generally said that n, / will be on the wafer side for 12 to 128 hours. The burn-in% system is or For wafers with short service life, "too potential? Multiple wafers in the wafer are used for wafer-level testing of defective products and cannot be repaired." Tonic products are repaired with laser equipment 34: test can still be repaired

! dc]

Defective products are classified into multiple categories such as "printing due to the contamination and oxygen efficiency of the concave wire during the printing process, and laser repair problems. Reaching the" laser repair "46, and again the" test wafer "47, Chip performance or quality, then "cut the wafer" 48, to obtain [pre-burn] test and flip chip wafer, and finally, & line, optical inspection and shipment inspection "49 for shipment . The protective metal layer 26 is still deposited in the step 27 such as the sputter-plated UBM layer, the electroplated long bump, and the [pre-burn] test. Therefore, the present invention: the round-level packaging process is processed in subsequent operations, and the fuse 23 is not affected. Reach the function of temporarily and completely protecting the fuse 23, and etch ~ the protective metal layer 26 within Γ within 27 to provide and return "the fuse 2 3 has no temporary protection door, so the protection of the present invention a. Whichever prevails, anyone familiar with any changes or techniques made within the scope defined by the scope of the patent application attached to the second appendix shall not depart from the spirit and scope of the present invention. Modifications and modifications belong to the present invention. Protection Fanguan 411

[Illustration of the diagram] Figure 1: Block flow diagram of the wafer-level packaging process of the protective fuse of the present invention; Figure 2: Wafer-level packaging process of the protective fuse according to the present invention, the round part provided Sectional schematic diagram; Figure 3 · Partial sectional schematic diagram of a protective metal layer deposited in a wafer-level packaging process of a protective fuse according to the present invention;

Figure 4: A schematic sectional view of a portion of a metal layer under the bump 々 formed by a wafer-level packaging process for protecting a fuse in accordance with the present invention; A

Figure 5 · Sectional schematic diagram of the wafer-level packaging process for protecting fuses according to the present invention; Figure 4 苐 6: Wafer-level packaging process for protecting fuses according to the present invention, removing the seventh metal layer And laser repair part of the cross-sectional schematic diagram; Figure 1 US patent No. 5,729, 041 "Semiconductor integrated circuit protection of a fuse window protection film" cross-section sound circle [Figure No. Explanation】 "Qiu called Buen Figure 10 Integrated circuit 11 Silicon substrate 14 Second oxide layer 16 Month oxide layer 20 Wafer 21 Silicon substrate 24 Di-insulator layer 27 Cavity 12 Field oxide layer 15 Spin-on glass 17 Opening hole 22 The first insulating layer 25 Welding pads 13 Fusible wire 18 Protective layer 23 Fusible wire 2 6 Protective metal layer

502411 Brief description of drawings 31 UBM layer 32 Photomask 33 Bump 34 Laser device 41 Provide a wafer 42 Deposit protective metal layer 43 Form bump 44 Remove protective metal layer 45 [Flame] Test 46 Laser repair 47 Test wafers 48 Cut wafers 49 Printing optical inspection and shipment inspection Λ

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Claims (1)

The steps include: there are a plurality of wafers, each and at least ^ one insulation has a recess above the fuse Φ ^ — 丨 "Fei Zhimin W W repairing, the laser cuts the crystal 11 in the cavity. < Solution, application, patent application, patent application scope [Patent application scope], a wafer-level packaging process for protecting fuses, providing a wafer, which is integrated into a wafer, including a wafer with a plurality of pads, A plurality of fuse layers; the insulating layer bares the pad and forms a cavity; deposits a protective metal layer on the cavity; forms a bump on the pad; removes the protective metal layer; cuts the wafer to make t Application: Wafer-level protection of dazzling silk as described in item i of the patent scope * In the step of depositing a protective metal layer, the guaranty belongs to 9 series selected from the group consisting of Chin, Lo, or Nickel. System; application: protection of the crystals of dissolved silk as described in item 1 of the patent scope _ [UBM '/ ,. Before forming a bump, first form the metal under the bump ^ = the wafer-level package of the protective fuse described in item 3 of the patent application scope, which is formed by vapor deposition or sputtering [gutter] A metal layer under the bump [UBM layer]. ^ Wafer-level package for protection fuses described in item 丨 of the patent scope of the patent, where the bumps are formed by electroplating. Wafer-level package for protection fuses as stated in claim 1 : ≫ υ / 4Π Patent Application Process ′ In which the wafer is pre-burned before the wafer is tested. System " Please patent No.! In the process of testing the wafer, the protection fuse described in the above item is "in the process of testing the wafer, and the wafer-level package circle of the protection fuse described in the crystal item is burned in parallel at the same time. For example, the first process in the scope of patent application, wherein a crystal pad is provided in a matrix arrangement. Wafer-level packaging of protective fuses as described in the first patent application The manufacturing process includes the following steps: After the laser is repaired, the wafer is tested to sort the wafer widely. Page 15