TW495941B - Method for packaging BGA for a voiding molding flash - Google Patents

Method for packaging BGA for a voiding molding flash Download PDF

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Publication number
TW495941B
TW495941B TW90121545A TW90121545A TW495941B TW 495941 B TW495941 B TW 495941B TW 90121545 A TW90121545 A TW 90121545A TW 90121545 A TW90121545 A TW 90121545A TW 495941 B TW495941 B TW 495941B
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TW
Taiwan
Prior art keywords
wafer
patent application
fingers
scope
tape
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Application number
TW90121545A
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Chinese (zh)
Inventor
Jansen Chiu
James Lai
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Walton Advanced Electronics Lt
Walsin Advanced Electronics
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Priority to TW90121545A priority Critical patent/TW495941B/en
Application granted granted Critical
Publication of TW495941B publication Critical patent/TW495941B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Abstract

A process for BGA package comprises: providing a lead frame, attaching dies, electrically connecting, attaching a tape, filling a package body, removing tape, forming a plurality of metal balls. A plurality sets of leads are derived form a lead frame and are formed by half-etching, before filling package body, the tape is attached to the solder surfaces of protrusive portions on the plurality sets of leads in order to avoid over-flow of the package body. The package body is covered on the upper surfaces of leads, so that the bonding strength of the leads with the package body is stronger, the leads will not peel and crack, while a unit of package cut to single BGA package.

Description

495941495941

【發明領域】 本發明係有關於一種防止溢膠之球格陣列BGA ( ba i i t d =rray )封裝方法，特別係有關於一種能降低製造成 、、、溢膠問題及封膠體結合強度較強之bga封方法。 【先前技術】 在美國專利案第5,999,413號「樹脂密封型式之半導 ，裝置」中，揭示一種球袼陣列BGA (baU grid array )[Field of the Invention] The present invention relates to a ball grid array BGA (ba iitd = rray) packaging method for preventing overflow, and particularly relates to a method that can reduce manufacturing problems, such as overflow problems and strong bonding strength. bga seal method. [Prior art] In US Patent No. 5,999,413 "Resin-sealed type semiconductor, device", a ball grid array BGA (baU grid array) is disclosed.

半導體裝置，如第1圖所示，該半導體裝置主要包含一晶 片2 1、一封膠體2 6、複數個引指2 4、複數個金屬導線2 5及 複數個銲錫球27，其中引指24係以衝壓（punching )方式 升v成此時引^曰2 4係為具有電性連接面2 4 a、外部連接面 24b及裸露面24c之金屬薄板，然後再以蝕刻（etching )A semiconductor device, as shown in FIG. 1, the semiconductor device mainly includes a wafer 21, a colloid 26, a plurality of fingers 2 4, a plurality of metal wires 25, and a plurality of solder balls 27, of which the finger 24 It is stamped (punching) to rise to v at this time. 2 4 is a metal sheet with an electrical connection surface 24a, an external connection surface 24b, and an exposed surface 24c, and then is etched.

方式形成嵌合面24x，以利於在引指24上形成銲錫球27， 而晶片21係具有一上表面21a、一下表面21c及複數個側面 2 1 b，在晶片2 1之上表面2 1 a中央部份係習知地形成有複數 個焊墊22 (bonding pad)及積體電路元件（integrated circuit element)(圖未繪出），晶片21之上表面21a係 以膠帶黏固於引指24之部份下表面，並以金屬導線25電性 連接晶片21之焊墊2 2與引指2 4之電性連接面2 4 a。The fitting surface 24x is formed in a manner to facilitate the formation of a solder ball 27 on the index finger 24, and the wafer 21 has an upper surface 21a, a lower surface 21c, and a plurality of side surfaces 2 1 b, and a surface 2 1 a above the wafer 2 1 The central part is conventionally formed with a plurality of bonding pads 22 (bonding pads) and integrated circuit elements (not shown). The upper surface 21a of the chip 21 is fixed to the index finger 24 with adhesive tape. A portion of the lower surface is electrically connected to the electrical connection surface 2 4 a of the pad 21 and the finger 24 of the chip 21 with a metal wire 25.

在其封膠（molding )過程中，係先形成一上、下模 具（圖未繪出），下模具有一凹洞，該凹洞之深度係等於 晶片21與膠帶之總和高度，而上模具亦有一凹洞，其深度 略小於下模具之深度，然後以一壓力使上、下模具接合， 再灌注尚未固化之熱固性封膠體26，由於上、下模均^有During the molding process, an upper and a lower mold (not shown) are formed first. The lower mold has a cavity. The depth of the cavity is equal to the total height of the wafer 21 and the tape. The upper mold is also There is a recess, the depth of which is slightly smaller than the depth of the lower mold, and then the upper and lower molds are joined by a pressure, and the uncured thermosetting sealing gel 26 is refilled.

495941 五、發明說明（2) θ片2;之：Γ使金屬導線25、引指24之電性連接面24a及 ιΓ二ΐ la與侧邊2ib密封於封膠體26内，又下模 裰霞晶：21與膠帶之總和高度，所以使晶片21之下 ir:Λ 體26外，以提供散熱之功效，完成封 人而？4 ，多的引指切除，並形成銲錫球27於引指24之嵌 a X，以作為表面結合至一印刷電路板 】printed circuit board，PCB)之連接點而由於上模 具有-凹洞，所以封膠體26在兩相對 出部26a及一階梯部26b，如第1圖所*，鲜錫球m凸495941 V. Description of the invention (2) θ sheet 2; of: Γ makes the electrical connection surface 24a and ιΓ of the metal wire 25, the finger 24, and ΐΓ and the side 2ib are sealed in the sealing compound 26, and the lower mold is made of Xiaxia The total height of the crystal: 21 and the tape, so that the ir: Λ body 26 under the wafer 21 is provided to provide heat dissipation and complete sealing. 4, the multiple fingers are cut off, and a solder ball 27 is embedded in the finger 24 a X, as a surface bonding to a printed circuit board (printed circuit board) PCB connection point because the upper mold has a -cavity, Therefore, the fresh tin ball m is convex at the two opposite exit portions 26a and a stepped portion 26b as shown in Fig. 1 *.

(I ί度封膠體26之凸出部26a，才能與印刷電路板 進丁衣面結合。 先用ΐί，半'體裝置具有諸多缺點，第―、引指24需要 先用衝壓（punching)方式，然後再用蝕刻（^^丨 方式形成，雖然此半導體裝置只需一導線架，但 成部需要兩個製造方式，增加了製程步驟與製造:^ 二、封膠體26在兩相對之引指24間具有一凸出部“^，’ 錫球27之形成高度必須高於此凸出部26a，才能盘 路板進行表面結合，所以凸出部26a限制了銲錫球 成高度；第三、在封膠過程中，係以上、 ^ 式進行封膠，在上、下模具接合不緊密的情況下，; 二膠，在製程中需再加入清除二膠 之步驟（如電漿 >月洗…等）；第、引指24之 24b及裸露面24c均裸露於封膠體26外，所以弓丨° = 體2 6之結合強度較小，在切割刀具將每_ ” * / 对裝早位切割成 W5941 五、發明說明（3) 獨立之半導體 【發明目的及 本發明之 方法，此BGA圭 架且以半蝕刻 製造成本，而 出部之焊接面 中不需有移除 護晶片免於外 面’使引指與 一封裝單位切 脫落斷裂…等 依本發明 提供一導 指具有一上表 凸出部係形成 黏固一晶 上表面及一下 墊； 電性連接 應引指之上表 提供一膠 面； 形成一熱 裝置時，會產生引指24脫落斷裂…等問題。 概要】 主要目的在於提供一種防止溢膠之BGA封裝 ί裝方法中，其複數組引指係取自同一導線 (half-etching)之方式形成，所以能降低 在封膠前，係以一膠帶黏貼於複數組引指凸 ’該膠帶能防止溢膠的問題產生，所以製程 溢膠的步驟，此外封膠體係密封晶片，能保 界環境之侵害’且封膠體覆蓋於引指之上表 封膠體間之結合強度較強，在切割刀具將每 割成獨立之BGA封裝結構時，不會產生引指•货 問題。 之防止溢膠BGA封裝方法，其包含步驟有： 線架’該導線架係具有複數組引指，每一引 面及一下表面，其上表面具有一凸出部，該 有一焊接面； 片於每一組引指之下表面，該晶片係具有一 表面，且晶片之上表面係形成有複數個焊 曰曰片與引指，使得晶片之焊墊電性導通至對 帶3亥膠帶係黏貼複數組引指凸出部之焊接 固性封 495941 五、發明說明（4) 面； 移除該膠帶，使複數組引指之凸出部之焊接面裸露於 封膠體外；及 形成複數個金屬球於引指凸出部之焊接面上。 【發明詳細說明】 請參閱所附圖式，本發明將列舉以下之實施例說明： 在本發明之一具體實施例中，第2a圖至第2f圖係為一 防止溢膠之BGA封裝方法中製程步驟之截面圖。 首先如第2 a圖所示，提供一導線架，該導線架係具有 複數組引指140，每一引指14〇係具有一上表面141及一下 表面142，其上表面141具有一凸出部143，該凸出部143係 形成有一焊接面1 4 4，而導線架係以半蝕刻之方式形成引 指140及其上表面141之凸出部143。 再如第2b圖所示，將晶片11〇之上表面η!以膠帶13〇 黏固於每一組引指140之下表面142，該晶片110係可為 DRAM、SRAM、flash、DDR或Rambus等記憶體晶片、微處理 器、邏輯性（logic )或是RF射頻之晶片，其材質為矽、 坤化鎵或其它半導體材料，晶片丨丨〇係具有一上表面丨丨1及 下表面112 ’而在晶片11〇上表面ill之中央部份係習知 地形成有複數個焊墊113 (bonding pad)及積體電路元件 (integrated circuit element )(圖未繪出），之後， 如第2c圖所示，以金屬導線丨5〇電性連接晶片丨1〇之焊墊 113與引才曰140之上表面141 ’其係以打線（w^re bonding )之方式使晶片11 〇之焊墊11 3電性導通至對應引指1 4 〇之(I) The protruding portion 26a of the sealing compound 26 can be combined with the printed circuit board. First, the semi-body device has many disadvantages. The first and fourth fingers 24 need to be punched first. Then, it is formed by etching (^^ 丨). Although this semiconductor device only needs a lead frame, the manufacturing process requires two manufacturing methods, which increases the process steps and manufacturing: ^ Second, the encapsulant 26 refers to the two opposite sides. 24 have a protruding part "^, 'The formation height of the solder ball 27 must be higher than this protruding part 26a in order to bond the circuit board to the surface, so the protruding part 26a limits the height of the solder ball; third, in During the sealing process, the above and ^ methods are used for sealing. When the upper and lower molds are not tightly connected, the second glue needs to be added in the process of removing the second glue (such as plasma > monthly washing ... Etc.); The first and second fingers 24 of 24b and the exposed surface 24c are exposed outside the sealing compound 26, so the bow 丨 ° = the body 2 6 has a small bonding strength, and the cutting tool will cut every Cheng W5941 V. Description of the invention (3) Independent semiconductor [Objective of the invention and the present invention Method, the BGA is manufactured at half-etching cost, and the soldering surface of the output part does not need to be removed to protect the wafer from the outside, so that the index finger and a packaging unit are cut off and broken ... etc. According to the present invention, a guide is provided. The finger has a protruding part on the upper surface to form a fixed upper surface and a lower pad; the electrical connection should provide an adhesive surface on the upper surface of the finger; when a thermal device is formed, the finger 24 will fall off and break ... Summary] The main purpose is to provide a BGA packaging method for preventing overflow of glue. The complex array of fingers is formed by the same wire (half-etching), so it can reduce the use of a tape before sealing. Adhere to the index finger of the complex array. 'This tape can prevent the problem of overflowing glue, so the process of overflowing the glue, in addition, the sealing system seals the wafer, which can protect the environment from environmental damage.' The bonding strength between the colloids is strong. When the cutting tool cuts each into an independent BGA packaging structure, it will not cause the problem of lead and goods. The method of preventing the overflow of the BGA packaging, which includes the steps: The wire frame system has a plurality of index fingers, each leading surface and the lower surface, the upper surface of which has a protruding part, which has a welding surface; a piece is on the lower surface of each set of index fingers, and the wafer system has a surface, and The upper surface of the wafer is formed with a plurality of soldering wafers and fingers, so that the pads of the wafer are electrically connected to the soldering solid seal 495941 with the protrusions of the array of fingers with the adhesive tape complex adhesive system. (4) surface; remove the tape, so that the welding surface of the protruding portion of the lead of the complex array is exposed outside the sealant; and form a plurality of metal balls on the welding surface of the protruding portion of the leading finger. [Detailed description of the invention] Please refer to the attached drawings. The present invention will be illustrated by the following embodiments. In a specific embodiment of the present invention, FIGS. 2a to 2f are cross-sectional views of process steps in a BGA packaging method for preventing overflow of glue. . First, as shown in FIG. 2a, a lead frame is provided. The lead frame has a plurality of fingers 140. Each finger 14 has an upper surface 141 and a lower surface 142. The upper surface 141 has a protrusion. The protruding portion 143 is formed with a soldering surface 1 4 4, and the lead frame is formed with a protruding portion 143 of the lead finger 140 and its upper surface 141 in a semi-etched manner. Then, as shown in FIG. 2b, the upper surface η! Of the wafer 11 is fixed to the lower surface 142 of each set of fingers 140 with an adhesive tape 13. The wafer 110 may be DRAM, SRAM, flash, DDR, or Rambus. Other memory chips, microprocessors, logic (logic) or RF radio frequency chips, the material is silicon, gallium or other semiconductor materials, the chip 丨 丨 〇 has an upper surface 丨 丨 1 and a lower surface 112 'And a plurality of bonding pads 113 (bonding pads) and integrated circuit elements (not shown) are conventionally formed on the central portion of the top surface ill of the wafer 11, and then, as shown in FIG. 2c As shown in the figure, the metal pad 丨 50 electrically connects the pad 113 of the wafer 丨 10 and the top surface 141 of the lead 140, which is a method of bonding the wafer 11 〇 by means of w ^ re bonding. 11 3 is electrically connected to the corresponding finger 1 4 〇

第8頁 495941 五、發明說明（5) 上表面141 然後’如第2d圖所示，在封膠前，係以一膠帶17〇黏 貼複數組引指140凸出部143之焊接面144，然後以壓模 (mo 1 d 1 ng )方式灌注尚未固化之熱固性封膠體1 2〇，該膠 帶170能防止封膠體12〇溢出，而封膠體12〇係密封晶片 110、金屬導線150，且覆蓋於引指14〇之上表面141，使引 指140與封膠體120間之結合性良好，接著，如第仏圖所 示，將膠帶170移除，使複數組引指14〇凸出部143之焊接 面144裸露於封膠體丨2〇外，由於在封膠過程中，膠帶17〇 係黏貼於複數組引指140凸出部143之焊接面144，所以不 會有溢膠的問題產t，故在製程中不需要有清除溢膠之步 驟（如電聚清洗…等）。 最後，如第2f圖所示，在引指140凸出部143之焊接面 144上形成金屬球160，該金屬球16〇係作 人_ 印刷電路板之連接點，最㈣每-封裝單彳=切γ刀Y切 割成獨立之BGA封裝結構1〇〇，即完成整個封裝程序，如 3圖所示，其係為BGA封裝結構100之底視圖，複數個金屬 球1 60係呈交錯排列，使金屬球丨6〇之間距離較大，在進疒 表面接合時，金屬球160之間不會因互相接觸而產生問仃 題0 此半導體封裝方法中，該複數組引指14〇係取自同— 導線架且僅以半触刻（half-etching)方法形成，所以处 降低製造成本，而在封膠過程前’係以—膠帶】7〇黏貼: 複數組引指140凸出部143之焊接面144，在注入之封膠體、 495941 五、發明說明（6) 1 2 0固化後’再將膠帶1 7 0移除，該膠帶1 7 〇能防止溢膠的 問題產生，使複數組引指140凸出部143之焊接面144完全 裸露於封膠體120外，所以製程中不需有清除溢膠的步驟 (如電漿清洗…等），使本發明之BGA封裝結構！ 〇0相較於 習知之BGA封裝結構具有較低之製造成本，而該封膠體1 固化後係呈四方扁平狀，無凸出的部份，所以不會限制金 屬球160之形成高度，此外封膠體丨2〇係密封晶片11〇，能 保護晶片11 0免於外界環境（濕氣、塵埃…等）之户宝， 且封膠體120係覆蓋於引指14〇之上表面;41，使引^^〇血 封膠體120間之結合強度較強，在切割刀具將每一封裝單、 位切割成獨立之BGA封裝結構1〇〇時，不會產生 蒗刻…笙μ跑《 υ ^ 故本發明之保護範圍當 者為準，任何熟知此項技藝 範圍内所作之任何變化與修 圍。 視後附之申請專利範圍所界 者，在不脫離本發明之精神 改，均屬於本發明之保護範 定 和Page 8 495941 V. Description of the invention (5) Upper surface 141 Then, as shown in FIG. 2d, before sealing, a tape 17 is used to paste the welding surface 144 of the plurality of array finger 140 protruding portions 143, and then The uncured thermosetting encapsulant 120 is poured by a compression mold (mo 1 d 1 ng). The adhesive tape 170 can prevent the encapsulant 12 from overflowing. The encapsulant 120 is a sealing chip 110 and a metal wire 150, and is covered with The upper surface 141 of the index finger 140 has a good bond between the index finger 140 and the sealing compound 120. Then, as shown in the second figure, the tape 170 is removed, so that the index finger 140 of the multiple index finger 143 is formed. The welding surface 144 is exposed outside the sealing compound. Since the adhesive tape 170 is adhered to the welding surface 144 of the protruding portion 143 of the index finger 140 of the complex array during the sealing process, there will be no problem of adhesive overflow. Therefore, there is no need to remove the spilled glue in the manufacturing process (such as electropolymer cleaning ...). Finally, as shown in FIG. 2f, a metal ball 160 is formed on the soldering surface 144 of the protruding portion 143 of the finger 140, and the metal ball 160 is the connection point of the printed circuit board. = Cut γ knife Y cuts into an independent BGA package structure 100, which completes the entire packaging process. As shown in Figure 3, it is a bottom view of the BGA package structure 100. A plurality of metal balls 1 60 are staggered. Make the distance between the metal balls and 60 larger, and when the surfaces are joined, the metal balls 160 will not cause problems due to contact with each other. In this semiconductor packaging method, the complex array refers to 14 and takes Self-identity-The lead frame is formed only by half-etching method, so the manufacturing cost is reduced, and it is tied to the tape before the sealing process. The welding surface 144, after the injection of the sealant, 495941 V. Description of the invention (6) 1 2 0 After curing, the tape 1 70 is removed, and the tape 1 7 can prevent the problem of overflowing glue and make the complex array The welding surface 144 of the protruding portion 143 of the finger 140 is completely exposed outside the sealing compound 120, so it is not used in the manufacturing process. Step of clearing excess glue (e.g., plasma cleaning, etc. ...), that the BGA package structure of the present invention! 〇0 Compared with the conventional BGA package structure, it has a lower manufacturing cost, and the sealing gel 1 has a square flat shape after curing, and there is no protruding part, so the formation height of the metal ball 160 is not limited. Colloid 丨 20 is a sealed wafer 110, which can protect the wafer 110 from the external environment (moisture, dust, etc.), and the sealed gel 120 covers the top surface of the index finger 14; 41 ^^ 〇 The blood seal colloid 120 has a strong bonding strength. When the cutting tool cuts each package unit and bit into an independent BGA package structure 100, no engraving will be produced ... Sheng μ runs "υ ^ Original The scope of protection of the invention shall prevail, and any changes and modifications made within the scope of this skill will be familiar. Those who fall within the scope of the appended patent applications, without departing from the spirit of the invention, belong to the protection scope of the invention and

495941 圖式簡單說明 【圖式說明】 第1圖：美國專利第5,999,41 3號「含有樹脂密封膠帶之 半導體震置」之半導體裝置之截面圖； =^，明之一具體實施例，「提供一導線架並形 成4複數個弓丨指」後之截面圖； 黏固晶片」後之截 電性連接」後之截 黏貼膠帶並形成封 移除膠帶」後之截 形成金屬球並切 依本發明之一具體實施例 面圖； 依本發明之一具體實施例 面圖； 依本發明之一具體實施例 第2e圖 膠體」後之截面圖； 依本發明之一具體實施例 面圖； 依本發明之一具體實施例 割」後之BGA封裝結構截面圖；及 依本發明之一具體實施例，一BGA封裝結構之底 視圖。 21 晶片 21 a 上表面 22 焊墊 24引指 24b外部連接面 2 5 金屬導線 21b侧面 24a 電性連接面 24c裸露面 21c下表面 24x嵌合面 495941 圖式簡單說明 26 封 膠 體 2 6a 凸 出 部 26b 階 梯 部 27 銲 錫 球 100 BGA封裝結構 110 晶 片 111 上 表 面 112 下 表 面 120 封 膠 體 130 膠 帶 140 引 指 141 上 表 面 142 下 表 面 143 凸 出 部 144 焊 接 面 150 金 屬 導線 160 金 屬 球 170 膠 帶 113 焊墊 <1495941 Brief Description of Drawings [Illustration of Drawings] Figure 1: Sectional view of a semiconductor device of US Pat. No. 5,999,41 3 "Semiconductor vibration containing resin sealing tape"; = ^, one of the specific embodiments, "provided A lead frame and 4 cross-sections are referred to; the cross-section view refers to the "post-cut electrical connection" after sticking the chip, the post-adhesive tape and the seal-removal tape after the cut-off form a metal ball and cut according to this A view of a specific embodiment of the invention; a view of a specific embodiment of the invention; a cross-sectional view of the colloid according to FIG. 2e of a specific embodiment of the invention; a view of a specific embodiment of the invention; A cross-sectional view of a BGA package structure after cutting a specific embodiment of the present invention; and a bottom view of a BGA package structure according to a specific embodiment of the present invention. 21 Chip 21 a Upper surface 22 Solder pad 24 Finger 24b External connection surface 2 5 Metal wire 21b Side surface 24a Electrical connection surface 24c Bare surface 21c Lower surface 24x Fitting surface 495941 Brief description of the drawing 26 Sealant 2 6a Projection 26b Step 27 Solder ball 100 BGA package structure 110 Wafer 111 Upper surface 112 Lower surface 120 Sealant 130 Tape 140 Finger 141 Upper surface 142 Lower surface 143 Protrusion 144 Welding surface 150 Metal wire 160 Metal ball 170 Tape 113 Pad < 1

第12頁Page 12

Claims (1)

六、申請專利範圍 【申請專利範圍】 1、一種BGA之封裝方法，其包含步驟有： t提供一導線架，該導線架係具有複數組引指，每一引 才曰具有一上表面及一下表面，其上表面具有一凸出部， 該凸出部係形成有一焊接面； ° 黏固一晶片於每一組引指之下表面，該晶片係具有一 上表面及一下表面，且晶片之上表面係形成有複數個焊 墊； 電性連接晶片與引指’使得晶片之焊塾電性導通至對 應引指之上表面； 提供一膠帶，該膠帶係黏貼複數組引指凸出部之焊接 面； 形成一熱固性封膠體，該封膠體係覆蓋引指之上表 面； 移除該膠帶，使複數組引指之凸出部之焊接面棵露於 封膠體外；及 形成複數個金屬球於引指凸出部之焊接面上。 2、 如申請專利範圍第1項所述之BGA之封裝方法，其中 「提供一導線架」之步驟中，導線架係以半蝕刻 〔half- etching〕方法形成引指及其上表面之凸出部。 3、 如申請專利範圍第1項所述之BGA之封裝方法，其中 「黏固一晶片於引指之下表面」之步驟中，晶片係以膠 帶黏固於引指之下表面。 4、 如申請專利範圍第1項所述之BGA之封裝方法，其中 Η if6. Scope of patent application [Scope of patent application] 1. A BGA packaging method, which includes the steps: t Provide a lead frame, the lead frame has a plurality of array of fingers, each lead has an upper surface and a bottom The surface has a protruding portion on the upper surface, and the protruding portion forms a welding surface; ° A wafer is fixed on the lower surface of each set of fingers, and the wafer has an upper surface and a lower surface, and A plurality of solder pads are formed on the upper surface; electrically connecting the chip and the fingers, so that the solder pads of the wafer are electrically connected to the upper surface of the corresponding fingers; a tape is provided, and the tape is used to stick the protrusions of the fingers of the complex array. Welding surface; forming a thermosetting sealant, the sealant system covering the upper surface of the fingers; removing the tape, so that the welding surface of the protruding portion of the plurality of fingers is exposed outside the sealant; and forming a plurality of metal balls On the welding surface of the protruding part of the finger. 2. The BGA packaging method described in item 1 of the scope of the patent application, wherein in the step of "providing a lead frame", the lead frame is formed by a half-etching method and the protrusions on the upper surface thereof. unit. 3. The BGA packaging method described in item 1 of the scope of the patent application, wherein in the step of "sticking a chip to the lower surface of the index finger", the chip is fixed to the lower surface of the index finger with an adhesive tape. 4. The BGA packaging method described in item 1 of the scope of patent application, where Η if ^941 六、申請專利範圍 「黏固一晶片於引指之下表面」之步驟中，晶片之焊墊 係形成於晶片上表面之中央部份。 5、如申請專利範圍第1項所述之BGA之封裝方法，其中 電性連接晶片與引指」之步驟中，係以打線方式將金 屬導線連接晶片之焊墊與引指之連接面。 6 申請專利範圍第4項所述之BGA之封裝方法，其中 1成一熱固性封膠體」之步驟中，係將晶片及金屬導 線也、封於封膠體内。 ^申請專利範圍第1項所述之BGA之封裝方法，其中 y成金屬球」之步驟中，金屬球係呈交錯排列。^ 941 6. Scope of patent application In the step of “sticking a wafer to the lower surface of the index finger”, the pads of the wafer are formed in the central part of the upper surface of the wafer. 5. The BGA packaging method as described in item 1 of the scope of the patent application, wherein the step of electrically connecting the chip and the finger is to connect the metal wire to the bonding pad of the chip and the connection surface of the finger by wire bonding. 6 The BGA packaging method described in item 4 of the scope of the patent application, in which the step of “10% into a thermosetting encapsulant” involves encapsulating the wafer and metal wires in the encapsulant. ^ The BGA packaging method described in item 1 of the scope of the patent application, wherein in the step of "y forming a metal ball", the metal balls are staggered. 第14頁Page 14
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