TW495939B - Chip scale package with a small surface mounting area - Google Patents

Chip scale package with a small surface mounting area Download PDF

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Publication number
TW495939B
TW495939B TW090117282A TW90117282A TW495939B TW 495939 B TW495939 B TW 495939B TW 090117282 A TW090117282 A TW 090117282A TW 90117282 A TW90117282 A TW 90117282A TW 495939 B TW495939 B TW 495939B
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TW
Taiwan
Prior art keywords
wafer
chip
pad
package structure
finger
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TW090117282A
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Chinese (zh)
Inventor
Jansen Chiu
Original Assignee
Waltom Advanced Electronics Lt
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Priority to TW090117282A priority Critical patent/TW495939B/en
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Publication of TW495939B publication Critical patent/TW495939B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A chip scale package (CSP) is disclosed. The CSP includes a die with bonding pads on the perimeter of two lateral sides of active surface, a plurality of leads on the die each having first end and second end, a plurality of metal bonding wires connecting the die and the first ends of the leads, and a first sealing layer covering the active surface of the die and the metal bonding wires. Each lead has a protruding portion over the first sealing layer and located between first end and second end for the outer electrical connection. Thus the CSP has a smaller surface mounting area.

Description

495939 五、發明說明（1) 【發明領域】 本發明係有關於一種無外接腳之 〔Chip Scale Package〕，特別係有二^寸封裝結構 於兩側邊之晶片尺寸封裝結構。/、 ； 種晶片焊墊位 【先前技術】 S:知半導體晶片係以一絕緣熱固性樹 〔package body〕密封，用以保護晶 j =體 害，並以導線架〔引指〕作為該半導體封裝 】。且古丨，一種半導體封裝結構 具有小卜 i 封裝〔Thin Small 〇utHne Package TSOP〕型態，其外接腳係在封裝體其中兩側，用以封 晶片11之半導體封裝結構1〇係包含該晶片"、密封 1之/二體12以及一往外電性傳輸之導線架〔lead ja二4 ，曰Η 1 1;線架具有一晶墊16〔…Pad〕及複數個 引扣14，曰曰片11係以銀膠等黏膠13黏固於晶墊16，並以複 數個金屬焊線1 5内部電性連接晶片丨丨之焊墊與引指丨4在封 膠體12内之内端，引指14之外端係往外延伸出封膠體12並 作適當彎折’在引指1 4之外端表面1 4a作為該半導體封裝 結構10與印刷電路板之表面結合端點，然而引指14之外端 表面14a係位於封膠體12之兩側外周邊，其表面結合寬度 Η1係2於擴大，具有較大的表面結合面，不利於高密度表 面結合’也就是說在一固定面積之印刷電路板僅能表面結 合較少量之半導體封裝結構丨〇。 隨著半導體封裝之微小化，美國專利案第6, 1 43, 981 495939 五、發明說明（2) " ------- 號「積體電路之塑膠封裝及其製造方法及其導線架」提出 :，以金屬墊取代外接腳之半導體封裝結構，以減少表面 結合面積〔f00tprint〕，如第2圖所示，一半導體封裝結 構係包含有一半導體晶片21、·一封膠體22、複數個金屬 引指及一金屬晶墊26，其中晶墊26係黏固晶片21，並以 金屬焊線25電性連接晶片21之焊墊與引指24之上表面 24a ’且引指24下表面24b係裸露於封膠體22，作為表面結 合至一印刷電路板之連接點，然而在上述之半導體封裝結 構20中，大面積之晶墊26佔據了 一定之表面積，使得在周 邊之引指24下表面24b仍具有一稍大之表面結合寬度”， 由於晶片21與印刷電路板具有不匹配的熱膨脹應力，若半 導體封裝結構2 〇對印刷電路板之焊接點兩侧間距〔即引指 24下表面24b之兩側間距〕或斜向最大間距過大，將承受 較大的熱應力，可能使得在最外圍的引指24下表面24b焊 接點斷裂，導致電性及機械結合失敗。 【發明目的及概要】 本發明之主要目的在於提供一種縮小表面結合面之晶 片尺寸封裝結構，利用在晶片正面之引指具有一凸起部， 作為電性連接之外端接點且引指承載於晶片上，以取代晶 墊，針對焊墊在兩侧邊之晶片進行構裝為晶片尺寸封裝結 構’達到縮小表面結合面而能高密度結合於印刷電路板。 依本發明之縮小表面結合面之晶片尺寸封裝結構，其 包含： 一晶片，具有一正面，該晶片正面之其中兩侧周邊形495939 V. Description of the Invention (1) [Field of the Invention] The present invention relates to a chip scale package without external pins, and particularly a chip size package structure with a two-inch package structure on both sides. / 、; Kinds of wafer bonding pads [Previous technology] S: It is known that the semiconductor wafer is sealed with an insulating thermosetting tree [package body] to protect the crystal j = body damage, and the lead frame [leading finger] is used as the semiconductor package. 】. Moreover, a semiconductor package structure has a Thin Small Package HSOP Package type. Its external pins are on both sides of the package. The semiconductor package structure 10 used to seal the chip 11 includes the chip. ", sealed 1 / two body 12 and a lead frame for external electrical transmission [lead ja 2 4, said ， 1 1; the wire frame has a crystal pad 16 [... Pad] and a plurality of buckles 14, said The sheet 11 is adhered to the crystal pad 16 with an adhesive 13 such as silver glue, and is electrically connected to the chip 丨 with the plurality of metal bonding wires 15 inside the bonding pads and fingers 丨 4 at the inner end of the sealing body 12, The outer end of the finger 14 extends out of the encapsulant 12 and is appropriately bent. 'The outer surface 14a of the finger 14 is used as the end point of the semiconductor package structure 10 and the surface of the printed circuit board. However, the finger 14 The outer end surface 14a is located on the outer periphery of both sides of the sealant 12, and its surface bonding width Η1 and 2 are enlarged. It has a large surface bonding surface, which is not conducive to high-density surface bonding. The circuit board can only have a small amount of semiconductor packaging structure on the surface.With the miniaturization of semiconductor packages, US Patent No. 6, 1 43, 981 495939 V. Description of the Invention (2) " ------- "Plastic Packaging of Integrated Circuits, Manufacturing Method and Wires thereof "Frame" proposes: replace the external semiconductor package structure with metal pads to reduce the surface bonding area [f00tprint]. As shown in Figure 2, a semiconductor package structure includes a semiconductor wafer 21, a colloid 22, a plurality of Metal fingers and a metal crystal pad 26, wherein the crystal pad 26 is a wafer 21, and a metal bonding wire 25 is used to electrically connect the pad 21 of the wafer 21 with the upper surface 24a of the finger 24 and the lower surface of the finger 24 24b is exposed on the encapsulant 22 as the connection point of the surface bonding to a printed circuit board. However, in the above-mentioned semiconductor package structure 20, the large-area crystal pad 26 occupies a certain surface area, so that the surrounding fingers 24 The surface 24b still has a slightly larger surface bonding width. "Because the wafer 21 and the printed circuit board have a mismatched thermal expansion stress, if the semiconductor package structure 2 〇 the distance between the two sides of the solder joints of the printed circuit board [ie, refers to the following table 24 The distance between the two sides of the surface 24b] or the maximum distance in the oblique direction is too large, which will bear a large thermal stress, which may cause the welding point of the lower surface 24b of the outermost index finger 24 to break, resulting in failure of electrical and mechanical bonding. [Summary] The main object of the present invention is to provide a chip size package structure with a reduced surface bonding surface. The leading finger on the front side of the chip has a protrusion as an external termination point for electrical connection and the leading finger is carried on the chip. Instead of the crystal pad, the wafers on both sides of the solder pad are configured into a wafer-size package structure, which achieves a reduced surface bonding surface and can be bonded to a printed circuit board with high density. The structure includes: a wafer having a front surface, and peripheral edges of two sides of the front surface of the wafer are shaped

495939 五、發明說明（3) 成有複數個焊墊； ，數個引指，位於、晶片·之正面上，具有第一表面及黏 貼曰曰片正面之第二表面，且每_引指具有第一 位於第一表面並在第一端與.第二端之間的凸起部，第 端係朝向對應之晶片焊墊，第二端係延伸至不具焊墊之 一晶片周邊； 、 複數個金屬料，電性連接該晶片之焊塾至對應引指 第一端之第一表面；及 第一封膠層’覆蓋該晶片之正面與金屬焊線，且該封 膠體係至少裸露出該複數個引指凸起部之一表面。 【發明詳細說明】 請參閱所附圖式，本發明將列舉以下之實施例說明： 在本發明之一具體實施例中，第3圖係為一晶片尺寸 封裝結構100之截面圖，第4圖為該晶片尺寸封裝結構1〇() 底面透視圖，第5a至5e圖為該晶片尺寸封裝妹椹〗〇() 封裝」係指封裝結構100之外觀尺寸不大於半導體晶片11〇 之一點三倍，該晶片尺寸封裝結構1〇〇主要包含有一晶片 、第一封膠層120、複數個金屬焊線150及複數個引指 140 〇 晶片 110 係可為DRAM、SRAM、SDRAM、flash、DDR 或 R a m b u s等s己憶體晶片、微處理器、邏輯性〔1 w〇〕或是 RaF射頻之晶片，其材質為矽、砷化鎵或其它半導體材料， 曰曰片11 0係具有一正面j j j及一背面j j 2，而在晶片j ι 〇之正 495939 五、發明說明（4) 面111係習知地形成有複數個焊墊1 1 3〔 bonding pad〕及 積體電路元件〔integrated circuit element〕〔圖未繪 出〕，而複數個焊墊11 3係形成於正面111之兩侧邊緣〔如 第3及4圖所示〕，在本實施例中·，晶片11 0係呈矩形而具 有較寬兩側邊與較窄兩側邊，複數個焊墊11 3係形成於正 面111之較窄兩側邊緣，並在晶片1 1 0之正面以膠帶1 3 〇黏 貼有複數個引指140。495939 V. Description of the invention (3) There are a plurality of solder pads; a plurality of lead fingers are located on the front side of the wafer, and have a first surface and a second surface on the front side of the wafer, and each lead finger has The first protrusion is located on the first surface and between the first end and the second end. The first end is toward the corresponding wafer pad, and the second end extends to the periphery of one of the wafers without the pad; Metal material, electrically connecting the solder pads of the chip to the first surface of the corresponding leading end; and a first sealant layer 'covering the front side of the chip and the metal bonding wire, and the sealant system at least exposes the plurality One finger refers to a surface of the protrusion. [Detailed description of the invention] Please refer to the attached drawings. The present invention will enumerate the following embodiments: In a specific embodiment of the present invention, FIG. 3 is a cross-sectional view of a chip-size package structure 100, and FIG. 4 10 () is a perspective view of the bottom surface of the chip size package structure, and FIGS. 5a to 5e are the chip size package structure. (0) (package) means the appearance size of the package structure 100 is not greater than one-third of the semiconductor wafer 110. Times, the chip size package structure 100 mainly includes a chip, a first sealing layer 120, a plurality of metal bonding wires 150, and a plurality of index fingers 140. The chip 110 can be DRAM, SRAM, SDRAM, flash, DDR or Rambus and other memory chips, microprocessors, logic [1 w0] or RaF radio frequency chips, whose material is silicon, gallium arsenide or other semiconductor materials, said that the film 110 is a front side jjj And a back surface jj 2 and the positive 495939 of the wafer j 〇 Ⅴ. Description of the invention (4) The surface 111 is conventionally formed with a plurality of bonding pads 1 1 3 [bonding pad] and integrated circuit elements [integrated circuit element ] [Figure not drawn], A plurality of bonding pads 11 3 are formed on both sides of the front surface 111 (as shown in FIGS. 3 and 4). In this embodiment, the wafer 110 is rectangular and has wide sides and narrow sides. On the side, a plurality of bonding pads 11 3 are formed on the narrower sides of the front surface 111, and a plurality of fingers 140 are pasted on the front surface of the wafer 1 10 with an adhesive tape 13.

複數個引指1 4 0係取自於同一導線架，如第3圖所示， 每一引指140具有第一表面141及一對應之第二表面丨42， 其中第二表面142係以膠帶130黏貼於晶片11〇之正面丨n， 較佳地第二表面1 4 2係為一實質之水平面，此外，如第4圖 所示，引指140另包含第一端143與第二端144，第一端143 係為引指1 4 0往晶片11 0之具焊墊11 3側邊之一延伸端，以 連接金屬焊線1 5 0，利用金屬焊線1 5 〇電性連接該晶片丨J 〇 之焊墊113至對應引指140第一端143之第一表面141，第二 端144係為引指140往晶片110之不具焊墊113侧邊之另一延 伸端，以銜接至一未切割前之導線架，引指14〇第一表面 141具有一凸起部145，凸起部145位在第一端丨43與第二端The plurality of fingers 1 40 are taken from the same lead frame. As shown in FIG. 3, each finger 140 has a first surface 141 and a corresponding second surface 42, wherein the second surface 142 is tape 130 is adhered to the front side of the wafer 110, preferably the second surface 1 42 is a substantially horizontal plane. In addition, as shown in FIG. 4, the index finger 140 further includes a first end 143 and a second end 144. The first end 143 is an extending end of the leading finger 1 40 to one of the sides of the chip 11 0 with the bonding pad 11 3 to connect the metal bonding wire 150 and the metal bonding wire 150 to electrically connect the chip.丨 J 〇 pad 113 to the first surface 141 corresponding to the first end 143 of the index finger 140, the second end 144 is another extension end of the index finger 140 to the side of the wafer 110 without the solder pad 113 to connect to An uncut lead frame, the index finger 140. The first surface 141 has a protrusion 145, and the protrusion 145 is located at the first end 43 and the second end.

144之間並具有至少一未被第一封膠層12〇覆蓋之表面，竹 為該晶片尺寸封裝結構100之外部電性連接點，或可在該 凸起部1 45接植有鉛錫合金之焊球〔圖未繪出〕，如第3圖 所示，兩側之凸起部145係具有較短之表面結合寬度H3， 以縮小表面結合面。 第 一封膠層1 2 0係位於晶片11 〇之正 面111，用以保護 495939 五、發明說明（5) 晶片11 0免於濕氣、塵埃之侵蝕，其為一種熱固性絕緣 材，如環氧樹脂，以壓、模〔mo 1 d i ng〕或印刷 〔pr i nt i ng〕等技術塗施並烘烤固化成形，其覆蓋晶片 110之正面111與金屬焊線150，且該第一封膠層120係至少 裸露出該複數個引指1 4 0凸起部1 4 5之一表面，在本實施例 中，該晶片尺寸封裝結構100另包含有第二封膠層16〇，位 在晶片1 1 0之背面11 2，以增進對晶片11 〇之保護。 因此’在上述晶片尺寸封裝結構1 〇 〇中，係利用内部 延伸之引指1 40取代習知金屬晶墊，引指1 40不但可承載晶 片110並能形成内縮之表面接點〔第一表面141之凸起部 145〕’當表面結合於一印刷電路板時，裸露之凸起部ία 表面可使多個晶片尺寸封裝結構1 〇 〇密集結合於印刷電路 板，此外，由於晶片尺寸封裝結構丨00具有較為内縮的表 面結合端點，故表面結合端點承受較少的熱應力，不會因 為晶片11 0與印刷電路板之間的熱膨脹係數不匹配而導 不當斷裂。 此外’上述之晶片尺寸封裝結構丨〇 〇除了能以一般 線架封裝製程製備之外，亦能以晶圓級封裝方法〔wa^r level packaging〕據以實施，首先，如第。圖所示提 供一晶圓，其包含有複數個未切割之晶片丨丨〇，每一晶 110具有一正面111及一背面112，該晶片正面lu之其曰曰 側周邊形成有複數個焊墊113 ;接著，如第旰圖、/ 膠帶13〇黏貼一導線架至晶圓’該導線架具 = “〇’每-引指"。具有第一表面141及黏貼晶；；=曰之 495939 五、發明說明（6) 第二表面142，且每一引指140具有第一端143、第二端144 以及位於第一表面141並在第一端143與第二端144之間的 凸起部145，第一端143係朝向對應之焊墊113，第二端144 係延伸至晶片11 0不具焊墊之一周邊；之後，如第5c圖所 示’打線形成金屬焊線150，其電性連接該晶片11〇之焊墊 113至對應引指140第一端143之第一表面141 ;之後，如第 5d圖所示，形成第一封膠層12〇於晶圓上，第一封膠層ι2〇 係覆蓋晶片110之正面111與金屬焊線15〇，且該第一封膠 層1 2 0係至少裸露出該複數個引指1 4 〇凸起部1 4 5之一表 面；如有需要，如第5e圖所示，將晶圓翻轉，形成第二封 膠層1 60於晶圓上，以覆蓋晶片丨丨〇之背面丨丨2 ;如有需 要，可在引指1 4 0凸起部1 4 5接植焊球，以利表面結合；最 後，切割該晶圓，以形成如第3圖所示之晶片尺寸封裝結 構 1 0 0。 、、° 故本發明之保護範圍當視後附之申請專利範圍所界 者為準，任何熟知此項技藝者，在不脫離本發明之 當圍内所作之任何變化與修改，均屬於本發明之保護範 495939 圖式簡單說明 【圖式說明】 第1 圖··習知TSOP半導體封裝結構之截面圖； 第2 圖：美國專利第6, 143, 981號「積體電路之塑膠封裝 及其製造方法及其導線架」之半導體封裝結構 載面圖； 第3圖：依本發明之一具體實施例，一晶片尺寸封裝結 構之截面圖； 第4圖：依本發明之第一具體實施例，該晶片尺寸封裝 結構之底面透視圖； 第h圖：依本發明之第—具體實施例，在製造該晶片尺 ^ •寸封裝結構之方法中所提供晶圓之截面圖； 圖·依本發明之第一具體實施例，在製造該晶片尺 园·寸封裝結構之方法中所黏貼導線架之截面圖； 依本發明之第一具體實施例，在製造該晶片尺 寸封敦結構之方法中所打線形成金屬焊線之戴 面圖； 依本發明之第一具體實施例，在製造該晶片尺 寸封裝結構之方法中所形成第一封膠層之戴面 圖；及 =本發明之第一具體實施例，在製造該晶片尺 、封裝結構之方法中所形成第二封膠層之截面 圖。 【圖號說明】 10半導體封裝結構 495939 圖式簡單說明 11 晶片 12 封 膠 體 13 黏 膠 14 引指 14a、 外 端 表 面 15 金 屬 焊 線 16 晶塾 20 半導 體 封 裝 結； 構 - 21 晶片 22 封 膠 體 24 引指 24a 上 表 面 24b 下 表 面 25 金屬 焊 線 26 晶 墊 100 晶片 尺 寸 封 裝 結構 110 晶片 111 正面 112 背 面 113 焊 墊 120 第一 封 膠 層 130 膠 帶 140 引指 141 第 一 表 面 142 第 二 表 面 143 第一 端 144 第 二 端 145 凸 起 部 150 金屬 焊 線 160 第 二 封 膠層 HI 表面 結 合 寬 度 H2 表面 結 合 寬 度 H3 表面 結 合 寬 度 b·. Η 第12頁Between 144 and at least one surface that is not covered by the first sealant layer 120, bamboo is the external electrical connection point of the chip size package structure 100, or a lead-tin alloy can be implanted at the convex portion 1 45 In the solder ball (not shown), as shown in FIG. 3, the convex portions 145 on both sides have a shorter surface bonding width H3 to reduce the surface bonding surface. The first adhesive layer 1 2 0 is located on the front side 111 of the wafer 11 0 to protect 495939. 5. Description of the invention (5) The wafer 110 is protected from moisture and dust. It is a thermosetting insulating material such as epoxy. The resin is applied and baked and cured by techniques such as pressing, mold [mo 1 di ng], or printing [pr i nt i ng], which covers the front surface 111 of the wafer 110 and the metal bonding wire 150, and the first sealant The layer 120 exposes at least one surface of the plurality of leading fingers 140 convex portions 145. In this embodiment, the chip-size package structure 100 further includes a second sealant layer 16 located on the wafer. The back surface of 11 is 11 2 to improve the protection of the wafer 11. Therefore, in the above-mentioned wafer size package structure 1000, the conventional metal crystal pad is replaced by the internally extended finger 1 40. The finger 1 40 can not only carry the wafer 110 but also form a contracted surface contact [the first The raised portion 145 of the surface 141] 'When the surface is bonded to a printed circuit board, the exposed raised portion αα surface enables multiple wafer size packaging structures 100 to be densely bonded to the printed circuit board. In addition, since the wafer size package Structure 丨 00 has a relatively narrow surface bonding end point, so the surface bonding end point bears less thermal stress, and will not be improperly broken due to the mismatch of the thermal expansion coefficient between the wafer 110 and the printed circuit board. In addition, the above-mentioned chip size packaging structure 丨 〇 〇 In addition to being able to be prepared by a general wireframe packaging process, it can also be implemented by a wafer level packaging method [wa ^ r level packaging], first, as described above. The figure provides a wafer that includes a plurality of uncut wafers. Each wafer 110 has a front surface 111 and a back surface 112. A plurality of bonding pads are formed on the periphery of the front side of the wafer. 113; Next, as shown in the second figure, / adhesive tape 13〇 paste a lead frame to the wafer 'the lead frame = "〇'each-quote". It has a first surface 141 and an adhesive crystal; 5. Description of the invention (6) The second surface 142, and each index finger 140 has a first end 143, a second end 144, and a protrusion located on the first surface 141 and between the first end 143 and the second end 144 Part 145, the first end 143 is directed to the corresponding solder pad 113, and the second end 144 is extended to the periphery of the wafer 110 without one of the solder pads; after that, as shown in FIG. The solder pad 113 of the wafer 11 is connected to the first surface 141 of the first end 143 of the corresponding finger 140; after that, as shown in FIG. 5d, a first sealant layer 12 is formed on the wafer, and the first seal The adhesive layer ι20 covers the front surface 111 of the wafer 110 and the metal bonding wire 150, and the first sealing layer 12 is exposed at least in the plurality. Refer to one of the surfaces of the raised portion 14 5; if necessary, as shown in FIG. 5e, turn the wafer over to form a second sealant layer 160 on the wafer to cover the wafer. Back surface 丨 丨 2; if necessary, solder balls can be connected to the leading finger 1 40 convex portion 1 4 5 to facilitate surface bonding; finally, the wafer is cut to form a wafer as shown in Figure 3 Dimensional package structure 100 °,. ° Therefore, the protection scope of the present invention shall be subject to the scope of the appended patent application scope. Any person skilled in the art will make any changes without departing from the scope of the present invention. All modifications and modifications belong to the protection scope of the present invention. 495939 Brief description of the drawings [Illustration of the drawings] Figure 1 · Sectional view of the conventional TSOP semiconductor package structure; Figure 2: US Patent No. 6, 143, 981 "Semiconductor package structure cross-sectional view of a plastic package of a bulk circuit and its manufacturing method and lead frame"; Figure 3: A cross-sectional view of a chip-size package structure according to a specific embodiment of the present invention; Figure 4: According to this In a first specific embodiment of the invention, the bottom surface of the chip-size package structure is transparent Figure h: a cross-sectional view of a wafer provided in a method for manufacturing the wafer size package structure according to the first embodiment of the present invention; A cross-sectional view of a lead frame pasted in a method for manufacturing the wafer scale-inch package structure; according to a first embodiment of the present invention, a wire bonding wire is used to form a wearing surface of a metal bonding wire according to a first embodiment of the present invention. Figure; a wearing view of a first sealant layer formed in a method of manufacturing the chip-size package structure according to a first specific embodiment of the present invention; and = a first specific embodiment of the present invention in manufacturing the wafer ruler 2. A cross-sectional view of the second sealant layer formed in the method of packaging structure. [Illustration of drawing number] 10Semiconductor package structure 495939 Brief description of the diagram 11 Wafer 12 Sealant 13 Adhesive 14 Finger 14a, Outer surface 15 Metal wire 16 Crystal 20 Semiconductor package junction; Structure-21 Chip 22 Sealant 24 Leader 24a upper surface 24b lower surface 25 metal bonding wire 26 die pad 100 chip size package structure 110 die 111 front 112 back 113 solder pad 120 first adhesive layer 130 tape 140 finger 141 first surface 142 second surface 143 first One end 144 Second end 145 Bump 150 Metal bonding wire 160 Second sealant layer HI Surface bonding width H2 Surface bonding width H3 Surface bonding width b ·. 页 page 12

Claims (1)

【申請專利範圍】 1、一種晶片尺寸封裝結構，其包含有： 曰曰片，具有一正面，該晶片正面之其中兩側周邊形 成有複數個焊墊； 複數個引指，位於晶片之正面上，具有第一表 ”片正面之第二表面，且每一引指具有第一 J面= 端以及位於第一表面且在第一端與第二端之間的凸起 部’第一端係朝向對應之晶片焊墊，第二端係延 具焊墊之一晶片周邊； 不 複數個金屬焊線，電性連接該晶片之焊墊至對鹿 第一端之第一表面；及 〜指 第一封膠層，覆蓋該晶片之正面與金屬焊線，且兮 一封膠層係至少裸露出該複數個引指凸起部之一表'^第 、如申請專利範圍第1項所述之晶片尺寸封裝結構面。 另包含第二封膠層，其覆蓋晶片之背面。 Q ’其 、如申請專利範圍第1項所述之晶片尺寸封裝結構， 中在引指第二表面與晶片正面之間係黏固有膠帶。其 、一種晶片尺寸封裝結構之晶圓級封裝方法，1 驟有： *包含步 提供一晶圓 片具有一正面 個焊墊； ，其 ，該 包含有複數個未切割之晶片 晶片正面之其中兩側周邊形 ，每—晶 成有複數 ，每 且 黏貼一導線架至晶圓，該導線架具有複數個引於 一引指具有第一表面及黏貼晶片正面之第二表面曰 495939 (时月心 第jtJ 案號 90117282 Λ_η 曰 修正 六、申請專利範圍 一引指具有第一端、第二端以及位於第一表面且在第一 端與第二端之間的凸起部，第一端係朝向對應之焊墊， 第二端係延伸至晶片不具焊墊之一周邊； 打線形成金屬焊線，其電性連接該晶片之焊墊至對應 引指第一端之第一表面； 形成第一封膠層於晶圓上’第一封膠層係覆盍該晶片 之正面與金屬焊線，且該第一封膠層係至少裸露出該複 數個引指凸起部之一表面；及 切割該晶圓。 5、如申請專利範圍第4 項所述之晶片尺寸封裝結構之晶 圓級封裝方法，其在切割該晶圓之前，形成第二封膠層 於晶圓上，以覆蓋該晶片之背面。[Scope of patent application] 1. A chip-size package structure comprising: a chip having a front surface, a plurality of pads formed on the periphery of both sides of the front surface of the chip; a plurality of index fingers on the front surface of the chip Has a second surface on the front side of the first watch sheet, and each index finger has a first J-plane = end and a raised portion 'first end system located on the first surface between the first end and the second end' Toward the corresponding wafer pad, the second end is the periphery of one of the wafers; the plurality of metal bonding wires are electrically connected to the wafer's pad to the first surface of the first end of the deer; and ~ refers to the first An adhesive layer covers the front surface of the wafer and the metal bonding wires, and at least one of the plurality of finger-pointing protrusions is exposed on the adhesive layer, as described in item 1 of the scope of patent application. The surface of the chip size package structure. It also contains a second sealant layer that covers the back of the wafer. Q 'The chip size package structure described in item 1 of the patent application range refers to the second surface and the front side of the chip. Inherent adhesive tape. A wafer-level packaging method for a wafer-size packaging structure includes the following steps: * Including the step of providing a wafer with a pad on the front side; which includes a plurality of uncut wafers on the front side of the wafer. There is a plurality of each crystal, each of which has a lead frame pasted to the wafer, and the lead frame has a plurality of second surfaces led to a finger with a first surface and a front surface of the pasted wafer, said 495939 (Shiyuexin JtJ case) No. 90117282 Λ_η Revision VI. Patent application scope 1 refers to a first end, a second end, and a convex portion located on the first surface between the first end and the second end. The first end faces the corresponding weld. The second end of the pad extends to the periphery of the wafer without a pad; a wire is formed to form a metal bonding wire that electrically connects the pad of the wafer to a first surface corresponding to the first end of the index finger; forming a first sealant layer on A 'first sealant layer on the wafer covers the front surface of the wafer and a metal bonding wire, and the first sealant layer exposes at least one surface of the plurality of index protrusions; and cuts the wafer. 5, as applied Item 4. The wafer of patentable scope round grain size level packaging method of a package structure, in which the wafer before dicing, a second encapsulation layer is formed on the wafer to cover the backside of the wafer. 第14頁 2002.05.17.014Page 14 2002.05.17.014
TW090117282A 2001-07-12 2001-07-12 Chip scale package with a small surface mounting area TW495939B (en)

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TW090117282A TW495939B (en) 2001-07-12 2001-07-12 Chip scale package with a small surface mounting area

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