TW493224B - Composite doped channel heterostructure field-effect transistor - Google Patents
Composite doped channel heterostructure field-effect transistor Download PDFInfo
- Publication number
- TW493224B TW493224B TW90126084A TW90126084A TW493224B TW 493224 B TW493224 B TW 493224B TW 90126084 A TW90126084 A TW 90126084A TW 90126084 A TW90126084 A TW 90126084A TW 493224 B TW493224 B TW 493224B
- Authority
- TW
- Taiwan
- Prior art keywords
- item
- scope
- layer
- transistor
- patent application
- Prior art date
Links
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
493224 五、發明說明(1) 發明領域 本發明係有關一種複合式摻雜通道異質結構場效電晶 體’其在高溫環境下依然可保有良好之元件特性。 發明背景 由於砷化銦鎵(InGaAs)材料具有較低的有效質量、較 问的移動率及飽和速度等優點,因此為了得到更佳的元件 致能,以砷化鎵(GaAs)為基板之異質結構場效電晶體中, 利用砷化銦鎵(InGaAs)取代砷化鎵(GaAs)作為通道材料已 經成為一種趨勢。然而由於砷化銦鎵(InGaAs)材料的能隙 較小,在高電場下會產生撞擊游離效應,使元件特性包括 漏電流、崩潰電壓、輸出電導、電壓增益及溫度表現等會 呈現劣化之現象。 本案發明人與其共事者於我國專利公報公告第452978 戒專利案揭示一可耐高溫操作之高崩潰電壓異質結構場效 電晶體,包含一半導體基板;一位於該基板表面之緩衝 層,一位於這緩衝層上之單原子摻雜層;一位於該單原子 摻雜層上之未摻雜層;一位於該未摻雜層上之次通道層; 位於該次通道層上之主通道層;一位於該主通道層上之 閘極層;一位於該閘極層上之歐姆接觸層。 發明要旨 本發明的主要目的為提出一種不具有上述先前技藝的 缺點的複合式摻雜通道異質結構場效電晶體。 s493224 V. Description of the invention (1) Field of the invention The present invention relates to a composite doped channel heterostructure field-effect electric crystal 'which can still maintain good element characteristics in a high temperature environment. BACKGROUND OF THE INVENTION Because indium gallium arsenide (InGaAs) materials have the advantages of lower effective mass, relatively high mobility and saturation speed, etc., in order to obtain better device enablement, gallium arsenide (GaAs) is used as substrate heterogeneity In the structure field effect transistor, it has become a trend to use indium gallium arsenide (InGaAs) instead of gallium arsenide (GaAs) as a channel material. However, due to the small energy gap of indium gallium arsenide (InGaAs) materials, impact ionization effects will occur under high electric fields, which will cause degradation of device characteristics including leakage current, breakdown voltage, output conductance, voltage gain, and temperature performance. . The inventor of this case and his collaborators disclosed in Chinese Patent Gazette Bulletin No. 452978 or Patent Case that a high breakdown voltage heterostructure field effect transistor capable of withstanding high temperature operation, including a semiconductor substrate; a buffer layer on the substrate surface, A single-atom doped layer on the buffer layer; an undoped layer on the single-atom doped layer; a secondary channel layer on the undoped layer; a primary channel layer on the secondary channel layer; A gate layer on the main channel layer; an ohmic contact layer on the gate layer. SUMMARY OF THE INVENTION The main object of the present invention is to provide a field effect transistor of a composite doped channel heterostructure without the disadvantages of the foregoing prior art. s
493224 五、發明說明(2) ' ' ~------、 一種依本發明所完成的複合式摻雜 電晶體,包含: 、"貝、、口構%致 一半導體基板; 一位於該基板表面之緩衝層—】; 一位於該緩衝層—1上之緩衝層-2 ; 一位於泫緩衝層—2上之摻雜通道層—1 ; 一位於該摻雜通道層—1上之摻雜通道層—2 ; 一位於該摻雜通道層—2上之簫特基接觸層; 位於忒蕭特基接觸層上之歐姆接, 基接觸層的—部份曝露出於該歐姆接觸層 亥肅特 一位於該歐姆接觸層上之汲極及源^;及 一位於該蕭特基接觸層的曝露 明的電晶體中,該基板』; /、 耗圍"於〇·1〜的厚度·兮螇庵9屯土仏、 之磷化銦鎵(InG49GaG,lP),1呈右緩衝層—2為未摻雜 的;^痄·# r ·ΰ1 其具有一乾圍介於200〜50 0 0埃 的厗度,该緩衝層-2亦可為未摻雜 、 其厚度範圍為20 0〜5 0 0 0埃,而草χ八玄,、·豕lxGai_xAs), 〇·2〜1·0 ;該緩衝層—2亦可為之變化範圍為 ΓΛ1 τ ^ 力J為未摻雜磷化銦鋁 ul〇.5lnG 5P) ’其厚度範圍為2 係坤化鎵(GaAs),其具有厚二5二°;矢’伽通道層-1 ^η=1χ10π.6χ1〇1δ cm-3^n^;®f50'300 ^ ^ 層一2係摻雜砷化銦鎵(InGa (d〇pant),該摻雜通道 3〇〜3〇〇埃,莫耳分率X之其具有厚度範圍為 季已圍為0.05〜0·3,濃度範圍493224 V. Description of the invention (2) '' ~ ------, A composite doped transistor completed in accordance with the present invention, including: " shell, silicon, and semiconductor structure; a semiconductor substrate; A buffer layer on the surface of the substrate—]; a buffer layer-2 on the buffer layer-1; a doped channel layer-1 on the rhenium buffer layer-2; and a buffer layer-2 on the doped channel layer-1 A doped channel layer-2; a photky contact layer on the doped channel layer-2; an ohmic contact on the schottky contact layer; a portion of the base contact layer is exposed to the ohmic contact layer He Suite a drain and source located on the ohmic contact layer; and an exposed transistor located on the Schottky contact layer, the substrate "; Thickness: 9 仏, 仏, 铟, 铟 (InG49GaG, 1P), 1 is the right buffer layer-2 is undoped; ^ 痄 · # r · ΰ1 It has a dry range between 200 ~ 50 With a degree of 0 angstrom, the buffer layer -2 may also be undoped, and its thickness ranges from 200 to 500 angstroms, while Cao X Baxuan, · 豕 lxGai_xAs), 〇 · 2 ~ 1 · 0 The buffer layer-2 can also have a variation range of ΓΛ1 τ ^ force J is undoped indium aluminum phosphide ul 0.55G 5P) 'its thickness range is 2 series gallium (GaAs), which has a thickness of two 52 °; γ ′ channel channel-1 ^ η = 1χ10π.6χ1〇1δ cm-3 ^ n ^; f50'300 ^ ^ Layer 1-2 series doped indium gallium arsenide (InGa (d〇pant), The doped channel has a thickness of 30 to 300 angstroms and a Mohr fraction X of which the thickness ranges from 0.05 to 0.3 in the quarter and the concentration ranges
493224 __90126084 年月日 修正 五、發明說明(3) 在n = lXl〇17〜βχι〇ΐ8 (:{11-3的11型摻雜(dopant);該蕭特基接 觸層係未摻雜磷化銦,其具有厚度範圍為 100〜1 0 0 0埃;該蕭特基接觸層亦可為未摻雜砷化鎵链 (AlxGai_xAs),其具有厚度範圍為1〇0〜1 0 0 0埃,莫耳分率χ 之變化範圍為〇· 2〜1· 0 ·,該蕭特基接觸層亦可為未摻雜τ石粦 化鋼紹(Ai^In。/)材料形成,其厚度範圍為1〇〇〜1〇〇〇埃; 該歐姆接觸層係摻雜砷化鎵(GaAs),其具有一範圍介於 2 0 0〜5 0 0 0埃的厚度,及-·濃度範圍為n=l X low〜1 X 1〇i9 cm-3的η型摻雜。 一選一地(Alternatively),於本發明的電晶體中, 該基板為半絕緣型之磷化銦(InP);該緩衝層-;1係未摻雜 之磷化錮(InP),其厚度範圍為〇.p5 〇#m ;該缓衝層一2493224 __90126084 Rev. 5th, the description of the invention (3) at n = lX1017 ~ βχι〇ΐ8 (: 11 type dopant of {11-3; the Schottky contact layer is undoped with phosphating Indium, which has a thickness ranging from 100 to 100 angstroms; the Schottky contact layer may also be undoped gallium arsenide chain (AlxGai_xAs), which has a thickness ranging from 100 to 100 angstroms, The variation range of the Mohr fraction χ is from 0.2 to 1.0. The Schottky contact layer can also be formed of an undoped τ stone-chemical steel (Ai ^ In. /) Material, and its thickness range is 100 ~ 100 Angstroms; the ohmic contact layer is doped with gallium arsenide (GaAs), which has a thickness ranging from 200 to 500 Angstroms, and the concentration range is n = l X low ~ 1 X 1〇i9 cm-3 n-type doping. Alternatively, in the transistor of the present invention, the substrate is a semi-insulating indium phosphide (InP); the buffer Layer-; 1 is undoped hafnium phosphide (InP), the thickness of which is in the range of 0. p5 0 # m; the buffer layer 2
Jtn未爻=之坤化銦銘Ul°.48ln°.52As),其具有厚度範圍為 ^〇〇〜〇000埃;該緩衝層—2亦可為未摻雜之銻砷化錮鋁 ^l^IrVxASySlVy),其具有厚度範圍為2〇〇5〇〇〇埃,而莫耳 S::x®之1'化耗圍為0.3 0.6,y之變化範圍為0.7〜hO ;該 S i; I㈣Ϊ碟化銦(InP)材料形成,其具有厚度範圍 嘹.二畜:S '辰度乾圍在n=1 Xl〇17〜6 Xl〇1S cnr3的n型摻 亦’…k這a - 2係摻雜砷化銦銨(j A s ),苴且有严 度範圍為30〜300埃,濃产r円—〇.53Ga0.47As),、,、有厗 型摻雜;該通道層圍在n=1X1(F〜6X1018…細 形成,其具有厚度4:3為〇 =坤化錮鎵⑽一)材料 圍為〇.3].〇,濃度範圍1〇〜5〇埃,莫耳分率X之變化範 雜·兮蓊牲I 在η —1 χ 1 〇17〜6 X 1 018 cnr3的η型摻 ^ ❹特基接觸層係未摻料化銦mw%52As,具有Jtn Un == Kunhua Indium Ming Ul ° .48ln ° .52As), which has a thickness in the range of ^ 00 ~ 〇000 angstroms; the buffer layer-2 may also be undoped antimony arsenide aluminum ^ IrVxASySlVy), which has a thickness in the range of 50000 Angstroms, and the Mo's S :: x®'s 1 'consumption range is 0.3 0.6, and the range of y is 0.7 ~ hO; the S i; I i Dish indium (InP) material is formed, which has a thickness range of 畜. Two animals: S 'Chendu dry around n = 1 Xl〇17 ~ 6 Xl〇1S cnr3 n-type doped also' ... kthis a-2 series Doped with indium ammonium arsenide (j A s), rhenium with a severity range of 30 to 300 angstroms, and concentrated production of r 円 —0.53 Ga 0.47 As), with, and erbium-type doping; the channel layer is surrounded by n = 1X1 (F ~ 6X1018 ... finely formed, which has a thickness of 4: 3 is 〇 = Kunhua 锢 Gallium Ⅰ) Material circumference is 0.3]. 〇, the concentration range is 10 ~ 50 Angstroms, Molar fraction Variation of X. Miscellaneous I I n-type doped at η -1 χ 1 〇17 ~ 6 X 1 018 cnr3 ^ Tecki contact layer is not doped with indium mw% 52As, with
493224 五、發明說明(4) " --*一· 厚度範圍為100〜1 0 0 0埃;該蕭特基接觸層亦可為未摻雜銻 2化,鋁(AlxIUSySbh),其具有厚度範圍為1〇〇〜1〇〇〇 矢莫耳分率X之變化範圍為〇·3〜〇·6,y之變化範圍為 〇·7〜1·〇 ;該歐姆接觸層係摻雜砷化銦鎵(InQ53GaG47As), 其具有厚度範圍為2〇〇〜500 0埃,濃度範圍為η=1 χ1〇18〜1 X 1019 cnr3的n型摻雜。 車父佳地’該閘極金屬為金(Au )、鋁(A1)、鈦(T i )、銦 U〇)、鉑(Pt)或其合金,更佳地為金(Au)。該汲極及源極 較佳地為金-鍺-鎳(Au/Ge/Ni)金屬。 於本發明的一較佳具體實施例中,本發明元件具有以 下之特點: (1 )採兩n+一 1 n〇.2GaG 8As/n-GaAs複合式摻雜通道結 ^ 利用^減神化銦鎵(InQ 2GaQ 8As)層的厚度以形成通道 量f =效應,這可以增加砷化銦鎵(InG.2GaQ 8As)通道層的 有^能隙’而砷化鎵(GaAs)層則可以增進元件在高電場下 之#作能力’因此可避免撞擊游離現象的產生,而漏電流 也可因此降低; (2)利用大能隙之磷化銦鎵(InQ 51p)材料作為蕭 1基接觸層及緩衝層;上方之磷化銦鎵(InG49GaG5iP)層可 提供凡件良好之蕭特基特性;下方之磷化銦鎵 (Inu9GaG 51p)層可抑制從基板漏失之基板漏電流,使元件 具有良好的炎止特性; (曾3) In0.49Ga0 51P/ln() 2Ga〇、In〇 49Ga〇 5iP/GaAs 界面間 大的導電帶不連續度(△&)可以有效的將載子侷限在複合493224 V. Description of the invention (4) "-* 1. The thickness ranges from 100 to 100 Angstroms; the Schottky contact layer may also be undoped antimony dioxide, aluminum (AlxIUSySbh), which has a thickness The range is 100 ~ 1000. The variation range of the mol fraction X is 0.3 ~ 0.6. The range of y is 0.7 ~ 1.0. The ohmic contact layer is doped with arsenide. Indium gallium (InQ53GaG47As) has an n-type doping with a thickness ranging from 2000 to 5000 angstroms and a concentration ranging from η = 1 × 1018 to 1 × 1019 cnr3. Chaya Jiadi 'The gate metal is gold (Au), aluminum (A1), titanium (Ti), indium U0), platinum (Pt), or an alloy thereof, and more preferably gold (Au). The drain and source electrodes are preferably gold-germanium-nickel (Au / Ge / Ni) metal. In a preferred embodiment of the present invention, the device of the present invention has the following characteristics: (1) Two n + 1 1 n0.2. GaGa 8As / n-GaAs composite doped channel junctions are used. (InQ 2GaQ 8As) layer thickness to form the channel amount f = effect, which can increase the energy gap of the InG.2GaQ 8As channel layer, while the GaAs layer can increase the The "working ability" under high electric field can avoid the occurrence of impact ionization, and the leakage current can be reduced accordingly; (2) the use of a large energy gap indium gallium phosphide (InQ 51p) material as the Xiao 1 base contact layer and buffer Layer; the upper InG49GaG5iP layer can provide good Schottky characteristics; the lower InGa9P layer (Inu9GaG 51p) layer can suppress the substrate leakage current from the substrate, so that the device has a good inflammation (Zeng 3) In0.49Ga0 51P / ln () 2Ga〇, In〇49Ga〇5iP / GaAs The large discontinuity of the conduction band between the interface (△ &) can effectively limit the carrier to the compound
493224493224
可保 内’因此即使在高溫環境下本發明元件依 有良好之元件特性。 τ m 本發明之複合式摻雜通道異質結構場效 但具有低漏電流、胃崩潰電壓、低 電二不 現外,其對溫度的表現二 急^: d!: ΐ線、】此本發明元件對應用在國内現今 :展之楗波及無線通訊系統方面具有很大的潛 轳兴吏i發明之特點及技術内容能被明顯地了解,下文 心舉一較佳具體實施例,並配合所附圖式作詳細說明了文 較佳具體實施例之詳細說明 …芩考圖一,其為依本發明之一較佳具體實施例所 之複合式#雜通道異質結構場效電晶體丨〇,包么由 依次為一半絕緣型之砷化鎵(GaAs)基板—12 ;厚°〇 5 未摻雜之砷化鎵(GaAs)緩衝層-14 ;厚5〇〇埃,未摻雜 化鋼録(InG.49Ga().51P)層-16 ;厚 15〇 埃,濃度n=r5><1〇17 之砷化鎵(GaAs)通道層_18 ;厚50埃,濃度η+ = 4χ1〇18 cm_3 之砷化銦鎵(InuGauAs)通道層—2〇 ;厚30 0埃,未摻雜之 碟化姻鎵(In。“Gao S1P)蕭特基接觸層—22 ;及厚5〇〇埃,濃 度n+MxlfPcnr3之砷化鎵歐姆接觸層-24 ;然後為兩金—鍺 -鎳(Au/Ge/Ni)金屬-26及-28蒸鍍於砷化鎵歐姆接觸層—24 之上,及金(Au)金屬-30蒸鍍於磷化銦鎵(InQ49GauiP)蕭特 基接觸層-2 2之上,分別用以做為源極(g 〇 u r c e )、汲極 (Drain)及閘極(Gate)之電極。It is guaranteed that the element of the present invention has good element characteristics even under a high temperature environment. τ m The composite doped channel heterostructure field effect of the present invention has low leakage current, gastric breakdown voltage, and low electricity, and its performance on temperature is urgent. ^: d !: ΐ line,] this invention The components are widely used in China today: exhibitions and wireless communication systems have great potential. The characteristics and technical contents of the invention can be clearly understood. The following will give a preferred specific embodiment and cooperate with the The drawings are used to explain the detailed description of the preferred embodiment in detail ... Consider Figure 1, which is a composite #heterochannel heterostructure field effect transistor according to a preferred embodiment of the present invention. It consists of a semi-insulating gallium arsenide (GaAs) substrate—12; thick ° 05; undoped gallium arsenide (GaAs) buffer layer-14; 500 angstroms thick; undoped steel (InG.49Ga (). 51P) layer-16; 15 angstroms thick, concentration n = r5> < 1017 gallium arsenide (GaAs) channel layer_18; 50 angstroms thick, concentration η + = 4χ1. 18 cm_3 InuGauAs channel layer—20; thickness 300 Angstroms, undoped disc-formed gallium (In. “Gao S1P) Schottky contact layer—22 ; And a gallium arsenide ohmic contact layer -24 with a thickness of 500 angstroms and a concentration of n + MxlfPcnr3; and then two gold-germanium-nickel (Au / Ge / Ni) metals -26 and -28 were deposited on the gallium arsenide ohm The contact layer -24 and the gold (Au) metal -30 are vapor-deposited on the indium gallium phosphide (InQ49GauiP) Schottky contact layer-2 2 as the source (g urce) and the drain, respectively. Electrode of Drain and Gate.
493224 五、發明說明(6) 本發明元件之結構是藉由低壓金屬有機化學氣相沉積 (LP-MOCVD)或分子束蠢晶成長法(MBE)在珅化鎵(GaAs)基 板-1 2上成長所得。元件是以傳統的溼蝕刻、光顯影、及 真空蒸鍍製程製備。金-鍺-鎳(Au/Ge/Ni)金屬層-26及_28 蒸鍍於摻雜之砷化鎵(GaAs)歐姆接觸層-24上,並在約400 C的環境下退火1分鐘以形成没-源極之歐姆接觸;在蒸鍍 上閘極金屬-30之前’沒-源極間之砷化鎵(GaAs)-24被钱 刻移除,以便將閘極金屬金(Au)蒸鍍於磷化銦鎵—22上; 最後利用化學溼姓刻法將各元件予以隔離。 圖二為本發明元件之相對應能帶圖,其中&為導電 帶,EF為費米能階’ Ev為價帶。本元件中利用大能隙之石舞 化銦鎵(I nQ 49GaG Ρ )材料作為蕭特基接觸層及緩衝展。上 方之磷化銦鎵(InGjGauiP)層可提供元件良好之蕭二基特 性;下方之磷化銦鎵(IiV^GauiP)層可抑制從基板漏^之 基板漏電流,使元件有良好的夾止特性。坤化1蘇' 〜 (In^Ga^As)及砷化鎵(GaAs)層形成複合式通道結構。 們縮減砷化銦鎵(InG.2GaQ.8As)層的厚度以形成通&量;化 效應,這可以增加砷化銦鎵(1% sAs)的有效=二, 砷化鎵(GaAs)層可以增進元件在高電場下 b μ 私穷卜之細作能力,因 此撞擊游離現象可以被避免而漏電流也因 口阳降低。此外在493224 V. Description of the invention (6) The structure of the device of the present invention is formed on a gallium halide (GaAs) substrate by low pressure metal organic chemical vapor deposition (LP-MOCVD) or molecular beam stupid growth (MBE). Growth income. The device is prepared by conventional wet etching, photo development, and vacuum evaporation processes. Gold-germanium-nickel (Au / Ge / Ni) metal layers -26 and _28 are vapor-deposited on the doped gallium arsenide (GaAs) ohmic contact layer -24, and annealed at about 400 C for 1 minute to Formed an ohmic contact between the source and the source; the gallium arsenide (GaAs) -24 between the source and the source was removed by a coin before evaporation of the gate metal -30 in order to vaporize the gate metal gold (Au) Plated on indium gallium phosphide-22; Finally, the components are isolated by chemical wet engraving. Fig. 2 is a corresponding energy band diagram of the element of the present invention, where & is a conductive band, EF is a Fermi energy level, and Ev is a valence band. In this device, a large band gap indium-gallium (I nQ 49GaG P) material is used as a Schottky contact layer and a buffer layer. The indium gallium phosphide (InGjGauiP) layer above can provide good characteristics of the device; the lower layer of indium gallium phosphide (IiV ^ GauiP) layer can suppress the substrate leakage current leaking from the substrate ^, so that the device has good clamping characteristics. Kunhua 1 Su '~ (In ^ Ga ^ As) and gallium arsenide (GaAs) layers form a composite channel structure. We reduced the thickness of the InG.2GaQ.8As layer to form a flux effect, which can increase the effectiveness of InGaAs (1% sAs) = 2. GaAs layer It can improve the ability of the device to perform fine work under high electric fields. Therefore, the impact-free phenomenon can be avoided and the leakage current is also reduced due to mouth yang. Also in
石知化鋼錄(I n〇 49Ga〇 51Ρ)及神化銦錄(I n Q o.2ua0 8As)、石ϋ 化細 蘇(I η〇.49GaQ 5ΐ Ρ)及石申化鎵(GaAs )界面間大的道杂册 > 〒笔可'不續 度可以有效的將載子侷限在通道層内,因μ ^ q凡外使在黑、、西班 境下本發明元件依然可保有良好之元件特性。 ° μ衣Shizhihua Steel Record (I n〇49Ga〇51P) and Demichemical Indium Record (I n Q o.2ua0 8As), Shi Yanhua fine Soviet (I η〇.49GaQ 5ΐ Ρ) and Shi Shenhua gallium (GaAs) interface Da Da's Miscellaneous Book> Discontinuity can effectively confine carriers to the channel layer, because μ ^ q can keep the elements of the present invention in a dark, black and western environment. Component characteristics. ° μ clothing
切224 五、發明説明(7) 圖一為本發明元件之兩端閘極崩潰電壓 電壓(V〇n)對溫度的關係圖。元件之閘極面積及起始 。而當閘極電流為〇· 5 mA/mm時,閘極崩潰雷1 0〇 β 溫度為 3 0 0,330,360,390,420 及450 Κ 分別Vgd)在 23· 9,23· 4,23· 0,22· 6 及22· 0 V ;另一方面:、、4· 5, 始電壓(V〇n)則為2· 05,1· 97,1. 93,1. 85,1 ^對應之起 以降 v。tl件在高溫時依然擁有高的閘極崩潰電壓(By ^1· 7〇 電壓(VQn),而其隨著溫度的變化率(竽士)則八D及起始 X 10 4/K及1· 14 X 10-3/K。如此優異的現象證明^到6· 8 件之結構設計確實可以有效將電子侷限在通道層發明 低漏電流、增加崩潰電壓,進而增進元件的高^ , 圖四為本發明元件在不同溫度下之共源出二二一 電壓三端特性圖。元件之閘極面積為J χ 1〇〇 em2。 ,為沒-爻極電壓(VDS),每一刻度為2 V ;縱座標為汲二電 流(ID),每一刻度為1 00 mA/_ ;閘-源極電壓(vGs)為—〇· 5 Ι/step,最大閘極電壓為+ ι·5 V。由圖中可發現本元件擁 有良好的電晶體放大、飽和及夾止特性。其臨界電壓() 在溫度為300,330,360,390,420及450 K時分別為 -1.795 ’ -1.797,-1.799,-1·800,一 1.803 及-1·808 V。 當溫度升高時,背景濃度會隨著升高,這會使額外的漏電 流經由基板流失’使元件之飽和及夾止特性變差。然而對 本元件而言,當溫度由3 00 Κ變化至4 5 0 Κ時,其臨界電壓 (Vth)的變化量只有1 3 mV,這表示元件的漏電流可以有效Cut 224 V. Description of the invention (7) Fig. 1 is a graph showing the relationship between the breakdown voltage (Von) of the gate and the temperature of the two ends of the element of the present invention. Gate area and starting of the component. When the gate current is 0.5 mA / mm, the gate breakdown temperature is 100, β, and the temperature is 300, 330, 360, 390, 420, and 450 κ (Vgd) at 23 · 9, 23 · 4, 23 · 0, 22 · 6 and 2 · 0 V; On the other hand:, 4, 5, the starting voltage (Von) is 2. 05, 1. 97, 1. 93, 1. 85, 1 ^ Corresponds to descend v. tl pieces still have a high gate breakdown voltage (By ^ 1.70 voltage (VQn)) at high temperature, and its rate of change with temperature (竽) is 8D and starting X 10 4 / K and 1 · 14 X 10-3 / K. Such an excellent phenomenon proves that the structural design of ^ to 6 · 8 pieces can indeed effectively confine the electrons to the channel layer, invent low leakage current, increase the breakdown voltage, and then increase the component height. Figure 4 This is the characteristic diagram of the two-terminal voltage and three-terminal characteristics of the components of the present invention at different temperatures. The gate area of the component is J χ 100m2. It is the no-sense voltage (VDS), each scale is 2 V; the vertical coordinate is the sink current (ID), each scale is 100 mA / _; the gate-source voltage (vGs) is -0.5 I / step, and the maximum gate voltage is + ι · 5 V. It can be found from the figure that this element has good transistor amplification, saturation, and pinch-off characteristics. Its critical voltages (-) at temperatures of 300, 330, 360, 390, 420, and 450 K are -1.795 '-1.797,- 1.799, -1 · 800, 1.803, and -1 · 808 V. When the temperature increases, the background concentration will increase, which will cause additional leakage current to be lost through the substrate. ' Makes the device's saturation and pinch-off characteristics worse. However, for this device, when the temperature changes from 3 00 K to 450 K, the change in its threshold voltage (Vth) is only 1 3 mV, which indicates the leakage of the device Current can be effective
五、發明說明(8) :ΐ ί低,使得臨界電壓(ν。隨溫度的變化率㈣, 本發明元件將非常適用於需要精準 小,因此 的數位積體電路中。 工 ’笔壓(Vth)變化 電二五。為及t:a;r;;:度為30 0及㈣、…極 圖。元件之閉二:為=電流2對”,之關係' 壓(VGS),每一刻度為〇、5 ,/m 、核座私為閘-源極電 每_列声 二、·,縱座標為閘極漏電流(IG), / 當溫度在3 0 0及450 κ、問-源極電 於Λ及22· t/ V範圍時,問極漏電流(Ig)則分別小 如#\曰 # _。此外在圖五中並沒有看到一般砷化 』、·豕琢效電晶體常出現之閘極漏電流(D之鐘型 曲線,這表示本發明元件之複合式通道紝 構確貫可以消除撞擊游離(impact i〇nizati〇 ^ 漏電流大幅的降低。 便 圖六為本發明元件之轉導值(心)、電壓增益(^)及輸 出電導(gds )對溫度的關係圖。元件之閘極面積為1 X丨〇 〇 // m 。杈座標為溫度,每一刻度為3 〇 κ。左縱座標為轉導 值(gm)及電壓增益(Av),每一刻度為4〇 mS/mm及4〇。右縱 ,標為輸出電導(gds),每一刻度為〇. 〇5 mS/mm。元件之偏 壓點定在汲-源極電壓(VDS)為6· 〇 V和閘-源極電壓(VGS)為 + 〇·5 V。輸出電導(gds)在溫度為 3〇〇,33〇,36〇,39〇, 420,及 450 K 時分別為 0·60,〇.61,0.61,0.61,0.60, 及0 · 6 0 m S / m m。可以發現到輸出電導(gds)在高溫時依然保 持很小值,並且對溫度的增加幾乎沒有相關性,這再次證V. Description of the invention (8): ΐ Low, so that the critical voltage (ν. The rate of change with temperature ㈣, the element of the present invention will be very suitable for digital integrated circuits that need to be accurate and small, so the work pressure (Vth ) The change of electricity is twenty-five. It is equal to t: a; r ;;: degrees are 30 0 and 极, ... pole figure. The second part of the component: == 2 pairs of current ", the relationship 'voltage (VGS), each scale Is 0,5, / m, the nuclear base is the gate-source current per column, and the vertical coordinate is the gate leakage current (IG), / when the temperature is between 300 and 450 κ, Q-source When the pole voltage is in the range of Λ and 22 · t / V, the leakage current (Ig) of the pole is as small as # \ Yue # _. In addition, the general arsenization is not seen in Figure 5. Frequent gate leakage current (D-shaped bell curve, which indicates that the composite channel structure of the element of the present invention can eliminate the impact leakage (impact i〇nizati〇 ^ leakage current is greatly reduced.) Figure 6 is the invention The relationship between the element's transduction value (heart), voltage gain (^), and output conductance (gds) as a function of temperature. The gate area of the element is 1 X 丨 〇〇 // m. The coordinate of the branch is temperature. A scale is 3 κ. The left vertical coordinate is the transconductance value (gm) and the voltage gain (Av). Each scale is 40 mS / mm and 40. The right vertical axis is the output conductance (gds). The degree is 0.05 mS / mm. The bias point of the device is set at a drain-source voltage (VDS) of 6.0 volts and a gate-source voltage (VGS) of +0.5 volts. The output conductance (gds ) 0. 60, 0.61, 0.61, 0.61, 0.60, and 0.60 m S / mm at temperatures of 300, 33, 36, 39, 420, and 450 K. Yes It is found that the output conductance (gds) remains small at high temperatures and has little correlation with the increase in temperature, which proves again
\\Adm-host\20010610\P11200\ckull299.ptd 493224 五、發明說明(9) 明了本兀件確實可以在保持很低的漏電流下增進元件的特 性。另一方面相對應的轉導值(&)則分別為丨6 },丨5 5, ^1 147,H1,及138 mS/mm,因此本元件可以得到相去 南之電壓增盈(A^g/gds)值分別為268,254,248,241, 235 ’及2 30。由於本發明元件擁有相當高之電壓增益( 值,因此相當適合於必須在高溫操作下之放大電路使用' 圖七為本發明元件在不同汲極電流(ID)條件下之頻率 元二牛之間極面積為1x100㈣2。橫座標為汲極 包"丨L( D),母一刻度為70 mA/mm,·縱座標為頻率,一 巧10 GHz。本元件擁有良好之頻率特性表現停 %其最大之早位電流增益裁止頻率(unity cUrrent gain cut-off fre(luency 卜)為15 9 GHz,最大 ^(maximum oscillation frequency fmax) |,J ^3〇. 5 " GHz。另一方面本發明元件也保有寬廣而線性 特性,當汲極電流mA/mm之操作範圍日士^ 本凡件頻率操作特性保持在其最大單位只/, (fT)及最大震錢率(f_)值的㈣以上,因止頻率 相當適合於高頻電路之應用。 ^明元件 雖然本發明已以—較佳實施例揭露如±,秋 以限定本發明’任何熟習此技藝者,纟不脫離:::非用 神和範圍β ’當可作各種之潤鄉,因此 精 當視後附之申請專利範圍所界定者為準。 之保蠖範圍 第14頁 \\Adm-host\20010610\PH200\ckull299.ptd 493224 案號 90126084 年 曰 修正 圖式簡單說明 圖一係本發明之複合式摻雜通道異質結構場效電晶體 之結構示意圖。 圖二係本發明元件之相對應能帶圖。 圖三係本發明元件之閘極崩潰電壓(BVgd)及起始電壓 ()對溫度的關係圖。 “- 圖四係本發明元件在不同溫度下之共源極電流—電壓 三端特性西線圖。 圖五係本發明元件在溫度為30 0及450 K、汲極-源極 電壓為4及8 V時,閘極漏電流對閘—源極電壓之關係圖。\\ Adm-host \ 20010610 \ P11200 \ ckull299.ptd 493224 V. Description of the invention (9) It is clear that this element can indeed improve the characteristics of the component while maintaining a very low leakage current. On the other hand, the corresponding transduction values (&) are respectively 丨 6}, 丨 5 5, ^ 1 147, H1, and 138 mS / mm, so this component can obtain a phase-to-south voltage gain (A ^ g / gds) values are 268, 254, 248, 241, 235 'and 2 30 respectively. Because the element of the present invention has a relatively high voltage gain value, it is quite suitable for use in amplifier circuits that must be operated at high temperatures. Figure 7 shows the frequency of the element of the present invention between two new elements under different drain current (ID) conditions. The pole area is 1x100㈣2. The horizontal coordinate is the drain package " 丨 L (D), the female scale is 70 mA / mm, and the vertical coordinate is frequency, which coincides with 10 GHz. This component has good frequency characteristics. The maximum early current gain cut-off frequency (unitity cUrrent gain cut-off fre) is 15 9 GHz, and the maximum ^ (maximum oscillation frequency fmax) |, J ^ 3〇. 5 " GHz. On the other hand this The invention element also maintains a wide and linear characteristic. When the operating range of the drain current mA / mm is in Japan, the frequency operation characteristic of this element is kept at its maximum unit only, (fT) and the maximum vibration rate (f_). Above, the stop frequency is quite suitable for the application of high-frequency circuits. Although the present invention has been disclosed as a preferred embodiment, such as ±, autumn is used to limit the present invention 'Anyone skilled in this art, don't leave: :: non Use God and Scope β 'as each Since it is Runxiang, it shall be subject to the definition of the scope of the patent application attached hereafter. The scope of guarantee is on page 14 \\ Adm-host \ 20010610 \ PH200 \ ckull299.ptd 493224 Case No. 90126084 Explanation Figure 1 is a schematic structural diagram of a field-effect transistor of a composite doped channel heterostructure of the present invention. Figure 2 is a corresponding band diagram of the element of the present invention. Figure 3 is a gate breakdown voltage (BVgd) of the element of the present invention and The relationship between the initial voltage () and the temperature. "-Figure 4 is a line graph of the common source current-voltage three-terminal characteristics of the device of the invention at different temperatures. Figure 5 is a device of the invention at temperatures of 30 0 and 450 K. The relationship between gate leakage current and gate-source voltage when the drain-source voltage is 4 and 8 V.
圖六係本發明兀件之轉導值(心)、電壓增益(Av)及輸 出電導(gdS)對溫度的關係圖。 ’ 圖七係本發明元件在不同汲極電流(D條件下之頻率 特性圖。 圖號說明 1 0 -場效電晶體 12-半絕緣型之砷化鎵(GaAs)基板 14-未摻雜之砷化鎵(GaAs)緩衝層 16-未摻雜之磷化銦鎵(InQ 49GaQ 51P)緩衝層 18-摻雜之砷化鎵(GaAs)通道層Figure 6 is a graph of the relationship between the transduction value (heart), voltage gain (Av), and output conductance (gdS) of the element of the present invention versus temperature. 'Figure 7 is a frequency characteristic diagram of the element of the present invention under different drain current conditions (D. Figure No. Description 10-Field Effect Transistor 12-Semi-Insulated Gallium Arsenide (GaAs) Substrate 14-Undoped GaAs buffer layer 16-undoped indium gallium phosphide (InQ 49GaQ 51P) buffer layer 18-doped gallium arsenide (GaAs) channel layer
2 0-摻雜之砷化銦鎵(111().2〇3(),5)通道層 22-未摻雜之磷化銦鎵(IriG ^GauiP)蕭特基接觸層 2 4 _ 推雜之坤化蘇(G a A s )歐姆接觸層 26,28-汲,源極之金-鍺-鎳(Au/Ge/Ni) 3 0- 閘極之金(Au)2 0-doped indium gallium arsenide (111 (). 203 (), 5) channel layer 22- undoped indium gallium phosphide (IriG ^ GauiP) Schottky contact layer 2 4 _ Ga A s ohmic contact layer 26, 28-drain, source gold-germanium-nickel (Au / Ge / Ni) 3 0- gate gold (Au)
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW90126084A TW493224B (en) | 2001-10-22 | 2001-10-22 | Composite doped channel heterostructure field-effect transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW90126084A TW493224B (en) | 2001-10-22 | 2001-10-22 | Composite doped channel heterostructure field-effect transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
TW493224B true TW493224B (en) | 2002-07-01 |
Family
ID=21679561
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW90126084A TW493224B (en) | 2001-10-22 | 2001-10-22 | Composite doped channel heterostructure field-effect transistor |
Country Status (1)
Country | Link |
---|---|
TW (1) | TW493224B (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI456755B (en) * | 2011-05-11 | 2014-10-11 | Univ Nat Kaohsiung Normal | Metamorphic integrated bifets |
TWI487101B (en) * | 2011-03-18 | 2015-06-01 | Univ Nat Cheng Kung | Electrophoretic gate heterostructure field effect transistor and its manufacturing method |
CN110610991A (en) * | 2019-09-27 | 2019-12-24 | 厦门市三安集成电路有限公司 | Epitaxial structure and low on-voltage transistor |
-
2001
- 2001-10-22 TW TW90126084A patent/TW493224B/en not_active IP Right Cessation
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI487101B (en) * | 2011-03-18 | 2015-06-01 | Univ Nat Cheng Kung | Electrophoretic gate heterostructure field effect transistor and its manufacturing method |
TWI456755B (en) * | 2011-05-11 | 2014-10-11 | Univ Nat Kaohsiung Normal | Metamorphic integrated bifets |
CN110610991A (en) * | 2019-09-27 | 2019-12-24 | 厦门市三安集成电路有限公司 | Epitaxial structure and low on-voltage transistor |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW466768B (en) | An In0.34Al0.66As0.85Sb0.15/InP HFET utilizing InP channels | |
JPH05275463A (en) | Semiconductor device | |
JPS5922367A (en) | Semiconductor device | |
TW452978B (en) | High-breakdown voltage heterostructure field-effect transistor for high-temperature operations | |
JPS5891682A (en) | Semiconductor device | |
TW493224B (en) | Composite doped channel heterostructure field-effect transistor | |
TW583772B (en) | Field-effect type compound semiconductor device and method for fabricating the same | |
TWI222750B (en) | Voltage adjustable multi-stage extrinsic transconductance amplification HEMT | |
JPS6356710B2 (en) | ||
CN109742144A (en) | A kind of enhanced MISHEMT device of slot grid and preparation method thereof | |
JP6838257B2 (en) | Semiconductor device | |
JP2019192795A (en) | High electron mobility transistor | |
JP6853423B2 (en) | Resistor element and power amplifier circuit | |
JPS6242569A (en) | Field effect transistor | |
JPH03145139A (en) | Field-effect transistor and manufacture thereof | |
JP5112404B2 (en) | Diamond field effect transistor | |
JP2019192796A (en) | High electron mobility transistor | |
US6184546B1 (en) | High barrier gate and tri-step doped channel field-effect transistor | |
US20230134698A1 (en) | Apparatus and method to control threshold voltage and gate leakage current for gan-based semiconductor devices | |
US20210320198A1 (en) | Transistor | |
JP2013030604A (en) | Field effect transistor | |
JPS6196770A (en) | Semiconductor device | |
TW588458B (en) | Heterostructure field-effect transistor | |
Yu et al. | InGaP/GaAs camel-like field-effect transistor for high-breakdown and high-temperature applications | |
JP4249874B2 (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MM4A | Annulment or lapse of patent due to non-payment of fees |