CN102709322B - High-threshold-voltage gallium nitride enhanced transistor structure and preparation method thereof - Google Patents

Abstract

High threshold voltage gallium nitride enhancement transistor structure and preparation method, related to semiconductor technology. The present invention includes a substrate, GaN and AlGaN layers and an insulating gate dielectric layer from bottom to top, characterized in that the insulating gate dielectric layer includes an insulating tunnel layer, a fixed charge layer and an insulating cap layer, the fixed charge layer is arranged above the insulating tunnel layer or embedded in the upper part of the insulating tunnel layer, an insulating cap layer is arranged above the fixed charge layer, and a gate metal is arranged above the insulating cap layer. The beneficial effect of the present invention is that compared with other technologies for manufacturing enhancement-mode GaN field effect transistors, the preparation process of this technology is well controllable, and the performance repeatability of the developed device is good. The developed enhancement-mode GaN MISHEMT device has good performance, large threshold voltage, large maximum source-drain saturation current density, small gate leakage, and a wide device operating voltage range, which can fully meet the needs of GaN integrated circuit development.

Description

High Threshold Voltage GaN Enhancement Transistor Structure and Fabrication Method

technical field

The present invention relates to semiconductor technology.

Background technique

Compared with high electron mobility transistors (HEMTs) based on AlGaAs/GaAs (AlGaAs/GaAs) heterojunctions, HEMT devices based on AlGaN/GaN (AlGaN/GaN) heterojunctions have the following advantages:

(1) The two-dimensional electron gas (2DEG) concentration at the AlGaN/GaN heterojunction interface is relatively high (up to 1013cm-2), which is nearly an order of magnitude higher than the 2DEG concentration at the AlGaAs/GaAs heterojunction interface. Therefore, based on AlGaN/GaN heterojunction HEMT will have higher output power density. As a mass-produced product, the power density of HEMT devices based on AlGaN/GaN heterojunction has reached more than 10W/mm, which is nearly 20 times higher than that of GaAs-based HEMT devices.

(2) Since GaN is a wide bandgap semiconductor, its operating temperature is high and can work normally above 500°C, while the limit operating temperature of HEMT devices based on AlGaAs/GaAs heterojunction is about 200°C.

(3) Since GaN has a higher breakdown electric field, HEMT devices based on AlGaN/GaN heterojunctions have higher gate-drain breakdown voltages. Compared with AlGaAs/GaAs heterojunction HEMT devices, their The working bias is several times higher.

(4) Due to the high chemical bond energy of the dry GaN material, the physical and chemical properties of the material are stable, and it is weakly affected by external physical and chemical effects. Therefore, HEMTs based on AlGaN/GaN heterojunctions have strong radiation resistance.

Due to the above characteristics of GaN devices, not only the HEMT devices based on AlGaN/GaN heterojunction can be widely used in the fields of high-frequency power devices such as radar, communication and aerospace, but also have great application potential in the field of power electronic devices, making it It has become the semiconductor material with the most application potential after silicon (Si) and gallium arsenide, and has been widely concerned and researched by the industry and academia.

Since GaN is a highly polar semiconductor material, a high concentration of 2DEG is naturally formed at the AlGaN/GaN heterojunction interface, and it is difficult to deplete the 2DEG at the AlGaN/GaN heterojunction interface under normal circumstances. Therefore, based on AlGaN/GaN Heterojunction HEMT devices are usually depletion type, that is, AlGaN/GaN heterojunction HEMT devices are in the normally-on state under zero bias, and only when a certain amount of negative bias is applied to the gate can the device be turned on. In the off state, for the application in the field of power electronic devices, its safety will become a big problem. At the same time, even for the design and development of digital logic integrated circuits, in order to ensure the logic safety of logic circuits, not only enhanced devices (threshold voltage greater than zero) are required, but also enhanced devices are required to have a higher threshold voltage. For this reason, research Workers have not only been exploring the fabrication technology of enhancement-mode AlGaN/GaN HEMT devices, but also been exploring ways to increase the threshold voltage. At present, the main methods of manufacturing enhanced GaN HEMT devices are as follows:

(1) Reduce the 2DEG concentration at the AlGaN/GaN heterojunction interface by energy band design and shearing, thereby realizing an enhanced GaN HEMT device.

The biggest disadvantage of this method is that it cannot achieve compatibility with depletion-mode GaN HEMT devices, that is to say, it is impossible to manufacture both enhancement-mode GaN HEMT devices and depletion-mode GaN HEMT devices on the same piece of material. Therefore, This method cannot meet the development needs of GaN digital logic circuits.

(2) By reducing the thickness of the AlGaN barrier layer in the gate region and reducing the 2DEG concentration in the gate region, an enhanced GaN HEMT device is realized.

Although this method is effective, its biggest problem is that it is difficult to accurately control the thickness of the AlGaN barrier layer in the gate region due to the difficulty in monitoring the etch rate. Therefore, the performance consistency and repeatability of the fabricated enhancement-mode GaN HEMT devices It is difficult to guarantee the reliability, which is also unacceptable for the development of GaN digital logic circuits. In addition, it is difficult to achieve a high threshold voltage with this method.

(3) F ions are implanted into the AlGaN barrier layer in the gate region to deplete the 2DEG in the gate region, thereby realizing an enhanced GaN HEMT device.

Although this method avoids the shortcomings of the above two methods, its biggest problem is that the F ion implantation of the AlGaN barrier layer in the gate region will destroy the characteristics of the AlGaN/GaN heterojunction interface and degrade the performance of the GaN enhanced HEMT device. , so that the performance of the developed GaN integrated circuit is poor. Moreover, in order to further increase the threshold voltage, the electrical performance of the device will be more severely degraded.

Contents of the invention

The technical problem to be solved by the present invention is to provide an enhanced GaN-HEMT device structure with a higher threshold voltage and its preparation method, which can realize the compatibility between the enhanced GaN HEMT device and the depletion-mode GaN HEMT device , and can ensure that the performance of the enhancement-mode GaN HEMT device is equivalent to that of the depletion-mode GaN HEMT device, and can also have a high threshold voltage.

The technical solution adopted by the present invention to solve the above-mentioned technical problem is: high threshold voltage gallium nitride enhancement transistor structure, including: including substrate, GaN and AlGaN layers and insulating gate dielectric layer from bottom to top, characterized in that the insulating gate The dielectric layer includes an insulating tunnel layer, a fixed charge layer and an insulating cap layer. The fixed charge layer is arranged above the insulating tunnel layer or embedded in the upper part of the insulating tunnel layer. An insulating cap layer is arranged above the fixed charge layer. Above the insulating cap layer is a gate metal layer. .

The material of the insulating gate dielectric layer is Al ₂ O ₃ , SiO ₂ , HfO ₂ , HfTiO, ZrO ₂ or SiNO.

The present invention also provides a high threshold voltage gallium nitride enhancement transistor structure preparation method, including the following steps:

(1) Prepare an AlGaN/GaN heterojunction material on a sapphire substrate, that is, a wafer, and deposit a layer of Al ₂ O ₃ film on the surface of the wafer as an insulating tunnel layer;

(2), prepare the metal electrode of source region and drain region;

(3) Spin-coat photoresist on the surface of the wafer, and locate the position of the gate area by aligning the photolithography method, put the wafer into the reactive ion etching machine, use _CF4 as the reaction gas, and align the gate The region is implanted with F ions to form a fixed charge layer;

(4) Deposit a 10nm thick Al ₂ O ₃ gate dielectric on the wafer surface at room temperature as an insulating cap layer;

(5), deposit Ni/Au metal thin film on wafer surface, the thickness of Ni/Au metal thin film is respectively 100nm and 50nm, and form gate metal electrode by lift-off process, then carry out annealing treatment to whole wafer under nitrogen atmosphere.

The beneficial effect of the invention is that, compared with other technologies for manufacturing enhanced GaN field effect transistors, the preparation process of the technology has good controllability, and the developed device performance has good repeatability. The enhanced GaN MISHEMT device developed has good performance, high threshold voltage, high maximum source-drain saturation current density, small gate leakage, and wide operating voltage range of the device, which can fully meet the needs of GaN integrated circuit development.

Description of drawings

Figure 1 is a schematic diagram of the structure of an enhancement-mode GaN HEMT device with a high threshold voltage.

Fig. 2 is a schematic diagram of the manufacturing process flow of the enhanced GaN MISHEMT device of the present invention manufactured by plasma immersion treatment and ion implantation method.

Fig. 3 is a schematic diagram of the manufacturing process flow of the enhanced GaN MISHEMT device of the present invention by vacuum deposition of an insulating gate dielectric film in an atmosphere containing F or Cl.

Fig. 4 is a schematic diagram of a GaN integrated circuit composed of an enhanced GaN MISHEMT and a depleted GaN MESHEMT of the present invention.

Fig. 5 is a schematic diagram of a GaN integrated circuit composed of an enhanced GaN MISHEMT and a depleted GaN MISHEMT of the present invention.

Fig. 6 is a graph showing the influence of the insulating cap layer of the present invention on the threshold voltage of the enhanced GaN MISHEMT device.

In FIG. 4 and FIG. 5 , the area of the negative charge icon juxtaposed under the insulating cap layer represents the fixed charge layer.

Detailed ways

The basic structure diagram of the enhanced GaN HEMT device of the present invention is shown in Figure 1, belongs to the metal-insulator-semiconductor (MIS) field effect transistor, compared with the common MIS structure GaN field effect transistor, the MIS structure GaN field effect transistor of the present invention The characteristics of the effect transistor are: the insulating gate dielectric includes three parts: an insulating cap layer, a fixed negative charge layer, and an insulating tunnel layer. The two-dimensional electron gas in the gate region is depleted by the charge of the fixed negative charge layer, and the threshold voltage is greater than zero. Then, the threshold voltage of the device is further increased by introducing an insulating cap layer, thereby manufacturing a GaN-enhanced high electron mobility transistor with a higher threshold. Among them, the insulating gate dielectric mainly uses Al ₂ O ₃ , SiO ₂ , HfO ₂ , HfTiO, ZrO _2. For SiN _x , SiNO, the introduced fixed negative charge mainly selects F ions and Cl ions with high electronegativity.

The specific manufacturing process of the present invention is as follows: depositing an insulating tunnel layer film first, then introducing a certain amount of fixed negative charges on the surface of the insulating tunnel layer film to realize an enhanced device, then depositing an insulating cap layer on the surface of the fixed negative charge layer, and finally Deposit the metal gate electrode. Through the introduction of the insulating cap layer, a built-in electric field is formed between the metal gate and the fixed negative charge layer, thereby realizing a higher threshold voltage.

In the present invention, the fixed negative charge can be introduced into the insulating gate dielectric by: plasma immersion treatment containing F or Cl, ion implantation of F or Cl into the gate dielectric, vacuum deposition of insulating gate dielectric in an atmosphere containing F or Cl thin film and other methods, wherein, for the method of introducing fixed negative charges by plasma immersion treatment, the amount of fixed negative charges entering the insulating gate dielectric is regulated by controlling the plasma power and immersion time; for the introduction of fixed negative charges by ion implantation The charge method, by controlling the energy of the implanted ions, the ions are only implanted into the insulating gate dielectric, and there is no ion implantation in the AlGaN barrier layer, so as to ensure that the characteristics of the AlGaN/GaN heterojunction interface and the performance of the developed device do not seriously occur. Degradation, and by controlling the dose of implanted ions to regulate the amount of fixed negative charges entering the insulating gate dielectric; for the method of introducing fixed negative charges by vacuum-depositing insulating gate dielectric films in an atmosphere containing F and Cl, by controlling the film The partial pressure of the gas containing F and Cl in the deposition atmosphere is used to control the amount of fixed negative charges entering the insulating gate dielectric.

For adopting plasma immersion treatment and ion implantation method to manufacture enhanced GaN MISHEMT device of the present invention, its manufacturing process flow is as shown in Figure 2, first deposits insulating tunnel layer dielectric film on AlGaN/GaN surface, then lithography goes out source electrode ( Source) and drain (Drain) positions, deposit metal electrodes at the source (Source) and drain (Drain) positions, and form ohmic contacts at the source and drain after rapid annealing. After the position of the gate region is defined by photolithography technology, the gate region is subjected to plasma immersion treatment or ion implantation to form a fixed charge layer film, and an insulating cap layer is deposited. Finally, a metal electrode is deposited on the gate region to form a gate electrode, thereby manufacturing an enhanced type GaN MISHEMT devices.

For the method of vacuum-depositing insulating gate dielectric film in an atmosphere containing F or Cl to manufacture the enhanced GaN MISHEMT device of the present invention, its manufacturing process is shown in Figure 3. Deposit the insulating tunnel layer dielectric film, and directly introduce fixed negative charges into the gate dielectric film during the gate dielectric deposition process through atmosphere control to form a fixed charge layer film, and then photoetch the source (Source) and drain (Drain) positions , Deposit metal electrodes at the source (Source) and drain (Drain) positions, and form ohmic contacts at the source and drain after rapid annealing. After the position of the gate region is defined by photolithography, a 10nm-thick insulating cap layer dielectric is finally deposited on the gate region, and then a metal electrode is deposited on the gate region to form a gate electrode, thereby manufacturing an enhanced GaN MISHEMT device.

The enhanced GaN MISHEMT device of the present invention can be integrated with a depletion GaN field effect transistor (MESHEMT) of a metal-semiconductor structure to form a GaN integrated circuit, as shown in Figure 4, and can also be integrated with a depletion GaN MISHEMT device integrated to form a GaN integrated circuit, as shown in Figure 5.

Using the process flow shown in Figure 2 of the present invention, the enhanced GaNMISHEMT device was successfully developed using F ion-implanted Al ₂ O ₃ (hereinafter abbreviated as: F:Al ₂ O ₃ ) thin film as the gate dielectric, and the device structure schematic diagram As shown in Figure 1. Specific steps are as follows:

(1) Prepare AlGaN/GaN heterojunction materials (hereinafter referred to as wafers) on sapphire substrates as the material basis for the development of GaN field effect transistors, and use molecular beam epitaxy (MBE) on the surface of AlGaN/GaN heterojunction materials A thin film of Al ₂ O ₃ with a thickness of about 10 nm is deposited as an insulating tunnel layer.

(2) Spin-coat photoresist on the surface of AlGaN/GaN heterojunction material covered with Al ₂ O ₃ film, locate the source region (Source) and drain region (Drain) by photolithography, and then use 1: 100 HF solution to etch away the Al ₂ O ₃ film at the position of the source region and the drain region. Electron beam evaporation technology is used to deposit Ti/Al/Ni/Au multilayer film metal electrodes. The thickness of Ti/Al/Ni/Au multilayer film metal electrodes is 20nm/100nm/30nm/50nm respectively, and the source area is prepared by lift-off process and the metal electrode of the drain region, and perform rapid annealing treatment (annealing temperature 825° C., annealing time 30 s) on the metal electrode in a nitrogen atmosphere to form an ohmic electrode.

(3), then spin-coat photoresist on the wafer surface, and after positioning the position of the gate region by aligning the photolithography method, put the wafer into the reactive ion etching machine, use _CF4 as the reaction gas, and F ion implantation is carried out in the gate area to form a fixed charge layer dielectric film. The process conditions are: implantation power 60W, working pressure 20mTorr, and implantation time 300s.

(4) Put the wafer into molecular beam epitaxy (MBE), and deposit a 10nm-thick Al ₂ O ₃ gate dielectric at room temperature as an insulating cap film.

(5) Electron beam evaporation is used to deposit a Ni/Au metal film on the wafer surface. The thickness of the Ni/Au metal film is 100nm/50nm respectively, and the gate metal electrode is formed by a lift-off process, and then the entire wafer is treated under a nitrogen atmosphere. The circle is annealed (annealing temperature 400°C, annealing time 10min.).

Through the above process steps, the enhanced GaN MISHEMT device with high threshold voltage F:Al ₂ O ₃ gate dielectric can be developed. For comparison, an enhanced GaN MISHEMT without insulating cap layer gate dielectric is also produced. , using the HP4284A LCR instrument to test the electrical properties of the two devices developed.

Figure 6 shows the influence of the insulating cap layer on the transfer characteristics of the device. It can be seen that the threshold voltage of the enhanced GaN MISHEMT device without the insulating cap layer gate dielectric is +0.5V, while the enhanced GaN MISHEMT device with the insulating cap layer gate dielectric The threshold voltage of the MISHEMT device reaches +2.6V. The enhanced device produced by this patented method not only has a higher threshold voltage, but also has a maximum source-drain saturation current of 350mA/mm and a maximum saturated transconductance of 55mS/mm.

Claims (5)

1. high threshold voltage gallium nitride enhancement transistor structure, comprise substrate, GaN and AlGaN layer and insulated gate dielectric layer from bottom to top, it is characterized in that, described insulated gate dielectric layer comprises insulating tunnel layer, fixed charge layer and insulative cap, fixed charge layer is arranged at above insulating tunnel layer or is embedded in insulating tunnel layer top, the top of fixed charge layer is provided with insulative cap, is grid metal electrode above insulative cap; Insulating tunnel layer is identical with insulative cap material.

2. high threshold voltage gallium nitride enhancement transistor structure as claimed in claim 1, it is characterized in that, the material of described insulating tunnel layer and insulative cap is Al ₂o ₃, SiO ₂, HfO ₂, HfTiO, ZrO ₂or SiNO.

3. prepare the method for high threshold voltage gallium nitride enhancement transistor structure as claimed in claim 1, it is characterized in that, comprise the steps:

(1), on a sapphire substrate prepare AlGaN/GaN heterojunction material, i.e. wafer, deposits one deck Al at crystal column surface ₂o ₃film, as insulating tunnel layer;

(2) metal electrode in source region and drain region, is prepared;

(3), at crystal column surface spin coating photoresist, and oriented the position in grid region by alignment light carving method after, wafer is put into reactive ion etching machine, use CF ₄as reacting gas, F ion injection is carried out to grid region, form fixed charge layer;

(4), at the Al that crystal column surface normal temperature deposition 10nm is thick ₂o ₃gate medium, as insulative cap;

(5), at crystal column surface deposition Ni/Au metallic film, the thickness of Ni/Au metallic film is respectively 100nm and 50nm, and forms grid metal electrode by stripping technology, then carries out annealing in process to whole wafer under nitrogen atmosphere.

4. method as claimed in claim 3, it is characterized in that, described step (2) is: be coated with Al ₂o ₃the AlGaN/GaN heterojunction material surface spin coating photoresist of film, orients the position in source region and drain region by photoetching, then uses the HF solution of 1:100 by the Al of source region and position, drain region ₂o ₃film etches away; Adopt electron beam evaporation technique depositing Ti/Al/Ni/Au multilayer film metal electrode, the thickness of Ti/Al/Ni/Au multilayer film metal electrode is respectively 20nm/100nm/30nm/50nm, stripping technology is adopted to prepare the metal electrode in source region and drain region, and in blanket of nitrogen, short annealing process is carried out to metal electrode, annealing temperature 825 DEG C, annealing time 30s, to form ohmic contact.

5. method as claimed in claim 3, it is characterized in that, described step (3) ~ (5) are:

(3), at crystal column surface spin coating photoresist, and oriented the position in grid region by alignment light carving method after, wafer is put into reactive ion etching machine, use CF ₄as reacting gas, F ion injection is carried out to grid region, form fixed charge layer, injecting power 60W, operating air pressure 20mTorr, injection length 300s;

(4), by wafer molecular beam epitaxy is put into, by the Al that normal temperature deposition 10nm is thick ₂o ₃gate medium, as insulative cap;

(5), adopt electron beam evaporation at crystal column surface deposition Ni/Au metallic film, the thickness of Ni/Au metallic film is respectively 100nm and 50nm, and form grid metal electrode by stripping technology, under nitrogen atmosphere annealing in process is carried out to whole wafer again, annealing temperature 400 DEG C, annealing time 10min.