CN102709322B - High-threshold-voltage gallium nitride enhanced transistor structure and preparation method thereof - Google Patents
High-threshold-voltage gallium nitride enhanced transistor structure and preparation method thereof Download PDFInfo
- Publication number
- CN102709322B CN102709322B CN201210172341.8A CN201210172341A CN102709322B CN 102709322 B CN102709322 B CN 102709322B CN 201210172341 A CN201210172341 A CN 201210172341A CN 102709322 B CN102709322 B CN 102709322B
- Authority
- CN
- China
- Prior art keywords
- layer
- gan
- metal electrode
- insulated
- fixed charge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 91
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 8
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 238000005516 engineering process Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 42
- 238000000137 annealing Methods 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 14
- 230000008021 deposition Effects 0.000 claims description 13
- 239000013078 crystal Substances 0.000 claims description 12
- 238000002347 injection Methods 0.000 claims description 10
- 239000007924 injection Substances 0.000 claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000004528 spin coating Methods 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 5
- 238000005566 electron beam evaporation Methods 0.000 claims description 4
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- 239000000243 solution Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- 230000005669 field effect Effects 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 238000011161 development Methods 0.000 abstract description 6
- 239000010408 film Substances 0.000 description 23
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 7
- 239000012298 atmosphere Substances 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- 238000005036 potential barrier Methods 0.000 description 5
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 230000001276 controlling effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 238000007654 immersion Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- -1 aluminium arsenic Chemical compound 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
A high threshold voltage gallium nitride enhanced transistor structure and a preparation method thereof relate to the semiconductor technology. The GaN-based gate structure comprises a substrate, a GaN layer, an AlGaN layer and an insulated gate dielectric layer from bottom to top, and is characterized in that the insulated gate dielectric layer comprises an insulated tunnel layer, a fixed charge layer and an insulated cap layer, the fixed charge layer is arranged above the insulated tunnel layer or embedded in the upper part of the insulated tunnel layer, the insulated cap layer is arranged above the fixed charge layer, and gate metal is arranged above the insulated cap layer. Compared with other technologies for manufacturing the enhanced GaN field effect transistor, the preparation technology of the invention has the advantages of good controllability and good repeatability of the performance of the developed device. The developed enhanced GaN MISHEMT device has good performance, large threshold voltage, large maximum source-drain saturation current density, small gate leakage and wide device working voltage range, and can completely meet the development requirement of a GaN integrated circuit.
Description
Technical field
The present invention relates to semiconductor technology.
Background technology
Compared with the High Electron Mobility Transistor (HEMT) based on gallium aluminium arsenic/gallium arsenic (AlGaAs/GaAs) heterojunction, the HEMT device based on aluminum gallium nitride/gallium nitrogen (AlGaN/GaN) heterojunction has the following advantages:
(1), two-dimensional electron gas (2DEG) concentration of AlGaN/GaN heterojunction boundary higher (can 1013cm-2 be reached), nearly order of magnitude is exceeded than the 2DEG concentration of AlGaAs/GaAs heterojunction boundary, therefore, the HEMT based on AlGaN/GaN heterojunction will have higher output power density.As the product of large-scale production, the HEMT device power density based on AlGaN/GaN heterojunction reaches more than 10W/ millimeter, exceeds nearly 20 times than the power density of GaAs HEMT.
(2), because GaN belongs to wide bandgap semiconductor, its working temperature is high, normally can work, and be about about 200 DEG C based on the working temperature limit of the HEMT device of AlGaAs/GaAs heterojunction more than 500 DEG C.
(3), because GaN has higher breakdown electric field, therefore, the HEMT device based on AlGaN/GaN heterojunction has higher grid-drain breakdown voltage, and compared with AlGaAs/GaAs heterojunction HEMT device, its operating bias exceeds more than several times.
(4), high by dry GaN material chemistry bond energy, the physical and chemical performance of material is stablized, and the impact by external physics, chemical action is weak, and therefore, the HEMT based on AlGaN/GaN heterojunction has very strong Radiation hardness.
Due to the above feature of GaN device, not only make the HEMT device based on AlGaN/GaN heterojunction can be widely used in the high-frequency power device fields such as radar, communication and Aero-Space, also in power electronic device field, there is very big application potential, make it to become the semi-conducting material having application potential after silicon (Si), gallium arsenic most, and be extensively subject to concern and the research of industry and educational circles.
Because GaN is a kind of strong polar semiconductor material, at the 2DEG of AlGaN/GaN heterojunction boundary self-assembling formation high concentration, be difficult to the 2DEG exhausting AlGaN/GaN heterojunction boundary under normal conditions, so, HEMT device based on AlGaN/GaN heterojunction is depletion type usually, that is: under zero-bias, the HEMT device of AlGaN/GaN heterojunction is in normally open, when only adding a certain size back bias voltage on grid, device just can be made to be in off state, this is for the application in power electronic device field, and its fail safe will become very large problem.Simultaneously, even if concerning digital logical integrated circuit design and development, in order to ensure the logical security of logical circuit, not only need enhancement device (threshold voltage is greater than zero), and require that enhancement device has higher threshold voltage, for this reason, research worker is not only exploring the manufacturing technology of enhanced AlGaN/GaN HEMT device always, and is exploring the method improving threshold voltage always.At present, the main method of enhancement mode GaN HEMT device manufacture is as follows:
(1), by design can be with and shear the 2DEG concentration reducing AlGaN/GaN heterojunction boundary, thus enhancement mode GaN HEMT device is realized.
The disadvantage of this method is: cannot realize the compatibility with depletion type GaN HEMT device, that is: cannot both manufacture enhancement mode GaN HEMT device on same one piece material, also develop depletion type GaN HEMT device, therefore, this method cannot meet the development needs of GaN Digital Logical Circuits.
(2), by the AlGaN potential barrier thickness in thinning grid region, reduce the 2DEG concentration in grid region, thus realize enhancement mode GaN HEMT device.
Although this method is effective, but its maximum problem is: due to very difficult monitoring etch rate, the thickness of grid region AlGaN potential barrier is caused to be difficult to accurate control, therefore, the consistency of performance of manufactured enhancement mode GaN HEMT device and repeatability are difficult to ensure, this is for the development of GaN Digital Logical Circuits, is beyond affordability equally.In addition, this method is difficult to realize higher threshold voltage.
(3), to grid region AlGaN potential barrier inject F ion, exhaust the 2DEG in grid region, thus realize enhancement mode GaN HEMT device.
Although this method avoids the shortcoming of above two kinds of methods, but its maximum problem is: the F ion injection of grid region AlGaN potential barrier can destroy AlGaN/GaN heterojunction boundary characteristic, make the performance degradation of GaN enhancement mode HEMT device, thus make developed GaN performance of integrated circuits poor.And in order to improve threshold voltage further, the electric property of device there will be more serious decline.
Summary of the invention
Technical problem to be solved by this invention is: provide a kind of enhancement mode GaN-HEMT device architecture with higher threshold voltage and preparation method thereof, this device architecture can realize the compatibility of enhancement mode GaN HEMT device and depletion type GaN HEMT device, can ensure that again enhancement mode GaN HEMT device is suitable with depletion type GaN HEMT device performance to greatest extent, but also high threshold voltage can be had.
The technical scheme that the present invention solve the technical problem employing is: high threshold voltage gallium nitride enhancement transistor structure, comprise: comprise substrate, GaN and AlGaN layer and insulated gate dielectric layer from bottom to top, it is characterized in that, described insulated gate dielectric layer comprises insulating tunnel layer, fixed charge layer and insulative cap, fixed charge layer is arranged at above insulating tunnel layer or is embedded in insulating tunnel layer top, the top of fixed charge layer is provided with insulative cap, is grid metal above insulative cap.
The material of described insulated gate dielectric layer is Al
2o
3, SiO
2, HfO
2, HfTiO, ZrO
2or SiNO.
The present invention also provides high threshold voltage gallium nitride enhancement transistor structure preparation method, comprises the steps:
(1), on a sapphire substrate prepare AlGaN/GaN heterojunction material, i.e. wafer, deposits one deck Al at crystal column surface
2o
3film is as insulating tunnel layer;
(2) metal electrode in source region and drain region, is prepared;
(3), at crystal column surface spin coating photoresist, and oriented the position in grid region by alignment light carving method after, wafer is put into reactive ion etching machine, use CF
4as reacting gas, F ion injection is carried out to grid region, form fixed charge layer;
(4), at the Al that crystal column surface normal temperature deposition 10nm is thick
2o
3gate medium is as insulative cap;
(5), at crystal column surface deposition Ni/Au metallic film, the thickness of Ni/Au metallic film is respectively 100nm and 50nm, and forms grid metal electrode by stripping technology, then carries out annealing in process to whole wafer under nitrogen atmosphere.
The invention has the beneficial effects as follows, compared with the technology manufacturing enhancement mode GaN field-effect transistor with other, preparation technology's controllability of this technology is good, and the device performance developed is reproducible.The enhancement mode GaN MISHEMT device performance developed is good, and threshold voltage is large, and maximum source and drain saturation current density is large, and grid leak electricity is little, device operating voltages wide ranges, can meet GaN integrated circuit development needs completely.
Accompanying drawing explanation
Fig. 1 is the enhancement mode GaN HEMT device structural representation with high threshold voltage.
Fig. 2 is the manufacturing process flow schematic diagram that using plasma submergence process and ion injection method manufacture enhancement mode GaN MISHEMT device of the present invention.
Fig. 3 adopts manufacturing the manufacturing process flow schematic diagram of enhancement mode GaN MISHEMT device of the present invention containing the method for vacuum moulding machine insulated gate dielectric film in F or Cl atmosphere.
Fig. 4 is the GaN integrated circuit schematic of enhancement mode GaN MISHEMT of the present invention and the integrated formation of depletion type GaN MESHEMT.
Fig. 5 is the GaN integrated circuit schematic of enhancement mode GaN MISHEMT of the present invention and the integrated formation of depletion type GaN MISHEMT.
Fig. 6 is the influence curve figure of insulative cap of the present invention to enhancement mode GaN MISHEMT device threshold voltage.
In Fig. 4 and Fig. 5, negative electrical charge icon area arranged side by side below insulative cap represents fixed charge layer.
Embodiment
The basic structure schematic diagram of enhancement mode GaN HEMT device of the present invention as shown in Figure 1, belong to metal-insulator semiconductor (MIS) field-effect transistor, compared with common MIS structure GaN field-effect transistor, the feature of MIS structure GaN field-effect transistor of the present invention is: this insulated gate medium comprises insulative cap, fixed negative charge layer, insulating tunnel layer three parts, grid region two-dimensional electron gas is exhausted by the quantity of electric charge of fixed negative charge layer, realize threshold voltage and be greater than zero, device threshold voltage is improved further again by introducing insulative cap, thus produce the GaN enhancement type high electron mobility transistor with higher thresholds, wherein, insulated gate medium mainly adopts Al
2o
3, SiO
2, HfO
2, HfTiO, ZrO
2, SiN
x, SiNO, the fixed negative charge introduced mainly selects F ion that electronegativity is high and Cl ion.
Concrete process for making of the present invention is: first deposit insulating tunnel layer film, a certain amount of fixed negative charge is introduced again at insulating tunnel layer film surface, to realize enhancement device, then at fixed negative charge layer surface deposition insulative cap, last plated metal gate electrode.By the introducing of insulative cap, between metal gate and fixed negative charge layer, form an internal electric field, thus achieve higher threshold voltage.
In the present invention, in insulated gate medium, introduce fixed negative charge can adopt: containing the plasma immersion process of F or Cl, to gate medium intermediate ion injection F or Cl, in methods such as the atmosphere vacuum moulding machine insulated gate dielectric films containing F or Cl, wherein, using plasma submergence process is introduced to the method for fixed negative charge, regulate and control to enter into the quantity of electric charge of the fixed negative charge of insulated gate medium by control plasma power and Immersion time; For the method adopting ion implantation to introduce fixed negative charge, by controlling the energy injecting ion, ion is made only to be injected in insulated gate medium, ion implantation is not had in AlGaN potential barrier, thus guarantee that the performance of AlGaN/GaN heterojunction boundary characteristic and institute's impurity profile serious degradation does not occur, and by controlling to inject the quantity of electric charge that ion dose regulates and controls to enter into the fixed negative charge of insulated gate medium; For adopting vacuum moulding machine insulated gate dielectric film in the atmosphere containing F, Cl to introduce the method for fixed negative charge, by controlling the quantity of electric charge regulating and controlling to enter into the fixed negative charge of insulated gate medium in thin film deposition atmosphere containing the dividing potential drop of F, Cl gas.
Enhancement mode GaN MISHEMT device of the present invention is manufactured for using plasma submergence process and ion injection method, its manufacturing process flow as shown in Figure 2, first at AlGaN/GaN surface deposition insulating tunnel layer dielectric film, make source electrode (Source) and drain electrode (Drain) position again by lithography, in source electrode (Source) and drain electrode (Drain) position deposit metal electrodes, and form ohmic contact through short annealing at source electrode and drain electrode.After defining position, grid region by photoetching technique, again plasma immersion process or ion implantation formation fixed charge layer film are carried out to grid region, and it is last to deposit insulative cap, forms gate electrode in grid region deposit metal electrodes, thus produce enhancement mode GaN MISHEMT device.
Enhancement mode GaN MISHEMT device of the present invention is being manufactured containing the method for vacuum moulding machine insulated gate dielectric film in F or Cl atmosphere for adopting, its manufacturing process flow as shown in Figure 3, first containing under F or Cl atmosphere at AlGaN/GaN surface deposition insulating tunnel layer dielectric film, and directly in gate medium deposition process, in gate dielectric membrane, introduce fixed negative charge by control climate, form fixed charge layer film, make source electrode (Source) and drain electrode (Drain) position again by lithography, in source electrode (Source) and drain electrode (Drain) position deposit metal electrodes, and form ohmic contact through short annealing at source electrode and drain electrode.After defining position, grid region by photoetching technique, finally at the insulative cap medium that grid region deposition 10nm is thick, then form gate electrode in grid region deposit metal electrodes, thus produce enhancement mode GaN MISHEMT device.
Both can carry out integrated with the depletion type GaN field-effect transistor (MESHEMT) of metal-semiconductor structure by enhancement mode GaN MISHEMT device of the present invention, form GaN integrated circuit, as shown in Figure 4, can also carry out integrated with depletion type GaN MISHEMT device, form GaN integrated circuit, as shown in Figure 5.
Adopt the present invention's technological process as shown in Figure 2, adopt the Al that F ion is injected
2o
3(hereinafter abbreviated as: F:Al
2o
3) film successfully have developed enhancement mode GaNMISHEMT device as gate medium, its device architecture schematic diagram is as shown in Figure 1.Concrete steps are as follows:
(1), AlGaN/GaN heterojunction material (hereinafter referred to as wafer) is prepared on a sapphire substrate, as the material foundation of development GaN field-effect transistor, molecular beam epitaxy (MBE) is adopted to be about the thick Al of 10nm at AlGaN/GaN heterojunction material surface deposition one deck
2o
3film, as insulating tunnel layer.
(2), Al is being coated with
2o
3the AlGaN/GaN heterojunction material surface spin coating photoresist of film, orients the position of source region (Source) and drain region (Drain) by photoetching, then uses the HF solution of 1:100 by the Al of source region and position, drain region
2o
3film etches away.Adopt electron beam evaporation technique depositing Ti/Al/Ni/Au multilayer film metal electrode, the thickness of Ti/Al/Ni/Au multilayer film metal electrode is respectively 20nm/100nm/30nm/50nm, stripping technology is adopted to prepare the metal electrode in source region and drain region, and in blanket of nitrogen, short annealing process (annealing temperature 825 DEG C is carried out to metal electrode, annealing time 30s), to form Ohmic electrode.
(3), again at crystal column surface spin coating photoresist, and oriented the position in grid region by alignment light carving method after, wafer is put into reactive ion etching machine, use CF
4as reacting gas, carry out F ion injection to grid region, form fixed charge layer dielectric film, process conditions are: injecting power 60W, operating air pressure 20mTorr, injection length 300s.
(4), again by wafer molecular beam epitaxy (MBE) is put into, by the Al that normal temperature deposition 10nm is thick
2o
3gate medium, as insulative cap film.
(5), adopt electron beam evaporation at crystal column surface deposition Ni/Au metallic film again, the thickness of Ni/Au metallic film is respectively 100nm/50nm, and form grid metal electrode by stripping technology, under nitrogen atmosphere annealing in process (annealing temperature 400 DEG C, annealing time 10min.) is carried out to whole wafer again.
By above processing step, this F:Al with high threshold voltage just can be have developed
2o
3the enhancement mode GaN MISHEMT device of gate medium, in order to compare, has also made the enhancement mode GaN MISHEMT of naked cap layers gate medium, adopts HP4284A LCR instrument to carry out electrical properties test to these developed two kinds of devices.
Fig. 6 gives the impact of this insulative cap on device transfer characteristic, can find out: the enhancement mode GaN MISHEMT device threshold voltage of naked cap layers gate medium is+0.5V, and has the enhancement mode GaN MISHEMT device threshold voltage of insulative cap gate medium to reach+2.6V.Adopt the enhancement device that this patent method is produced, not only have higher threshold voltage, and maximum source and drain saturation current reaches 350mA/mm, maximum saturation mutual conductance reaches 55mS/mm.
Claims (5)
1. high threshold voltage gallium nitride enhancement transistor structure, comprise substrate, GaN and AlGaN layer and insulated gate dielectric layer from bottom to top, it is characterized in that, described insulated gate dielectric layer comprises insulating tunnel layer, fixed charge layer and insulative cap, fixed charge layer is arranged at above insulating tunnel layer or is embedded in insulating tunnel layer top, the top of fixed charge layer is provided with insulative cap, is grid metal electrode above insulative cap; Insulating tunnel layer is identical with insulative cap material.
2. high threshold voltage gallium nitride enhancement transistor structure as claimed in claim 1, it is characterized in that, the material of described insulating tunnel layer and insulative cap is Al
2o
3, SiO
2, HfO
2, HfTiO, ZrO
2or SiNO.
3. prepare the method for high threshold voltage gallium nitride enhancement transistor structure as claimed in claim 1, it is characterized in that, comprise the steps:
(1), on a sapphire substrate prepare AlGaN/GaN heterojunction material, i.e. wafer, deposits one deck Al at crystal column surface
2o
3film, as insulating tunnel layer;
(2) metal electrode in source region and drain region, is prepared;
(3), at crystal column surface spin coating photoresist, and oriented the position in grid region by alignment light carving method after, wafer is put into reactive ion etching machine, use CF
4as reacting gas, F ion injection is carried out to grid region, form fixed charge layer;
(4), at the Al that crystal column surface normal temperature deposition 10nm is thick
2o
3gate medium, as insulative cap;
(5), at crystal column surface deposition Ni/Au metallic film, the thickness of Ni/Au metallic film is respectively 100nm and 50nm, and forms grid metal electrode by stripping technology, then carries out annealing in process to whole wafer under nitrogen atmosphere.
4. method as claimed in claim 3, it is characterized in that, described step (2) is: be coated with Al
2o
3the AlGaN/GaN heterojunction material surface spin coating photoresist of film, orients the position in source region and drain region by photoetching, then uses the HF solution of 1:100 by the Al of source region and position, drain region
2o
3film etches away; Adopt electron beam evaporation technique depositing Ti/Al/Ni/Au multilayer film metal electrode, the thickness of Ti/Al/Ni/Au multilayer film metal electrode is respectively 20nm/100nm/30nm/50nm, stripping technology is adopted to prepare the metal electrode in source region and drain region, and in blanket of nitrogen, short annealing process is carried out to metal electrode, annealing temperature 825 DEG C, annealing time 30s, to form ohmic contact.
5. method as claimed in claim 3, it is characterized in that, described step (3) ~ (5) are:
(3), at crystal column surface spin coating photoresist, and oriented the position in grid region by alignment light carving method after, wafer is put into reactive ion etching machine, use CF
4as reacting gas, F ion injection is carried out to grid region, form fixed charge layer, injecting power 60W, operating air pressure 20mTorr, injection length 300s;
(4), by wafer molecular beam epitaxy is put into, by the Al that normal temperature deposition 10nm is thick
2o
3gate medium, as insulative cap;
(5), adopt electron beam evaporation at crystal column surface deposition Ni/Au metallic film, the thickness of Ni/Au metallic film is respectively 100nm and 50nm, and form grid metal electrode by stripping technology, under nitrogen atmosphere annealing in process is carried out to whole wafer again, annealing temperature 400 DEG C, annealing time 10min.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210172341.8A CN102709322B (en) | 2012-05-30 | 2012-05-30 | High-threshold-voltage gallium nitride enhanced transistor structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210172341.8A CN102709322B (en) | 2012-05-30 | 2012-05-30 | High-threshold-voltage gallium nitride enhanced transistor structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102709322A CN102709322A (en) | 2012-10-03 |
| CN102709322B true CN102709322B (en) | 2015-07-01 |
Family
ID=46901970
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210172341.8A Expired - Fee Related CN102709322B (en) | 2012-05-30 | 2012-05-30 | High-threshold-voltage gallium nitride enhanced transistor structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102709322B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9704959B2 (en) | 2013-05-21 | 2017-07-11 | Massachusetts Institute Of Technology | Enhancement-mode transistors with increased threshold voltage |
| CN106206309A (en) * | 2015-05-07 | 2016-12-07 | 中国科学院苏州纳米技术与纳米仿生研究所 | Secondary epitaxy p-type nitride realizes method and enhancement mode HEMT of enhancement mode HEMT |
| CN105428314A (en) * | 2015-12-26 | 2016-03-23 | 中国电子科技集团公司第十三研究所 | Preparation method for GaN-based HEMT device |
| CN110571267B (en) * | 2019-08-13 | 2024-09-27 | 中山市华南理工大学现代产业技术研究院 | Having NiOXMIS-HEMT device of protective layer and preparation method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184943A (en) * | 2011-04-18 | 2011-09-14 | 电子科技大学 | Enhanced AlGaN/GaN HEMT (High Electron Mobility Transistor) device and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6690042B2 (en) * | 2000-09-27 | 2004-02-10 | Sensor Electronic Technology, Inc. | Metal oxide semiconductor heterostructure field effect transistor |
| US8183595B2 (en) * | 2005-07-29 | 2012-05-22 | International Rectifier Corporation | Normally off III-nitride semiconductor device having a programmable gate |
-
2012
- 2012-05-30 CN CN201210172341.8A patent/CN102709322B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184943A (en) * | 2011-04-18 | 2011-09-14 | 电子科技大学 | Enhanced AlGaN/GaN HEMT (High Electron Mobility Transistor) device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102709322A (en) | 2012-10-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2020221222A1 (en) | High-threshold-voltage normally-off high-electron-mobility transistor and preparation method therefor | |
| CN105304689B (en) | AlGaN/GaN HEMT devices and production method based on fluorinated graphene passivation | |
| CN102938413B (en) | Algan/gan heterojunction enhanced device and manufacturing method thereof | |
| CN102386223B (en) | High-threshold voltage gallium nitride (GaN) enhancement metal oxide semiconductor heterostructure field effect transistor (MOSHFET) device and manufacturing method | |
| CN102945860B (en) | AlGaN/GaN heterojunction enhancement-mode device with in-situ SiN cap layer and production method thereof | |
| CN102184943A (en) | Enhanced AlGaN/GaN HEMT (High Electron Mobility Transistor) device and manufacturing method thereof | |
| CN109004017B (en) | HEMT device with polarization junction longitudinal leakage current barrier layer structure and preparation method thereof | |
| CN104269433B (en) | Gallium-nitride-based enhancement type heterojunction field effect transistor with composite channel layer | |
| CN104201104A (en) | Manufacturing method for gallium nitride-based enhanced device | |
| CN104167445B (en) | GaN-based enhancement/depletion mode heterojunction field effect transistor with buried gate structure | |
| CN109659355A (en) | Normally-off gallium oxide field-effect transistor structure and preparation method | |
| CN102945859A (en) | GaN heterojunction HEMT (High Electron Mobility Transistor) device | |
| CN104952938A (en) | Gallium nitride heterojunction MIS grid-control power diode and manufacturing method thereof | |
| CN109873034A (en) | Normally-off HEMT power device of deposit polycrystalline AlN and preparation method thereof | |
| CN104393040A (en) | HEMT device with charged media | |
| CN105355659A (en) | Trench-gate AlGaN/GaN HEMT device structure and manufacturing method | |
| CN109888013A (en) | The enhanced GaN base HEMT device and preparation method thereof of magnesium doping preparation | |
| CN102709322B (en) | High-threshold-voltage gallium nitride enhanced transistor structure and preparation method thereof | |
| CN105448964A (en) | Composite stepped field plate trench gate AlGaN/GaN HEMT high-voltage device structure and manufacturing method therefor | |
| CN104037218A (en) | High-performance AlGaN/GaN HEMT high-voltage element structure based on polarization effect and manufacturing method | |
| CN105448975A (en) | Composite step field plate grooved-gate high electron mobility transistor (HEMT) high-voltage device and fabrication method thereof | |
| CN107154426A (en) | A kind of device architecture and implementation method for improving silicon substrate GaN HEMT breakdown voltages | |
| US20220102540A1 (en) | Gan-hemt device with sandwich structure and method for preparing the same | |
| CN103745990B (en) | Depletion-mode AlGaN/GaN MISHEMT high tension apparatus and preparation method thereof | |
| CN104064595B (en) | A kind of enhanced AlGaN based on slot grid structure/GaN MISHEMT device architecture and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150701 Termination date: 20180530 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |