TW492158B - Capacitor structure in copper process - Google Patents

Abstract

A method for forming a capacitor with metal layer/dielectric layer/metal layer structure in the copper metal dual-layered damascene structure is disclosed in the present invention. At first, a substrate is provided, and a copper metal layer is deposited in the upmost dielectric layer by using a damascene method. Then, a silicon nitride layer is deposited on the substrate and is followed by depositing low k dielectric material on the silicon nitride layer. Another silicon nitride layer is deposited on the dielectric layer for use as a hard mask of the dual damascene structure. The metal layer, thin dielectric layer, and metal layer are sequentially deposited to complete the capacitor stack. The etching for defining the upper and the lower electrodes are performed, in which the length of the lower electrode is larger than that of the upper electrode such that it is convenient to connect with the subsequent trenches. When defining the lower electrode, different conducting layers can be programmed and formed at the same time for use as the resistors. Finally, the dual damascene region, the region for connecting both upper and lower electrodes of the capacitor, and the region for connecting the resistor are etched to complete the production of the capacitor.

Description

492158 A7 _B7_ V. Description of the Invention () This case is an addendum to the patent application No. 8 8 1 2006 1 entitled "Capacitor Structure in Integrated Circuit Manufacturing Process". The invention relates to a capacitor structure for forming a metal electrode in a copper metal process and a method for manufacturing the same. FIELD OF THE INVENTION: The present invention relates to a semiconductor process, and in particular to a method for forming a metal layer in a copper metal double-layered mosaic structure. / Dielectric layer / metal layer capacitor method. Background of the invention: In recent years, the trend of the semiconductor manufacturing industry is to reduce the size of memory cells to increase the degree of accumulation and the memory capacity of memory chips. When the line width of semiconductors continues to explode from sub-microns, the Characteristics still need to be maintained. For example, the minimum amount of stored charge required by a capacitor in a dynamic random access memory (DRAM) remains constant, so that the high reliability of the memory can be maintained. (Please read the precautions on the back before filling in this page) Γ-· _1 n ϋ n US n · if 'in tn m chain 丨 Printing device of employee cooperative of employee of Intellectual Property Bureau of Ministry of Economic Affairs The description must be full, so that the example will be supplemented. , As Kahua said. Often changed, small pieces of the same element need to be subtracted, and the multi-conductor sounds like a half-capacity shadow, which can be transformed into a 5L set. The radiator product makes the sub-capacity, and the high-granularity α decreases. To date, this paper is easy to read and understand. The paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm). 492158 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs.

A7 B7 V. Description of the invention () National Method No. 5457065, "Method of MANUFACTURING A NEW DRAM CAPACITOR STRUCTURE HAVING INCREASED CAPACITANCE" disclosed by Cheng et al. "Is a shape, stacked capacitor to increase the capacitance value structure. The other types of capacitors, such as trench capacitors or crown capacitors, are also used to increase the area of the capacitor to improve its performance.

The increase in the storage capacitance value can be achieved by increasing the capacitor area as described above, or by making the dielectric layer thin and using a high dielectric constant dielectric layer. However, due to charge leakage (such as Fowler-Nordheim Tunnel effect) and the quality of the dielectric layer, so there are certain restrictions on thinning the capacitor, and materials that can replace silicon dioxide π%) such as% 〇5 or BST = are not used now High dielectric constant materials (many people are still studying materials with higher dielectric constants). In addition, the traditional capacitor production 'whether it is using AM or No.' and it can be used to include analog / volume ts (digital / analog, and digital signal) (4))) usually use Fuyuyu 4 Miscellaneous silicon is used as the upper and lower private plates of the capacitor. However, when the accumulation degree of the lane conductor is increased, and the operation speed of the element is accelerated, the traditional doping 祯 a 访 / 八 + a ', the structure #I $ 日 日; 丨 electric layer / doped complex Silicon capacitors are required for A # 4 + r. At the same time, this type of semiconductor material will generate a depletion mode of the interface due to the voltage applied by%, due to 10 X 297 mm) -nnn I nnn-n —I nnnn a & J1 n -I- nnunn I nnn If nnn-(Please read the precautions on the back before filling this page) A7 V. Description of the invention (which affects the reliability of capacitors) However, in recent years, there have been 'people researching capacitors for metal electrode plates' such as The first A — D 冃 is corrected by-σσ Tune does not, that is, the use of aluminum metal as an electric valley for the upper and lower electrode plates respectfully + stand on the surface without thinking. In the inner metal dielectric layer (IMD) Aluminium metal layer on top of 100]] After 110 ', the dielectric layer 12 and the aluminum metal layer 130 are deposited to form a capacitor. The connector is deposited with the dielectric layer 140 and the plug is connected to the capacitor. On external snow circuits. Because I Lu metal is less susceptible to oxidation,

And it can form capacitor structure with metal / intermediate temperature / such as human M layer / aluminum metal. Although the most important Iy w wire material in today's integrated circuits is the base material, the pure | g has a resistance coefficient of about 2.7 micro-ohm · cm, and at the same time, it adds silicon and copper to form alloy materials. The purpose of using aluminum alloy is to improve the anti-electromigration (eiectromi & ration resistance) ability of pure aluminum substrate. This prevents the aluminum and silicon interfaces from diffusing at the fusion temperature. Of course, in order to effectively reduce the resistivity, copper metal is the best choice, because the resistivity of copper material is about 17 micro-ohm-cm, which is much smaller than air material. At the same time, the resistance of copper metal itself to electrical migration is better than that of aluminum material, so it is a predictable conductor material. However, 'due to the shortcomings of copper metal that are easy to oxidize and not easy to etch, copper wires are formed by dual damascene (dual damascene instead of traditional plasma etching / because the direct deposition of an oxide layer on copper metal will consume copper material') and Due to the rapid diffusion effect and leakage current, the capacitor structure of the above aluminum metal electrode plate is not suitable for the copper metal process of double-layer mosaic structure. Therefore, there is still a need to have a paper standard for copper metal electrode plates that conforms to Chinese national standards. (CNS) A4 specification (21〇X 297 issued) ------ i— TV --- · (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs- ------- ^ -------------- 1 嬅 · A7 Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of Invention () Private Valley Structure and Manufacturer's Demand. &Amp; The purpose and summary of the invention of the integrated circuit manufacturing process of the next generation: In view of the above invention, the capacitors in the circuit are usually r / ?, traditional memory or mixed signal ^ Integrated circuits are highly integrated and doped with f On the evening, The lower electrode plate, however, develops in the direction of the dagger formed by the metal material, and the operating speed of the element is also increased as the material of the container electrode plate is the best choice. Therefore, the main part of the present invention is ^% One of the, is to form the metal g & 'to achieve a highly reliable capacitor in the copper process. The purpose of this ^ ^ ^ ^-^ ^ purpose' is only in the formation of the via hole (via) stage 10% stacking of capacitors, avoiding copper metal in the process of capacitors ^ / months to remove impurities, etching, or exposure to copper metal in wet, clean and affect the electrical properties of the electronic pen. According to the purpose described above The present invention first provides a semiconductor substrate with active and passive components, and even forms multiple metal interconnects. Then, a low-k dielectric material layer is deposited on the uppermost layer of the substrate to become an internal metal dielectric layer (Inter -Metal Dielectric (IMD). When using traditional lithography ---- I-^ --XI-- -------- ^ · I I ------ (Please read the note on the back first (Please fill in this page for matters) Printed by Consumer Cooperative 492158

V. Description of the invention (After the etching method is used to form a damascene region on the dielectric layer, a steel metal is deposited by Electrochemical Deposition (ECD) or sputtering, and then it is planarized by chemical mechanical polishing. Before the formation of the copper metal, titanium nitride or titanium tungsten alloy can be deposited as a barrier layer. Next, a silicon nitride layer is deposited on the substrate, and then a low-k dielectric material such as silica or appropriate doping is used. A heterogeneous silicon dioxide material is deposited on the silicon nitride layer. Then, another layer of nitrided silicon is deposited on the dielectric layer as a hard mask of a double-layer mosaic structure. In one embodiment, this The thickness of the silicon nitride layer is about 1 500 angstroms. Then, a metal layer of aluminum metal, nitride button, titanium nitride, or a combination thereof is deposited on the silicon nitride layer to a thickness of about 500. At about 1 500 Angstroms, a dielectric layer with a thickness of about 40 to Angstroms is deposited on top of this metal layer. Finally, a metal layer of the same aluminum metal, nitride button, nitride nitride, or a combination thereof is deposited. The capacitor stack is completed on top of the dielectric layer. When the capacitors are stacked After the completion of the process, 'the definition of the upper and lower electrode plates is engraved', and the length of the lower electrode plate will be longer than that of the upper electrode plate, so as to be connected with the subsequent wire layer trenches. At the same time, when defining the lower electrode plate, it can be called to form different The conductive layer is used as a resistor. Finally, the above silicon nitride hard mask etching pattern is also patterned to facilitate the double-layer mosaic structure. After that, a layer of dielectric material is deposited to define the capacitor and the resistor. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)

• I ---- ^ --- 1— — III Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed M2158 A7 ~ ^ ---- B7____ 5. Description of the invention () Substrate And then etch out the double-layered mosaic area, the area connected to the upper and lower electrode plates of the capacitor, and the area connected to the resistor, and then fill the copper metal with an electrochemical deposition method to complete the metal layer / dielectric layer of the invention > Metal layer capacitor structure and manufacturing method. Since the capacitor of the present invention is formed at the intermediate dielectric layer stage, it can avoid contact with the copper metal wire of the bottom layer, which causes the exposure of the steel metal to the external environment, and the electrical property of the capacitor can be improved. Additional resistors can be formed to facilitate circuit designer planning. Brief description of the drawings: The preferred embodiment of the present invention will be described in more detail in the following explanatory texts with the following figures, where: The first A-D diagram is a capacitor with a metal formed according to the traditional method of P ► A schematic cross-sectional view of an electrode plate. A second view is a cross-sectional view of a copper metal layer formed in accordance with the present invention. A third view is a dielectric layer, a metal layer, an oxide layer, and a metal layer on a copper metal layer formed in accordance with the present invention. Schematic cross-section of layer stacking. The fourth figure is the engraving and forming of low-k dielectrics according to the present invention. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (please read the back first) Please note this page and fill in this page again) -------- Order · ---- Line. 492158 A7 B7 V. Description of the invention (Sectional schematic diagram of the layer; The fifth figure shows the double-inlay formation of the copper metal layer according to the present invention Structure and cross-section / surface schematic diagram of capacitor connection. Detailed description of the invention: The method disclosed in the present invention is a method for forming a metal layer / dielectric layer / metal layer capacitor structure in a dual damascene structure of copper metal. As capacitors are widely used in integrated circuits, capacitors used to store signals in dynamic random access memory (DRAM), or capacitors in integrated circuits of mixed signal circuits, etc. In order to meet the new generation of capacitors, ^… J, and to simplify the manufacturing process, the capacitor manufacturing method of the present invention is available. The detailed description of s% in this post will be as follows (please read the precautions on the back before filling (This page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, refer to the second figure, which is a schematic cross-sectional view of a copper-inlaid metal layer formed in accordance with the present invention. The substrate 200 will be A semiconductor wafer and active and passive components formed on the semiconductor wafer, or multilevel interconnects are formed when the component is completed. However, in this figure, for simplicity, only the substrate 2 is used. 00 is indicated. In the multi-metal interconnection process, a layer of a dielectric material with a low-k value is formed between each wire layer, for example, silicon oxide (si〇2) can be used. Applicable paper size: Applicable to China National Standard (CNS) A4 specification (210 X 297 mm, i · _1 nnnnn 1 11 I 1 ^ 9 HI »19 n milk 2158 A7 B7 V. Description of the invention (field-doped silicon oxide, etc.) This dielectric isolation layer is also called internal metal dielectric layer (IMD). First, the traditional lithography and etching process is used to etch the 'line area' in this layer and use the chemical deposition method. (E1 DePsltlon, ECD) or Dc magnetron sputtering method to deposit copper metal area 2i0. In addition, before the copper metal is formed, it can be performed first by means of, for example, DC magnetron quenching > Metals such as titanium nitride (TiN) or titanium tungsten (Tiw) alloys (not shown in the figure), such conductive materials are called barrier layers, the purpose is to avoid the Interface phenomenon and increase its adhesion. Meanwhile, in this figure, for convenience of explanation, the connection plugs of the copper metal layer 210 and the underlying metal layer are not shown. After the copper metal layer 210 is filled into the mosaic area, it can be fully planarized by chemical mechanical polishing (CMp), and the previously deposited barrier layer is used as the end point of the polishing. (Please read the precautions on the back before filling out this page) _f ------- 1 order ----- line _ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Refer to the third picture 'This picture is in accordance with The invention is a schematic cross-sectional view of a capacitor stack structure. After the copper-inlaid metal region 21 is formed, a silicon nitride layer 220 is then deposited on the substrate 200 and the copper metal layer 21 by, for example, plasma enhanced chemical vapor deposition (PECVD), and the thickness is maintained at About 500 to 1,500 angstroms. Then, a layer of low-k dielectric material 230 is deposited on the nitrided layer 22. The dielectric material 23 can be a dioxygen paper. The paper is a Chinese standard (CNS) A4 specification (210 X 297 mm). ) 492 changed. H said that it was supplemented by A7 and B7. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention () Siliconized material, or composed of appropriately doped silicon dioxide material, as the isolation material between the wires. For use (IMD layer). The silicon dioxide layer can be deposited by PECVD. In one embodiment, the thickness of the dielectric material is about 2000 to 8000 angstroms. After the dielectric material 230 is formed, a silicon nitride (Si3N4) layer 240 is deposited thereon by the same PECVD method. In the present invention, the silicon nitride layer 240 is used as a hard mask for etching the bottom dielectric layer 230 in a double-layered damascene structure, and in one embodiment, the thickness of the silicon nitride layer 240 About 500 to 1,500 Angstroms. After the dielectric layer is deposited, a metal layer 250 of aluminum metal, tantalum nitride, titanium nitride, or a combination thereof is deposited on the silicon nitride layer 240 by magnetron DC sputtering. In one embodiment, the thickness of the metal layer is about 500 to 1500 angstroms, and it can be changed as needed. A thin dielectric layer material 260 is then deposited on the metal layer 250, for example, using PECVD or the like. The thickness of the dielectric layer 260 may be between about 40 and 100 angstroms. The dielectric layer 260 may be made of a high dielectric constant material such as a silicon oxide / silicon nitride layer, a silicon oxide / silicon nitride / silicon oxide layer, Ta205, or BaTi03. And other materials. This thin or high dielectric constant dielectric layer will increase the capacitance stored in the capacitor. After the dielectric layer 260 is formed, a second metal layer is then deposited. The paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 g) (Please read the precautions on the back before filling this page) JI- ------- Order --------- Line Win

492158. V. Description of the invention (270), this metal layer can also be deposited with a metal layer of aluminum metal, nitride group, titanium nitride, or a combination thereof by a magnetron DC sputtering method, and in one embodiment, ' The thickness of this metal layer is about 500 to 1500 Angstroms. Since the via hole of the subsequent connection capacitor is also a copper metal layer, this type of material can also be used as a metal material to increase adhesion and isolation. Refer to the fourth figure, which is a schematic cross-sectional view of an etched capacitor according to the present invention. After the capacitor stack is formed, the process of defining the upper and lower electrode plates will be performed. At this moment, since the capacitor structure of the metal layer / dielectric layer / metal layer is built on the inner metal dielectric layer, the process can be easily performed. For example, after a patterned photoresist layer is formed on the capacitor stack (not shown in the figure), the stack layer is etched by an anisotropic etching technique such as a dry ion etching technique such as reactive ion etching (RIE), and the Fluorine or chlorine-containing plasma. In order to connect the upper electrode plate 270 and the lower electrode plate 250, it is necessary to divide and etch it twice, and the length of the lower electrode plate 250 formed as shown in the figure is larger than the length of the upper electrode plate 270. ------- Ί --- ^ ---------- Order --------- (Please read the precautions on the back before filling this page) The container capacity is engraved with 0. It is left under the printed layer of the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and is engraved. The other steps are the same. On the area, it touches the non-layer bottom of the equal layer to break up, and the exposed air mask is exposed to the exposure technique, and t) is used to create an etched layer and a π-resistance shadow. After the layer was passed, the light was blocked, and the required area was also used. The plan constitutes the application of the Chinese National Standard (CNS) A4 specification (210 X 297 cm) to this paper size.% Correction

V. Description of the Invention (492158) Contact openings of the silicon nitride layer 240 formed by the etch method 492158 After the openings of the silicon nitride layer 240 are formed, the patterned photoresist layer is first stripped in two ways: dry and wet. The chemical fluorine phase method is used to scramble the silicon layer 24o, the conductive layer 25o, and the capacitor stack plating layer to form a second low-k dielectric material layer 280. This dielectric material 28 may also be composed of silicon dioxide material 'or a properly doped silicon dioxide material as an isolation material between the wires. In one embodiment, the silicon dioxide layer can be deposited by a PECVD method and has a thickness of about 2000 to 8000 angstroms. Refer to the fifth figure, which is a schematic cross-sectional view of a copper metal double-layer mosaic structure formed according to the present invention. Next, another patterned photoresist layer (not shown in the figure) is deposited on the dielectric layer 28 and the double-layered damascene region of the bottom layer and the region connecting the upper and lower electrode plates of the capacitor are exposed. To etch a silicon oxide layer or a silicon nitride layer, a plasma containing carbon fluoride, such as CHh, or C3F8, can be used to provide a reaction gas of carbon atoms and fluorine atoms, and the interlayer in the double-layer drum region电 层 28。 Electric layer 28. The top patterned photoresist layer is used as the etching mask, and the silicon nitride | 240 is used as the etching stop layer, and the dielectric layer ⑶ is the patterned silicon nitride layer 240 as the etching mask, and the bottom layer is used. In short: the siliconized layer 2 2 0 serves as an etch stop layer. When the last name is engraved, a ditch connecting the upper and lower electrode plates will be formed (or the size of this paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 meals)) -------- Order ----- ---- f Please read the phonetic on the back? Matters before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 492158

The Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed a letter of explanation () wire area) patterns 290 and 300, mosaic area 310, and double-layer mosaic area 320, etc., and then copper metal was filled in the trench pattern by, for example, electrochemical deposition. 290 and 300, mosaic region 310, and double mosaic region 320. In this deposition process, the lower electrode plate 250 of the capacitor is connected by a trench of number .00, and the upper electrode plate 270 is connected by a channel of number 290. The inlaid area 3 and 10 are connected through the conductive layer 250 and the double-layered inlaid area. 320 are connected to each other to form a resistance region. The capacitor structure and manufacturing method for forming a metal layer / dielectric layer / metal layer in a copper-metal double-layer mosaic structure according to the present invention will be applicable to capacitors in memories or capacitors in mixed signals. When the capacitor is formed at the intermediate dielectric layer stage, it can avoid contact with the underlying copper metal wires, which will cause the copper metal to be exposed to the external environment during etching, removing impurities, or wet cleaning. The capacitor's electricity will be affected. Sex can also be effectively improved. At the same time, during circuit design, it is also possible to use additional resistors when forming capacitors to facilitate circuit designers in planning multiple metal interconnects. As understood by those familiar with this technology, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; all others that are completed without departing from the spirit disclosed by the present invention Equivalent changes or modifications should be included in the scope of patent application described below. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ---------------------- Order -------- -(Please read the notes on the back before filling out this page) 492158

V. Description of the invention () Drawing number comparison description: 200 substrate 210 copper metal layer 220 silicon nitride layer 230 dielectric material 240 silicon nitride layer 250 metal layer / lower electrode plate 250, conductive layer 260 dielectric layer 270 metal layer / Upper electrode: plate 2 8 0 dielectric layer 290 ditch 300 ditch 3 10 inlay area 320 double inlay area Please read the notes on the back before filling out this page) Printed on the paper by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

492158 6. Scope of patent application Patent scope of patent application printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs: K kinds of capacitor structures located in the inner metal dielectric layer, the structure includes at least: semiconductor substrate 'the semiconductor substrate has copper metal wires; A dielectric layer, the first dielectric layer is located on the semiconductor substrate; a metal layer / second dielectric layer / second metal layer capacitor structure, the capacitor structure is located on the first dielectric layer The area of the second metal layer at the same time is larger than the area of the first metal layer; the third dielectric layer is formed on the first dielectric layer and the valley structure and forms A trench connecting the first metal layer and the second metal layer of the capacitor structure; and a steel metal layer, the copper metal layer is located in a double-layered mosaic structure formed by the first dielectric layer and the third dielectric layer . 2. The capacitor structure according to item 1 of the scope of patent application, wherein the above copper metal layer is formed by electro-chemical deposition (ECD) plating. 3. The capacitor structure according to item 1 of the scope of the patent application, wherein the first metal layer is selected from one of a metal cluster consisting of a metal, a nitride group, a titanium nitride, and a 14 combination. 14 (Please read the precautions on the back before filling out this page}, «II — — Line 丨 · Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 492158 A8 B8 C8 D8 6. Scope of patent application 4. If the scope of patent application is the first The capacitor structure according to item 1, wherein the second metal layer is one of metal clusters selected from the group consisting of aluminum metal, tantalum nitride, titanium nitride, or a combination thereof. 5. The capacitor structure according to item 1 of the scope of patent application Among them, the above-mentioned second dielectric layer is one of the clusters composed of silicon oxide / silicon nitride layer, silicon oxide / silicon nitride / silicon oxide layer, Ta205 and BaTi03 materials. The capacitor structure of item 1, wherein the thickness of said second dielectric layer is about 40 to 100 angstroms. 7.-A method for forming a capacitor in a metal dielectric layer, which method includes at least ... Depositing a first dielectric layer on the semiconductor substrate; depositing a first metal layer, a second dielectric layer, and a second metal layer on the first dielectric layer; etching the first dielectric layer A metal layer The second dielectric layer and the second metal layer form a capacitor structure, wherein the area of the second metal layer at the bottom is larger than the first metal layer; depositing a third dielectric layer on the capacitor and the first dielectric layer Above; This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) 492158 A8 B8 C8 D8 printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics, the scope of the patent application is to etch the third dielectric layer to form a trench connecting the first metal layer and the second metal layer of the capacitor, and simultaneously form the trench A dual-layer mosaic structure of the first dielectric layer and the third dielectric layer; and < depositing a copper metal layer in the dual-layer mosaic structure and the trench. 8. The method according to item 7 of the patent application scope, wherein the above copper metal layer is formed by electro-chemical deposition (ECD) plating. 9. The method according to item 7 of the patent application, wherein the first metal layer is one of a metal cluster selected from the group consisting of aluminum metal, tantalum nitride, titanium nitride, or a combination thereof. 10. The method according to item 7 of the scope of patent application, wherein the second metal layer is one of a metal cluster selected from the group consisting of aluminum metal, nitride button, titanium nitride, or a combination thereof. -& 11. The method according to item 7 of the scope of patent application, wherein the second dielectric layer is a oxide oxide layer / nitride stone layer, an oxide crushed / nitrided crushed / oxidized crushed layer, T05, BaTi03 One of the clusters of materials. 12. The method according to item 7 of the patent application, wherein the thickness of the second dielectric layer is about 40 to 100 angstroms. (Please read the precautions on the back before filling this page); · Order i I line 16 · This paper size applies to the national standard (CNS) A4 (210 X 297 mm) 492158 A8 B8 C8 D8 Patent scope 3 Act 7. -Y layer resistance " Electroforming around ΑΓ 巳 I is the same as the special one, please refer to the description of the etching of the layer gold (please read the precautions on the back before filling this page) nv I — Order --------- line 丨 # Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 7 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)